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-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini41
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt458
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini41
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt979
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini291
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt371
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini291
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt351
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini417
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt499
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini304
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt359
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini276
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout10
-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt406
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini41
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt492
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini41
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt950
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini291
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt290
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini291
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt296
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini417
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt353
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini304
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt316
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini276
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr3
-rwxr-xr-xtests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout12
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt441
52 files changed, 6464 insertions, 3591 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
index 6320b231e..fcd6df11a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -779,29 +780,36 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
-tXP=0
+tXP=6000
tXPDLL=0
-tXS=0
+tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
index 70f465dc7..321da6ba3 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:27
-gem5 executing on e108600-lin, pid 39611
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:43
+gem5 executing on e108600-lin, pid 28041
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 37822000 because target called exit()
+Exiting @ tick 41083000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index 5987fdc63..6227dc2b6 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000038 # Number of seconds simulated
-sim_ticks 38282000 # Number of ticks simulated
-final_tick 38282000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000041 # Number of seconds simulated
+sim_ticks 41083000 # Number of ticks simulated
+final_tick 41083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 159466 # Simulator instruction rate (inst/s)
-host_op_rate 159415 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 951356890 # Simulator tick rate (ticks/s)
-host_mem_usage 253388 # Number of bytes of host memory used
+host_inst_rate 172605 # Simulator instruction rate (inst/s)
+host_op_rate 172547 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1105034404 # Simulator tick rate (ticks/s)
+host_mem_usage 251288 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 6413 # Number of instructions simulated
sim_ops 6413 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory
system.physmem.bytes_read::total 34048 # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 23232 # Nu
system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory
system.physmem.num_reads::total 532 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 606864845 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 282534873 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 889399718 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 606864845 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 606864845 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 606864845 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 282534873 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 889399718 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 565489375 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 263271913 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 828761288 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 565489375 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 565489375 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 565489375 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 263271913 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 828761288 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 532 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 38177000 # Total gap between requests
+system.physmem.totGap 40972000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,9 +91,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 446 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 85 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
@@ -187,83 +187,93 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 83 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 377.831325 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 247.256857 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.629090 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18 21.69% 21.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 20 24.10% 45.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 11 13.25% 59.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 13.25% 72.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 3.61% 75.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 4 4.82% 80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 3.61% 84.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 4 4.82% 89.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9 10.84% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 83 # Bytes accessed per row activation
-system.physmem.totQLat 3252000 # Total ticks spent queuing
-system.physmem.totMemAccLat 13227000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 91 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 363.604396 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 235.588514 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 321.826485 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22 24.18% 24.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 22 24.18% 48.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13 14.29% 62.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 8 8.79% 71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5 5.49% 76.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 4 4.40% 81.32% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 3.30% 84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 8 8.79% 93.41% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6 6.59% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 91 # Bytes accessed per row activation
+system.physmem.totQLat 6580250 # Total ticks spent queuing
+system.physmem.totMemAccLat 16555250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6112.78 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 12368.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24862.78 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 889.40 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31118.89 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 828.76 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 889.40 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 828.76 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 6.95 # Data bus utilization in percentage
-system.physmem.busUtilRead 6.95 # Data bus utilization in percentage for reads
+system.physmem.busUtil 6.47 # Data bus utilization in percentage
+system.physmem.busUtilRead 6.47 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 437 # Number of row buffer hits during reads
+system.physmem.readRowHits 436 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 71761.28 # Average gap between requests
-system.physmem.pageHitRate 82.14 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2020200 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 77015.04 # Average gap between requests
+system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 264180 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 136620 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1956360 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 21270690 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 184500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 25871865 # Total energy per rank (pJ)
-system.physmem_0.averagePower 823.813565 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 196750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 30182000 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 347760 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 189750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1505400 # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 3932430 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 68640 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 13617300 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 928800 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 23977530 # Total energy per rank (pJ)
+system.physmem_0.averagePower 583.625643 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 32009500 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 39500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1300000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 2418500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 7463000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 29862000 # Time in different power states
+system.physmem_1.actEnergy 421260 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 208725 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1842120 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 20078820 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1230000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 25385970 # Total energy per rank (pJ)
-system.physmem_1.averagePower 808.341665 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2146500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 28481000 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 2005 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1239 # Number of conditional branches predicted
+system.physmem_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 4022490 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 174720 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 14292750 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 178080 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 24213345 # Total energy per rank (pJ)
+system.physmem_1.averagePower 589.365503 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 31744250 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 288500 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1300000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 7679500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 31350750 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 2003 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1238 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1607 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 1605 # Number of BTB lookups
system.cpu.branchPred.BTBHits 377 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 23.459863 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 23.489097 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 235 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 336 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectLookups 335 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 13 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 323 # Number of indirect misses.
+system.cpu.branchPred.indirectMisses 322 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 38282000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 76564 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 41083000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 82166 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6413 # Number of instructions committed
system.cpu.committedOps 6413 # Number of ops (including micro ops) committed
system.cpu.discardedOps 1095 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 11.938874 # CPI: cycles per instruction
-system.cpu.ipc 0.083760 # IPC: instructions per cycle
+system.cpu.cpi 12.812412 # CPI: cycles per instruction
+system.cpu.ipc 0.078049 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction
system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction
@@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 6413 # Class of committed instruction
-system.cpu.tickCycles 12651 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 63913 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles 12644 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 69522 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 103.736314 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 103.984752 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1990 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11.775148 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 103.736314 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.025326 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025326 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 103.984752 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.025387 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025387 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4591 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4591 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 1250 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1250 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits
@@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data 221 # n
system.cpu.dcache.demand_misses::total 221 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 221 # number of overall misses
system.cpu.dcache.overall_misses::total 221 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 7713000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7713000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9281000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9281000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 16994000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 16994000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 16994000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 16994000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8545500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8545500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 10429000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 10429000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 18974500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 18974500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 18974500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 18974500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1346 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1346 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
@@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.099955
system.cpu.dcache.demand_miss_rate::total 0.099955 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.099955 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.099955 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 80343.750000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 80343.750000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74248 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 74248 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 76895.927602 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 76895.927602 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 76895.927602 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 89015.625000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 89015.625000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 83432 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 83432 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 85857.466063 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 85857.466063 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 85857.466063 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -431,14 +441,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169
system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7617000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7617000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5452500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5452500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13069500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13069500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13069500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13069500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8449500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 8449500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6089500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 6089500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14539000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14539000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14539000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14539000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071322 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071322 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
@@ -447,31 +457,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076436
system.cpu.dcache.demand_mshr_miss_rate::total 0.076436 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076436 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.076436 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79343.750000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79343.750000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74691.780822 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74691.780822 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77334.319527 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 77334.319527 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88015.625000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88015.625000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83417.808219 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83417.808219 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86029.585799 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 86029.585799 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 174.445567 # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse 175.153182 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 2322 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 6.379121 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 174.445567 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.085178 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.085178 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 175.153182 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.085524 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.085524 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 5736 # Number of tag accesses
system.cpu.icache.tags.data_accesses 5736 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst 2322 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 2322 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 2322 # number of demand (read+write) hits
@@ -484,12 +494,12 @@ system.cpu.icache.demand_misses::cpu.inst 364 # n
system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
system.cpu.icache.overall_misses::total 364 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 28460500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 28460500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 28460500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 28460500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 28460500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 28460500 # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 30317500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 30317500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 30317500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 30317500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 30317500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 30317500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 2686 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 2686 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 2686 # number of demand (read+write) accesses
@@ -502,12 +512,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.135517
system.cpu.icache.demand_miss_rate::total 0.135517 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.135517 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.135517 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78188.186813 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 78188.186813 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 78188.186813 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 78188.186813 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 78188.186813 # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83289.835165 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 83289.835165 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 83289.835165 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 83289.835165 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 83289.835165 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -520,43 +530,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 364
system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28096500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 28096500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28096500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 28096500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28096500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 28096500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29953500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 29953500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29953500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 29953500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29953500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 29953500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135517 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.135517 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135517 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.135517 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77188.186813 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77188.186813 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77188.186813 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 77188.186813 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82289.835165 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82289.835165 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82289.835165 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 82289.835165 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 278.242026 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 279.180738 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 532 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.001880 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 174.459359 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 103.782667 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005324 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.003167 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.008491 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.152793 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 104.027945 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005345 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.003175 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.008520 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 422 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.016235 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
@@ -575,18 +585,18 @@ system.cpu.l2cache.demand_misses::total 532 # nu
system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses
system.cpu.l2cache.overall_misses::total 532 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5343000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5343000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27539000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 27539000 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7471500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 7471500 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 27539000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 12814500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 40353500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 27539000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 12814500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 40353500 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5980000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 5980000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29396000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 29396000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8304000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 8304000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 29396000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 14284000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 43680000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 29396000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 14284000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 43680000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses)
@@ -611,18 +621,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.998124 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73191.780822 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73191.780822 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75865.013774 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75865.013774 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77828.125000 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77828.125000 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 75852.443609 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75865.013774 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75825.443787 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 75852.443609 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81917.808219 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81917.808219 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80980.716253 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80980.716253 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86500 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86500 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82105.263158 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80980.716253 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84520.710059 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82105.263158 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -641,18 +651,18 @@ system.cpu.l2cache.demand_mshr_misses::total 532
system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4613000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4613000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23909000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23909000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6511500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6511500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23909000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11124500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 35033500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23909000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11124500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 35033500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5250000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5250000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25766000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25766000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7344000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7344000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25766000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12594000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 38360000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25766000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12594000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 38360000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses
@@ -665,25 +675,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63191.780822 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63191.780822 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65865.013774 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65865.013774 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67828.125000 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67828.125000 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65865.013774 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65825.443787 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65852.443609 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71917.808219 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71917.808219 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70980.716253 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70980.716253 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70980.716253 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74520.710059 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72105.263158 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
@@ -709,18 +719,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 532 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 38282000 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 41083000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 459 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
@@ -741,9 +751,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 532 # Request fanout histogram
-system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2826500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 7.4 # Layer utilization (%)
+system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2825000 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 6.9 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 81c1646b5..dc66b2c5c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -727,29 +728,36 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
-tXP=0
+tXP=6000
tXPDLL=0
-tXS=0
+tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index b4b146baf..27b942df1 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:27
-gem5 executing on e108600-lin, pid 39605
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:49
+gem5 executing on e108600-lin, pid 28099
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 22019000 because target called exit()
+Exiting @ tick 23776000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
index 1341b2242..518b46438 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000022 # Number of seconds simulated
-sim_ticks 22248000 # Number of ticks simulated
-final_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000024 # Number of seconds simulated
+sim_ticks 23776000 # Number of ticks simulated
+final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114507 # Simulator instruction rate (inst/s)
-host_op_rate 114481 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 398824007 # Simulator tick rate (ticks/s)
-host_mem_usage 254412 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 93889 # Simulator instruction rate (inst/s)
+host_op_rate 93856 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 349385939 # Simulator tick rate (ticks/s)
+host_mem_usage 252568 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6385 # Number of instructions simulated
sim_ops 6385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory
system.physmem.bytes_read::total 31040 # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu
system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory
system.physmem.num_reads::total 485 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 485 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 22109000 # Total gap between requests
+system.physmem.totGap 23381000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,11 +91,11 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
@@ -187,104 +187,115 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation
-system.physmem.totQLat 4498250 # Total ticks spent queuing
-system.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation
+system.physmem.totQLat 8009750 # Total ticks spent queuing
+system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.90 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.20 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 394 # Number of row buffer hits during reads
+system.physmem.readRowHits 395 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45585.57 # Average gap between requests
-system.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 48208.25 # Average gap between requests
+system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ)
-system.physmem_0.averagePower 871.044055 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ)
+system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ)
+system.physmem_0.averagePower 621.784975 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
+system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states
+system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ)
-system.physmem_1.averagePower 850.487920 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 2853 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups
+system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ)
+system.physmem_1.averagePower 629.216130 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
+system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 2854 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups
system.cpu.branchPred.BTBHits 713 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups.
+system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions.
+system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits 25 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 436 # Number of indirect misses.
+system.cpu.branchPred.indirectMisses 437 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 2261 # DTB read hits
+system.cpu.dtb.read_hits 2252 # DTB read hits
system.cpu.dtb.read_misses 48 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 2309 # DTB read accesses
-system.cpu.dtb.write_hits 1039 # DTB write hits
+system.cpu.dtb.read_accesses 2300 # DTB read accesses
+system.cpu.dtb.write_hits 1038 # DTB write hits
system.cpu.dtb.write_misses 28 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 1067 # DTB write accesses
-system.cpu.dtb.data_hits 3300 # DTB hits
+system.cpu.dtb.write_accesses 1066 # DTB write accesses
+system.cpu.dtb.data_hits 3290 # DTB hits
system.cpu.dtb.data_misses 76 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 3376 # DTB accesses
-system.cpu.itb.fetch_hits 2294 # ITB hits
+system.cpu.dtb.data_accesses 3366 # DTB accesses
+system.cpu.itb.fetch_hits 2295 # ITB hits
system.cpu.itb.fetch_misses 27 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2321 # ITB accesses
+system.cpu.itb.fetch_accesses 2322 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -298,236 +309,236 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 44497 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 47553 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 16557 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2853 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 2294 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2449 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2480 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename
+system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2476 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 10787 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 37 26.24% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2475 22.97% 89.69% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1111 10.31% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10787 # Type of FU issued
-system.cpu.iq.rate 0.242421 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 140 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 10776 # Type of FU issued
+system.cpu.iq.rate 0.226610 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 141 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 84 # number of nop insts executed
-system.cpu.iew.exec_refs 3386 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1643 # Number of branches executed
-system.cpu.iew.exec_stores 1077 # Number of stores executed
-system.cpu.iew.exec_rate 0.231544 # Inst execution rate
-system.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 9761 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 5150 # num instructions producing a value
-system.cpu.iew.wb_consumers 7013 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.219363 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_refs 3376 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1642 # Number of branches executed
+system.cpu.iew.exec_stores 1076 # Number of stores executed
+system.cpu.iew.exec_rate 0.216390 # Inst execution rate
+system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 9755 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 5155 # num instructions producing a value
+system.cpu.iew.wb_consumers 7025 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle
system.cpu.commit.committedInsts 6402 # Number of instructions committed
system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -574,47 +585,47 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 26146 # The number of ROB reads
-system.cpu.rob.rob_writes 27511 # The number of ROB writes
+system.cpu.rob.rob_reads 26790 # The number of ROB reads
+system.cpu.rob.rob_writes 27482 # The number of ROB writes
system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6385 # Number of Instructions Simulated
system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 6.968990 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.143493 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 12938 # number of integer regfile reads
-system.cpu.int_regfile_writes 7444 # number of integer regfile writes
+system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 12923 # number of integer regfile reads
+system.cpu.int_regfile_writes 7437 # number of integer regfile writes
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits
-system.cpu.dcache.overall_hits::total 2407 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits
+system.cpu.dcache.overall_hits::total 2402 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses
@@ -623,43 +634,43 @@ system.cpu.dcache.demand_misses::cpu.data 537 # n
system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses
system.cpu.dcache.overall_misses::total 537 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits
@@ -677,138 +688,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 173
system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses
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@@ -827,18 +838,18 @@ system.cpu.l2cache.demand_misses::total 485 # nu
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-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses)
@@ -863,18 +874,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997942 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -893,18 +904,18 @@ system.cpu.l2cache.demand_mshr_misses::total 485
system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses
@@ -917,25 +928,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution
@@ -961,18 +972,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 413 # Transaction distribution
system.membus.trans_dist::ReadExReq 72 # Transaction distribution
system.membus.trans_dist::ReadExResp 72 # Transaction distribution
@@ -993,9 +1004,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 485 # Request fanout histogram
-system.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.6 # Layer utilization (%)
+system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 10.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
index b9631a6d8..067911f85 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=6
eventq_index=0
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestToDir=system.ruby.dir_cntrl0.requestToDir
responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
enable_prefetch=false
eventq_index=0
l1_request_latency=2
@@ -319,6 +346,10 @@ l2_select_num_bits=0
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
optionalQueue=system.ruby.l1_cntrl0.optionalQueue
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
prefetcher=system.ruby.l1_cntrl0.prefetcher
recycle_latency=10
requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -447,17 +478,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
l2_request_latency=2
l2_response_latency=2
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -574,18 +615,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
ruby_system=system.ruby
topology=Crossbar
@@ -748,42 +794,216 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
router_id=0
virt_nets=3
@@ -875,8 +1095,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
router_id=1
virt_nets=3
@@ -968,8 +1194,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
router_id=2
virt_nets=3
@@ -1061,8 +1293,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
router_id=3
virt_nets=3
@@ -1195,9 +1433,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
index 838211534..1a88d47ac 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alp
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 22:00:08
-gem5 started Mar 14 2016 22:01:20
-gem5 executing on phenom, pid 28860
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Oct 13 2016 20:28:06
+gem5 started Oct 13 2016 20:28:31
+gem5 executing on e108600-lin, pid 8233
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 121535 because target called exit()
+Exiting @ tick 129075 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
index d17f0dc2a..66e7aabe9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000122 # Number of seconds simulated
-sim_ticks 121535 # Number of ticks simulated
-final_tick 121535 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000129 # Number of seconds simulated
+sim_ticks 129075 # Number of ticks simulated
+final_tick 129075 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 67126 # Simulator instruction rate (inst/s)
-host_op_rate 67120 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1273887 # Simulator tick rate (ticks/s)
-host_mem_usage 453732 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 59192 # Simulator instruction rate (inst/s)
+host_op_rate 59185 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1192972 # Simulator tick rate (ticks/s)
+host_mem_usage 410988 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 93504 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 17728 # Number of bytes written to this memory
@@ -22,35 +22,35 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1461 #
system.mem_ctrls.num_reads::total 1461 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 277 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 277 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 769358621 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 769358621 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 145867446 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 145867446 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 915226067 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 915226067 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 724416037 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 724416037 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 137346504 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 137346504 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 861762541 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 861762541 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1461 # Number of read requests accepted
system.mem_ctrls.writeReqs 277 # Number of write requests accepted
system.mem_ctrls.readBursts 1461 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 277 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 74240 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 19264 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 5376 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM 74368 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 19136 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 6400 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 93504 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 17728 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 163 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ 299 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 160 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 102 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 61 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 90 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 90 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 21 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 101 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 22 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 4 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 84 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 78 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 75 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 26 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 395 # Per bank write bursts
@@ -60,21 +60,21 @@ system.mem_ctrls.perBankWrBursts::0 0 # Pe
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 24 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 7 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 7 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 16 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 21 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 121448 # Total gap between requests
+system.mem_ctrls.totGap 128982 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 277 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1160 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 1162 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -151,9 +151,9 @@ system.mem_ctrls.wrQLenPdf::26 6 # Wh
system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -185,88 +185,99 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 217 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 357.751152 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 214.775071 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 343.064988 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 66 30.41% 30.41% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 51 23.50% 53.92% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 17 7.83% 61.75% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 18 8.29% 70.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 15 6.91% 76.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 6 2.76% 79.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 12 5.53% 85.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 4 1.84% 87.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 28 12.90% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 217 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 150.400000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 107.633945 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 97.202366 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::72-79 1 20.00% 40.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::240-247 1 20.00% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.800000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.771851 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 3 60.00% 60.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 8011 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 30051 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 5800 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.91 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 215 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 364.055814 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 222.075931 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 347.859995 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 60 27.91% 27.91% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 55 25.58% 53.49% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 24 11.16% 64.65% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 15 6.98% 71.63% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 8 3.72% 75.35% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 9 4.19% 79.53% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 8 3.72% 83.26% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 5 2.33% 85.58% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 31 14.42% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 215 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 193.166667 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 134.817545 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 132.906609 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::64-79 1 16.67% 33.33% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 50.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::224-239 1 16.67% 66.67% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::240-255 1 16.67% 83.33% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::384-399 1 16.67% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.666667 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.640671 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.032796 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 4 66.67% 66.67% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 2 33.33% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 15493 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 37571 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5810 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 13.33 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.91 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 610.85 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 44.23 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 769.36 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 145.87 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 32.33 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 576.16 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 49.58 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 724.42 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 137.35 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 5.12 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.77 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 4.89 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 22.41 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 943 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.29 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 68.42 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 69.88 # Average gap between requests
-system.mem_ctrls.pageHitRate 80.14 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 506520 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 281400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5703360 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 65986164 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 12347400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 92702076 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 791.986980 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 22788 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 3900 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 92991 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 1103760 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 613200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 8236800 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 622080 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 78402132 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1456200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 98062572 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 837.783614 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 1811 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 3900 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 111353 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen 22.78 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 949 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 91 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 81.67 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 77.78 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 74.21 # Average gap between requests
+system.mem_ctrls.pageHitRate 81.31 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 514080 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 270480 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 5380704 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 258912 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 8608824 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 320256 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 37409784 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 6725376 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 2906400 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 72229056 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 559.589820 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 109312 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 366 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 4166 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 9809 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 17514 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 15181 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 82039 # Time in different power states
+system.mem_ctrls_1.actEnergy 1071000 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 560280 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 7893984 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 576288 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 9834240.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 12597000 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 372480 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 45058272 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 640512 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 78604056 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 608.979709 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 100248 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 270 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 4160 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 1668 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 24165 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 98812 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -301,8 +312,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 121535 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 121535 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 129075 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 129075 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6403 # Number of instructions committed
@@ -321,7 +332,7 @@ system.cpu.num_mem_refs 2060 # nu
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 121535 # Number of busy cycles
+system.cpu.num_busy_cycles 129075 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1056 # Number of branches fetched
@@ -361,13 +372,13 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 9652 # delay histogram for all message
-system.ruby.delayHist::mean 0.164525 # delay histogram for all message
-system.ruby.delayHist::stdev 1.011525 # delay histogram for all message
-system.ruby.delayHist | 9293 96.28% 96.28% | 0 0.00% 96.28% | 214 2.22% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
+system.ruby.delayHist::mean 0.163697 # delay histogram for all message
+system.ruby.delayHist::stdev 1.010840 # delay histogram for all message
+system.ruby.delayHist | 9297 96.32% 96.32% | 0 0.00% 96.32% | 210 2.18% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 0 0.00% 98.50% | 145 1.50% 100.00% | 0 0.00% 100.00% # delay histogram for all message
system.ruby.delayHist::total 9652 # delay histogram for all message
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
@@ -379,10 +390,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8463
-system.ruby.latency_hist_seqr::mean 13.360747
-system.ruby.latency_hist_seqr::gmean 2.097350
-system.ruby.latency_hist_seqr::stdev 29.565169
-system.ruby.latency_hist_seqr | 7303 86.29% 86.29% | 1141 13.48% 99.78% | 4 0.05% 99.82% | 1 0.01% 99.83% | 8 0.09% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 14.251684
+system.ruby.latency_hist_seqr::gmean 2.119385
+system.ruby.latency_hist_seqr::stdev 32.289040
+system.ruby.latency_hist_seqr | 7301 86.27% 86.27% | 1142 13.49% 99.76% | 3 0.04% 99.80% | 1 0.01% 99.81% | 6 0.07% 99.88% | 9 0.11% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
@@ -394,12 +405,12 @@ system.ruby.hit_latency_hist_seqr::total 6972
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1491
-system.ruby.miss_latency_hist_seqr::mean 71.160295
-system.ruby.miss_latency_hist_seqr::gmean 66.961050
-system.ruby.miss_latency_hist_seqr::stdev 30.103565
-system.ruby.miss_latency_hist_seqr | 331 22.20% 22.20% | 1141 76.53% 98.73% | 4 0.27% 98.99% | 1 0.07% 99.06% | 8 0.54% 99.60% | 6 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 76.217304
+system.ruby.miss_latency_hist_seqr::gmean 71.053455
+system.ruby.miss_latency_hist_seqr::stdev 35.454362
+system.ruby.miss_latency_hist_seqr | 329 22.07% 22.07% | 1142 76.59% 98.66% | 3 0.20% 98.86% | 1 0.07% 98.93% | 6 0.40% 99.33% | 9 0.60% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00%
system.ruby.miss_latency_hist_seqr::total 1491
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1250 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 800 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
@@ -415,15 +426,15 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 30 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1461 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1491 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 4.310281
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 4.058493
system.ruby.network.routers0.msg_count.Control::0 1491
system.ruby.network.routers0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.msg_count.Response_Data::1 1491
@@ -440,8 +451,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 6400
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 2336
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 8.369194
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 7.880302
system.ruby.network.routers1.msg_count.Control::0 2952
system.ruby.network.routers1.msg_count.Request_Control::2 1041
system.ruby.network.routers1.msg_count.Response_Data::1 3229
@@ -458,16 +469,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 6400
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 2336
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 4.058913
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 3.821809
system.ruby.network.routers2.msg_count.Control::0 1461
system.ruby.network.routers2.msg_count.Response_Data::1 1738
system.ruby.network.routers2.msg_count.Response_Control::1 2629
system.ruby.network.routers2.msg_bytes.Control::0 11688
system.ruby.network.routers2.msg_bytes.Response_Data::1 125136
system.ruby.network.routers2.msg_bytes.Response_Control::1 21032
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 5.579463
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized 5.253535
system.ruby.network.routers3.msg_count.Control::0 2952
system.ruby.network.routers3.msg_count.Request_Control::2 1041
system.ruby.network.routers3.msg_count.Response_Data::1 3229
@@ -484,7 +495,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 6400
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 2336
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 8856
system.ruby.network.msg_count.Request_Control 3123
system.ruby.network.msg_count.Response_Data 9687
@@ -497,15 +508,15 @@ system.ruby.network.msg_byte.Response_Data 697464
system.ruby.network.msg_byte.Response_Control 114384
system.ruby.network.msg_byte.Writeback_Data 61776
system.ruby.network.msg_byte.Writeback_Control 7008
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 121535 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 6.128687
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 129075 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 5.770676
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 1041
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 1491
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 437
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 8328
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 107352
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 3496
-system.ruby.network.routers0.throttle1.link_utilization 2.491875
+system.ruby.network.routers0.throttle1.link_utilization 2.346310
system.ruby.network.routers0.throttle1.msg_count.Control::0 1491
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 900
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 800
@@ -518,7 +529,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 640
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 2336
-system.ruby.network.routers1.throttle0.link_utilization 8.499198
+system.ruby.network.routers1.throttle0.link_utilization 8.002712
system.ruby.network.routers1.throttle0.msg_count.Control::0 1491
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 1461
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 2353
@@ -533,7 +544,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 640
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 2336
-system.ruby.network.routers1.throttle1.link_utilization 8.239190
+system.ruby.network.routers1.throttle1.link_utilization 7.757893
system.ruby.network.routers1.throttle1.msg_count.Control::0 1461
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1041
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 1768
@@ -542,26 +553,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 11688
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 8328
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 127296
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 12904
-system.ruby.network.routers2.throttle0.link_utilization 2.110503
+system.ruby.network.routers2.throttle0.link_utilization 1.987217
system.ruby.network.routers2.throttle0.msg_count.Control::0 1461
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 277
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 1176
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 11688
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 19944
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 9408
-system.ruby.network.routers2.throttle1.link_utilization 6.007323
+system.ruby.network.routers2.throttle1.link_utilization 5.656401
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 1461
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 1453
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 105192
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 11624
-system.ruby.network.routers3.throttle0.link_utilization 6.128687
+system.ruby.network.routers3.throttle0.link_utilization 5.770676
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 1041
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 1491
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 437
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 8328
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 107352
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 3496
-system.ruby.network.routers3.throttle1.link_utilization 8.499198
+system.ruby.network.routers3.throttle1.link_utilization 8.002712
system.ruby.network.routers3.throttle1.msg_count.Control::0 1491
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 1461
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 2353
@@ -576,7 +587,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 640
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 10440
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 10152
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 2336
-system.ruby.network.routers3.throttle2.link_utilization 2.110503
+system.ruby.network.routers3.throttle2.link_utilization 1.987217
system.ruby.network.routers3.throttle2.msg_count.Control::0 1461
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 277
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 1176
@@ -593,9 +604,9 @@ system.ruby.delayVCHist.vnet_0::total 2728 # de
system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::samples 5883 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::mean 0.072752 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1::stdev 0.374480 # delay histogram for vnet_1
-system.ruby.delayVCHist.vnet_1 | 5669 96.36% 96.36% | 0 0.00% 96.36% | 214 3.64% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::mean 0.071392 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1::stdev 0.371094 # delay histogram for vnet_1
+system.ruby.delayVCHist.vnet_1 | 5673 96.43% 96.43% | 0 0.00% 96.43% | 210 3.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_1::total 5883 # delay histogram for vnet_1
system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2
@@ -605,10 +616,10 @@ system.ruby.delayVCHist.vnet_2::total 1041 # de
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1185
-system.ruby.LD.latency_hist_seqr::mean 33.565401
-system.ruby.LD.latency_hist_seqr::gmean 7.686795
-system.ruby.LD.latency_hist_seqr::stdev 38.515936
-system.ruby.LD.latency_hist_seqr | 803 67.76% 67.76% | 378 31.90% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 3 0.25% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 36.416034
+system.ruby.LD.latency_hist_seqr::gmean 7.907367
+system.ruby.LD.latency_hist_seqr::stdev 46.041898
+system.ruby.LD.latency_hist_seqr | 802 67.68% 67.68% | 375 31.65% 99.32% | 1 0.08% 99.41% | 0 0.00% 99.41% | 3 0.25% 99.66% | 3 0.25% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
@@ -620,18 +631,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 601
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 584
-system.ruby.LD.miss_latency_hist_seqr::mean 67.078767
-system.ruby.LD.miss_latency_hist_seqr::gmean 62.700967
-system.ruby.LD.miss_latency_hist_seqr::stdev 28.185747
-system.ruby.LD.miss_latency_hist_seqr | 202 34.59% 34.59% | 378 64.73% 99.32% | 0 0.00% 99.32% | 0 0.00% 99.32% | 3 0.51% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 72.863014
+system.ruby.LD.miss_latency_hist_seqr::gmean 66.405671
+system.ruby.LD.miss_latency_hist_seqr::stdev 41.005857
+system.ruby.LD.miss_latency_hist_seqr | 201 34.42% 34.42% | 375 64.21% 98.63% | 1 0.17% 98.80% | 0 0.00% 98.80% | 3 0.51% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 584
-system.ruby.ST.latency_hist_seqr::bucket_size 64
-system.ruby.ST.latency_hist_seqr::max_bucket 639
+system.ruby.ST.latency_hist_seqr::bucket_size 16
+system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 15.551445
-system.ruby.ST.latency_hist_seqr::gmean 2.706248
-system.ruby.ST.latency_hist_seqr::stdev 29.831548
-system.ruby.ST.latency_hist_seqr | 773 89.36% 89.36% | 90 10.40% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 15.646243
+system.ruby.ST.latency_hist_seqr::gmean 2.719887
+system.ruby.ST.latency_hist_seqr::stdev 27.764380
+system.ruby.ST.latency_hist_seqr | 649 75.03% 75.03% | 12 1.39% 76.42% | 101 11.68% 88.09% | 10 1.16% 89.25% | 36 4.16% 93.41% | 52 6.01% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@@ -640,21 +651,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 649 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 649
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
+system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
system.ruby.ST.miss_latency_hist_seqr::samples 216
-system.ruby.ST.miss_latency_hist_seqr::mean 59.273148
-system.ruby.ST.miss_latency_hist_seqr::gmean 53.885554
-system.ruby.ST.miss_latency_hist_seqr::stdev 31.884011
-system.ruby.ST.miss_latency_hist_seqr | 124 57.41% 57.41% | 90 41.67% 99.07% | 0 0.00% 99.07% | 0 0.00% 99.07% | 1 0.46% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 59.652778
+system.ruby.ST.miss_latency_hist_seqr::gmean 54.981344
+system.ruby.ST.miss_latency_hist_seqr::stdev 22.464955
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 5.56% 5.56% | 101 46.76% 52.31% | 10 4.63% 56.94% | 36 16.67% 73.61% | 52 24.07% 97.69% | 4 1.85% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 216
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6413
-system.ruby.IFETCH.latency_hist_seqr::mean 9.331826
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.594079
-system.ruby.IFETCH.latency_hist_seqr::stdev 25.833878
-system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 673 10.49% 99.80% | 4 0.06% 99.86% | 1 0.02% 99.88% | 4 0.06% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 9.968034
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.606700
+system.ruby.IFETCH.latency_hist_seqr::stdev 27.770381
+system.ruby.IFETCH.latency_hist_seqr | 5727 89.30% 89.30% | 674 10.51% 99.81% | 2 0.03% 99.84% | 1 0.02% 99.86% | 3 0.05% 99.91% | 6 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
@@ -666,10 +677,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5722
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 691
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.325615
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 75.760449
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.311514
-system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 673 97.40% 98.12% | 4 0.58% 98.70% | 1 0.14% 98.84% | 4 0.58% 99.42% | 4 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 84.230101
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 81.513388
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.252511
+system.ruby.IFETCH.miss_latency_hist_seqr | 5 0.72% 0.72% | 674 97.54% 98.26% | 2 0.29% 98.55% | 1 0.14% 98.70% | 3 0.43% 99.13% | 6 0.87% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 691
system.ruby.Directory_Controller.Fetch 1461 0.00% 0.00%
system.ruby.Directory_Controller.Data 277 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 7127384c1..2e87336b3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=6
eventq_index=0
forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestToDir=system.ruby.dir_cntrl0.requestToDir
responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
l2_select_num_bits=0
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
@@ -433,17 +464,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
request_latency=2
responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
@@ -566,18 +607,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
ruby_system=system.ruby
topology=Crossbar
@@ -740,42 +786,216 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
router_id=0
virt_nets=3
@@ -867,8 +1087,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
router_id=1
virt_nets=3
@@ -960,8 +1186,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
router_id=2
virt_nets=3
@@ -1053,8 +1285,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
router_id=3
virt_nets=3
@@ -1187,9 +1425,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index c750cc80b..3faf7299f 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 22:01:23
-gem5 started Mar 14 2016 22:02:29
-gem5 executing on phenom, pid 29128
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Oct 13 2016 20:30:58
+gem5 started Oct 13 2016 20:31:25
+gem5 executing on e108600-lin, pid 17789
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 108878 because target called exit()
+Exiting @ tick 115948 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 99bf8d33d..0d7120e11 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000109 # Number of seconds simulated
-sim_ticks 108878 # Number of ticks simulated
-final_tick 108878 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000116 # Number of seconds simulated
+sim_ticks 115948 # Number of ticks simulated
+final_tick 115948 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 66441 # Simulator instruction rate (inst/s)
-host_op_rate 66435 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1129573 # Simulator tick rate (ticks/s)
-host_mem_usage 461124 # Number of bytes of host memory used
+host_inst_rate 62775 # Simulator instruction rate (inst/s)
+host_op_rate 62768 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1136521 # Simulator tick rate (ticks/s)
+host_mem_usage 416956 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75712 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 12416 # Number of bytes written to this memory
@@ -22,29 +22,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1183 #
system.mem_ctrls.num_reads::total 1183 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 194 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 194 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 695383824 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 695383824 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 114035893 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 114035893 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 809419717 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 809419717 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 652982371 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 652982371 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 107082485 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 107082485 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 760064857 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 760064857 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1183 # Number of read requests accepted
system.mem_ctrls.writeReqs 194 # Number of write requests accepted
system.mem_ctrls.readBursts 1183 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 194 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 64576 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 11136 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM 65152 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 10560 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 5440 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 75712 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 12416 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 174 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 79 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 51 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 81 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 75 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 94 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 99 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 2 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
@@ -53,15 +53,15 @@ system.mem_ctrls.perBankRdBursts::9 1 # Pe
system.mem_ctrls.perBankRdBursts::10 56 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 51 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 365 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 67 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 367 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 69 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 18 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
@@ -69,12 +69,12 @@ system.mem_ctrls.perBankWrBursts::9 0 # Pe
system.mem_ctrls.perBankWrBursts::10 3 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 41 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 20 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 108826 # Total gap between requests
+system.mem_ctrls.totGap 115890 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 194 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1009 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 1018 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -136,21 +136,21 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 4 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 7 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 7 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
@@ -185,88 +185,99 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 334.817734 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 202.715946 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 328.878595 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 47 23.15% 55.17% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 25 12.32% 67.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 72.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 11 5.42% 78.33% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.25% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 5 2.46% 85.71% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 8 3.94% 89.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 208 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 330.153846 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 204.681326 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 325.358480 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 61 29.33% 29.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 54 25.96% 55.29% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 30 14.42% 69.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 9 4.33% 74.04% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 16 7.69% 81.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 5 2.40% 84.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 5 2.40% 86.54% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 4 1.92% 88.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 24 11.54% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 208 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 138.600000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 101.703151 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 85.219129 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 142.600000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 108.227176 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 79.531755 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::168-175 1 20.00% 60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::192-199 1 20.00% 80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::136-143 1 20.00% 60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::200-207 1 20.00% 80.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 17 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.976446 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 1 20.00% 60.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 2 40.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 7036 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26207 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 5045 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.97 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 13845 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 33187 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5090 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 13.60 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.97 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 593.10 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 50.55 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 695.38 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 114.04 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 32.60 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 561.91 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 46.92 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 652.98 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 107.08 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 5.03 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.39 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.37 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 21.05 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 80 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 79.88 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 70.80 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 79.03 # Average gap between requests
-system.mem_ctrls.pageHitRate 78.97 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 529200 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 294000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5004480 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 248832 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 61961508 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 6534600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 81183900 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 800.014782 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 16245 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 87571 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 907200 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 504000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 642816 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 67902048 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1323600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 84655104 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 834.221250 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 1730 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 96382 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen 21.83 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 811 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 79.67 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 67.83 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 84.16 # Average gap between requests
+system.mem_ctrls.pageHitRate 78.46 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 528360 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 278208 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 4706688 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 158688 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 8177904 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 299520 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 33992976 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 6547200 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 1905360 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 65814504 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 567.620865 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 97183 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 354 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 3906 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 5638 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 17050 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 14454 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 74546 # Time in different power states
+system.mem_ctrls_1.actEnergy 999600 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 525504 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 6922944 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 551232 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 10734696 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 319488 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 40821120 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 789120 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 70268664 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 606.036016 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 91295 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 272 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 2055 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 20461 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 89520 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -301,8 +312,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 108878 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 108878 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 115948 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 115948 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6403 # Number of instructions committed
@@ -321,7 +332,7 @@ system.cpu.num_mem_refs 2060 # nu
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 108878 # Number of busy cycles
+system.cpu.num_busy_cycles 115948 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1056 # Number of branches fetched
@@ -361,7 +372,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
@@ -372,10 +383,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8463
-system.ruby.latency_hist_seqr::mean 11.865178
-system.ruby.latency_hist_seqr::gmean 1.973283
-system.ruby.latency_hist_seqr::stdev 27.863065
-system.ruby.latency_hist_seqr | 7453 88.07% 88.07% | 995 11.76% 99.82% | 2 0.02% 99.85% | 0 0.00% 99.85% | 9 0.11% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 12.700579
+system.ruby.latency_hist_seqr::gmean 1.992540
+system.ruby.latency_hist_seqr::stdev 30.668579
+system.ruby.latency_hist_seqr | 7444 87.96% 87.96% | 1001 11.83% 99.79% | 3 0.04% 99.82% | 0 0.00% 99.82% | 6 0.07% 99.89% | 8 0.09% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
@@ -387,27 +398,27 @@ system.ruby.hit_latency_hist_seqr::total 7041
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1422
-system.ruby.miss_latency_hist_seqr::mean 65.663854
-system.ruby.miss_latency_hist_seqr::gmean 57.123275
-system.ruby.miss_latency_hist_seqr::stdev 33.791401
-system.ruby.miss_latency_hist_seqr | 412 28.97% 28.97% | 995 69.97% 98.95% | 2 0.14% 99.09% | 0 0.00% 99.09% | 9 0.63% 99.72% | 4 0.28% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 70.635724
+system.ruby.miss_latency_hist_seqr::gmean 60.522119
+system.ruby.miss_latency_hist_seqr::stdev 39.545085
+system.ruby.miss_latency_hist_seqr | 403 28.34% 28.34% | 1001 70.39% 98.73% | 3 0.21% 98.95% | 0 0.00% 98.95% | 6 0.42% 99.37% | 8 0.56% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00%
system.ruby.miss_latency_hist_seqr::total 1422
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1274 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 776 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 239 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1183 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1422 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 6.929545
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 6.507012
system.ruby.network.routers0.msg_count.Request_Control::0 1422
system.ruby.network.routers0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 239
@@ -420,8 +431,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 11744
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 10.407520
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 9.772915
system.ruby.network.routers1.msg_count.Request_Control::0 1422
system.ruby.network.routers1.msg_count.Request_Control::1 1183
system.ruby.network.routers1.msg_count.Response_Data::2 2366
@@ -438,8 +449,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 108216
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 21208
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 3.477975
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 3.265904
system.ruby.network.routers2.msg_count.Request_Control::1 1183
system.ruby.network.routers2.msg_count.Response_Data::2 1183
system.ruby.network.routers2.msg_count.Writeback_Data::2 194
@@ -450,8 +461,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 9464
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 6.938347
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized 6.515277
system.ruby.network.routers3.msg_count.Request_Control::0 1422
system.ruby.network.routers3.msg_count.Request_Control::1 1183
system.ruby.network.routers3.msg_count.Response_Data::2 2366
@@ -468,7 +479,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 108216
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 21680
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 3104
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 21208
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 7815
system.ruby.network.msg_count.Response_Data 7098
system.ruby.network.msg_count.ResponseL2hit_Data 717
@@ -481,15 +492,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 51624
system.ruby.network.msg_byte.Writeback_Data 324648
system.ruby.network.msg_byte.Writeback_Control 74352
system.ruby.network.msg_byte.Unblock_Control 63624
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108878 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 6.499476
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 115948 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 6.103167
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 1355
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 10840
-system.ruby.network.routers0.throttle1.link_utilization 7.359614
+system.ruby.network.routers0.throttle1.link_utilization 6.910857
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 1422
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 1309
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 1355
@@ -498,7 +509,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 11376
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 11744
-system.ruby.network.routers1.throttle0.link_utilization 12.338122
+system.ruby.network.routers1.throttle0.link_utilization 11.585797
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 1422
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 1309
@@ -511,7 +522,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 11744
-system.ruby.network.routers1.throttle1.link_utilization 8.476919
+system.ruby.network.routers1.throttle1.link_utilization 7.960034
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 1183
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 239
@@ -526,7 +537,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 9464
-system.ruby.network.routers2.throttle0.link_utilization 1.977443
+system.ruby.network.routers2.throttle0.link_utilization 1.856867
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 1183
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 194
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 194
@@ -535,19 +546,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 9464
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 9464
-system.ruby.network.routers2.throttle1.link_utilization 4.978508
+system.ruby.network.routers2.throttle1.link_utilization 4.674940
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 194
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 85176
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 1552
-system.ruby.network.routers3.throttle0.link_utilization 6.499476
+system.ruby.network.routers3.throttle0.link_utilization 6.103167
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 1183
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 239
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 1355
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 85176
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 17208
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 10840
-system.ruby.network.routers3.throttle1.link_utilization 12.338122
+system.ruby.network.routers3.throttle1.link_utilization 11.585797
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 1422
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 1183
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 1309
@@ -560,7 +571,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 94248
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 10840
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 11744
-system.ruby.network.routers3.throttle2.link_utilization 1.977443
+system.ruby.network.routers3.throttle2.link_utilization 1.856867
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 1183
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 194
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 194
@@ -569,13 +580,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 9464
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 13968
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 1552
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 9464
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::bucket_size 64
+system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1185
-system.ruby.LD.latency_hist_seqr::mean 27.428692
-system.ruby.LD.latency_hist_seqr::gmean 5.747000
-system.ruby.LD.latency_hist_seqr::stdev 36.091782
-system.ruby.LD.latency_hist_seqr | 775 65.40% 65.40% | 87 7.34% 72.74% | 279 23.54% 96.29% | 40 3.38% 99.66% | 1 0.08% 99.75% | 1 0.08% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 29.289451
+system.ruby.LD.latency_hist_seqr::gmean 5.875383
+system.ruby.LD.latency_hist_seqr::stdev 39.627102
+system.ruby.LD.latency_hist_seqr | 857 72.32% 72.32% | 323 27.26% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
@@ -584,21 +595,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 659
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 526
-system.ruby.LD.miss_latency_hist_seqr::mean 60.539924
-system.ruby.LD.miss_latency_hist_seqr::gmean 51.393520
-system.ruby.LD.miss_latency_hist_seqr::stdev 31.024435
-system.ruby.LD.miss_latency_hist_seqr | 116 22.05% 22.05% | 87 16.54% 38.59% | 279 53.04% 91.63% | 40 7.60% 99.24% | 1 0.19% 99.43% | 1 0.19% 99.62% | 0 0.00% 99.62% | 0 0.00% 99.62% | 1 0.19% 99.81% | 1 0.19% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 64.731939
+system.ruby.LD.miss_latency_hist_seqr::gmean 54.016248
+system.ruby.LD.miss_latency_hist_seqr::stdev 35.753260
+system.ruby.LD.miss_latency_hist_seqr | 198 37.64% 37.64% | 323 61.41% 99.05% | 2 0.38% 99.43% | 0 0.00% 99.43% | 1 0.19% 99.62% | 2 0.38% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 526
system.ruby.ST.latency_hist_seqr::bucket_size 64
system.ruby.ST.latency_hist_seqr::max_bucket 639
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 17.057803
-system.ruby.ST.latency_hist_seqr::gmean 3.071194
-system.ruby.ST.latency_hist_seqr::stdev 31.094076
-system.ruby.ST.latency_hist_seqr | 753 87.05% 87.05% | 110 12.72% 99.77% | 0 0.00% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 17.729480
+system.ruby.ST.latency_hist_seqr::gmean 3.104775
+system.ruby.ST.latency_hist_seqr::stdev 31.273004
+system.ruby.ST.latency_hist_seqr | 749 86.59% 86.59% | 115 13.29% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@@ -610,18 +621,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 615
system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
system.ruby.ST.miss_latency_hist_seqr::samples 250
-system.ruby.ST.miss_latency_hist_seqr::mean 56.560000
-system.ruby.ST.miss_latency_hist_seqr::gmean 48.538116
-system.ruby.ST.miss_latency_hist_seqr::stdev 33.930333
-system.ruby.ST.miss_latency_hist_seqr | 138 55.20% 55.20% | 110 44.00% 99.20% | 0 0.00% 99.20% | 0 0.00% 99.20% | 1 0.40% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 58.884000
+system.ruby.ST.miss_latency_hist_seqr::gmean 50.399294
+system.ruby.ST.miss_latency_hist_seqr::stdev 31.651062
+system.ruby.ST.miss_latency_hist_seqr | 134 53.60% 53.60% | 115 46.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 0 0.00% 99.60% | 1 0.40% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 250
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6413
-system.ruby.IFETCH.latency_hist_seqr::mean 8.288944
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.525778
-system.ruby.IFETCH.latency_hist_seqr::stdev 24.342417
-system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 566 8.83% 99.86% | 0 0.00% 99.86% | 0 0.00% 99.86% | 6 0.09% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 8.956962
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.536905
+system.ruby.IFETCH.latency_hist_seqr::stdev 27.408738
+system.ruby.IFETCH.latency_hist_seqr | 5838 91.03% 91.03% | 563 8.78% 99.81% | 1 0.02% 99.83% | 0 0.00% 99.83% | 5 0.08% 99.91% | 5 0.08% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
@@ -633,10 +644,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5767
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 646
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.359133
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 66.307554
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.276818
-system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 566 87.62% 98.61% | 0 0.00% 98.61% | 0 0.00% 98.61% | 6 0.93% 99.54% | 3 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.990712
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.267502
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 42.993310
+system.ruby.IFETCH.miss_latency_hist_seqr | 71 10.99% 10.99% | 563 87.15% 98.14% | 1 0.15% 98.30% | 0 0.00% 98.30% | 5 0.77% 99.07% | 5 0.77% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.15% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 646
system.ruby.Directory_Controller.GETX 198 0.00% 0.00%
system.ruby.Directory_Controller.GETS 985 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 072c6d45b..c3c3a350f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=5
distributed_persistent=true
@@ -258,8 +280,12 @@ eventq_index=0
fixed_timeout_latency=100
l2_select_num_bits=0
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
persistentToDir=system.ruby.dir_cntrl0.persistentToDir
+power_model=Null
recycle_latency=10
reissue_wakeup_latency=10
requestFromDir=system.ruby.dir_cntrl0.requestFromDir
@@ -361,6 +387,7 @@ N_tokens=2
buffer_size=0
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
dynamic_timeout_enabled=true
eventq_index=0
fixed_timeout_latency=300
@@ -370,8 +397,12 @@ l2_select_num_bits=0
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
no_mig_atomic=true
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache
persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache
+power_model=Null
recycle_latency=10
reissue_wakeup_latency=10
requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -497,17 +528,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -524,12 +560,17 @@ N_tokens=2
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
filtering_enabled=true
l2_request_latency=5
l2_response_latency=5
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache
+power_model=Null
recycle_latency=10
responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -626,18 +667,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
ruby_system=system.ruby
topology=Crossbar
@@ -926,42 +972,342 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23
+power_model=Null
router_id=0
virt_nets=6
@@ -1137,8 +1483,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23
+power_model=Null
router_id=1
virt_nets=6
@@ -1314,8 +1666,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
router_id=2
virt_nets=6
@@ -1491,8 +1849,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35
+power_model=Null
router_id=3
virt_nets=6
@@ -1751,9 +2115,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index f535b9682..57e41dbee 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 22:02:54
-gem5 started Mar 14 2016 22:04:07
-gem5 executing on phenom, pid 29513
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Oct 13 2016 20:33:48
+gem5 started Oct 13 2016 20:34:16
+gem5 executing on e108600-lin, pid 27525
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 108253 because target called exit()
+Exiting @ tick 113952 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index e5f292184..b89069f53 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000108 # Number of seconds simulated
-sim_ticks 108253 # Number of ticks simulated
-final_tick 108253 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000114 # Number of seconds simulated
+sim_ticks 113952 # Number of ticks simulated
+final_tick 113952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 94410 # Simulator instruction rate (inst/s)
-host_op_rate 94397 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1595747 # Simulator tick rate (ticks/s)
-host_mem_usage 455808 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 64476 # Simulator instruction rate (inst/s)
+host_op_rate 64460 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1146955 # Simulator tick rate (ticks/s)
+host_mem_usage 412808 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 75456 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14656 # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1179 #
system.mem_ctrls.num_reads::total 1179 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 229 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 229 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 697033800 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 697033800 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 135386548 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 135386548 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 832420349 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 832420349 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 662173547 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 662173547 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 128615557 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 128615557 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 790789104 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 790789104 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1179 # Number of read requests accepted
system.mem_ctrls.writeReqs 229 # Number of write requests accepted
system.mem_ctrls.readBursts 1179 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 229 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 65088 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 10368 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 6144 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM 64256 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 11200 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 5120 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 75456 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 14656 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 162 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 112 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ 175 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 117 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 95 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::5 19 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 92 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 59 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 51 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11 53 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 361 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 360 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 45 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 7 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 20 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 5 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 18 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::14 43 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::14 37 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 108170 # Total gap between requests
+system.mem_ctrls.totGap 113863 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 229 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 1017 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 1004 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -138,10 +138,10 @@ system.mem_ctrls.wrQLenPdf::13 1 # Wh
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 7 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 7 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 7 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 7 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
@@ -153,7 +153,7 @@ system.mem_ctrls.wrQLenPdf::28 6 # Wh
system.mem_ctrls.wrQLenPdf::29 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -185,87 +185,96 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 203 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 338.916256 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 206.604664 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 325.225174 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 65 32.02% 32.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 46 22.66% 54.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 21 10.34% 65.02% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 11 5.42% 70.44% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 17 8.37% 78.82% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 10 4.93% 83.74% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 8 3.94% 87.68% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 4 1.97% 89.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 21 10.34% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 203 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 156.500000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 117.084065 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 90.391924 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-31 1 16.67% 16.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::80-95 1 16.67% 33.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::160-175 1 16.67% 50.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::192-207 1 16.67% 66.67% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::208-223 1 16.67% 83.33% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::256-271 1 16.67% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 6 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads
+system.mem_ctrls.bytesPerActivate::samples 201 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 338.149254 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 209.301438 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 329.237418 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 56 27.86% 27.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 54 26.87% 54.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 27 13.43% 68.16% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 9 4.48% 72.64% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 15 7.46% 80.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 6 2.99% 83.08% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 6 2.99% 86.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 4 1.99% 88.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 24 11.94% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 201 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 138 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 99.720637 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 86.905121 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::80-87 1 20.00% 40.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::160-167 1 20.00% 60.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::208-215 1 20.00% 80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 6 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 7213 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 26536 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 5085 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 7.09 # Average queueing delay per DRAM burst
+system.mem_ctrls.wrPerTurnAround::16 5 100.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 13296 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 32372 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 5020 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 13.24 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 26.09 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 601.26 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 56.76 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 697.03 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 135.39 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 32.24 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 563.89 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 44.93 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 662.17 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 128.62 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 5.14 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.70 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 4.76 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.41 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.35 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 23.01 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 816 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 88 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 80.24 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 75.21 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 76.83 # Average gap between requests
-system.mem_ctrls.pageHitRate 79.72 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 521640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5104320 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 311040 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 57840408 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 10149600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 80828088 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 796.508485 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 21689 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 81532 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 945000 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 525000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 6764160 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 684288 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 67474548 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 1707000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 84711276 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 834.659638 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 2397 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 95729 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen 22.60 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 806 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 73 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 80.28 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 65.18 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 80.87 # Average gap between requests
+system.mem_ctrls.pageHitRate 78.76 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 471240 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 255024 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 4695264 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 217152 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 9219600.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 7578264 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 292992 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 33706152 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 7106688 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 1604640 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 65147016 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 570.509199 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 96809 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 351 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 3653 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 4385 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 18507 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 13139 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 73917 # Time in different power states
+system.mem_ctrls_1.actEnergy 992460 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 521640 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 6774432 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 451008 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 10831824 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 319872 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 39423936 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 1117056 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 69037188 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 605.844461 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 89154 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 259 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 2909 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 20688 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 86456 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -300,8 +309,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 108253 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 108253 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 113952 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 113952 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6403 # Number of instructions committed
@@ -320,7 +329,7 @@ system.cpu.num_mem_refs 2060 # nu
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 108253 # Number of busy cycles
+system.cpu.num_busy_cycles 113952 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1056 # Number of branches fetched
@@ -360,7 +369,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
@@ -371,86 +380,86 @@ system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8463
-system.ruby.latency_hist_seqr::mean 11.791327
-system.ruby.latency_hist_seqr::gmean 1.956562
-system.ruby.latency_hist_seqr::stdev 27.556143
-system.ruby.latency_hist_seqr | 7446 87.98% 87.98% | 996 11.77% 99.75% | 8 0.09% 99.85% | 4 0.05% 99.89% | 5 0.06% 99.95% | 4 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 12.464729
+system.ruby.latency_hist_seqr::gmean 1.971984
+system.ruby.latency_hist_seqr::stdev 29.823065
+system.ruby.latency_hist_seqr | 7459 88.14% 88.14% | 983 11.62% 99.75% | 7 0.08% 99.83% | 3 0.04% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 8
system.ruby.hit_latency_hist_seqr::max_bucket 79
system.ruby.hit_latency_hist_seqr::samples 7284
-system.ruby.hit_latency_hist_seqr::mean 1.635502
-system.ruby.hit_latency_hist_seqr::gmean 1.092626
-system.ruby.hit_latency_hist_seqr::stdev 3.754063
+system.ruby.hit_latency_hist_seqr::mean 1.636052
+system.ruby.hit_latency_hist_seqr::gmean 1.092653
+system.ruby.hit_latency_hist_seqr::stdev 3.757041
system.ruby.hit_latency_hist_seqr | 7080 97.20% 97.20% | 0 0.00% 97.20% | 21 0.29% 97.49% | 182 2.50% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 7284
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1179
-system.ruby.miss_latency_hist_seqr::mean 74.535199
-system.ruby.miss_latency_hist_seqr::gmean 71.564149
-system.ruby.miss_latency_hist_seqr::stdev 28.099799
-system.ruby.miss_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 79.365564
+system.ruby.miss_latency_hist_seqr::gmean 75.701428
+system.ruby.miss_latency_hist_seqr::stdev 33.123085
+system.ruby.miss_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00%
system.ruby.miss_latency_hist_seqr::total 1179
system.ruby.Directory.incomplete_times_seqr 1178
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1313 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 737 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 5767 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 646 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 187 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 1196 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 1383 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 6.022466
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 5.719513
system.ruby.network.routers0.msg_count.Request_Control::1 1383
system.ruby.network.routers0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers0.msg_count.Response_Control::4 1
system.ruby.network.routers0.msg_count.Writeback_Data::4 1355
-system.ruby.network.routers0.msg_count.Persistent_Control::3 52
+system.ruby.network.routers0.msg_count.Persistent_Control::3 44
system.ruby.network.routers0.msg_bytes.Request_Control::1 11064
system.ruby.network.routers0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 97560
-system.ruby.network.routers0.msg_bytes.Persistent_Control::3 416
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 4.541676
+system.ruby.network.routers0.msg_bytes.Persistent_Control::3 352
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 4.313658
system.ruby.network.routers1.msg_count.Request_Control::1 1383
system.ruby.network.routers1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers1.msg_count.Response_Control::4 1
system.ruby.network.routers1.msg_count.Writeback_Data::4 1584
system.ruby.network.routers1.msg_count.Writeback_Control::4 968
-system.ruby.network.routers1.msg_count.Persistent_Control::3 26
+system.ruby.network.routers1.msg_count.Persistent_Control::3 22
system.ruby.network.routers1.msg_bytes.Request_Control::1 11064
system.ruby.network.routers1.msg_bytes.Request_Control::2 9568
system.ruby.network.routers1.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 7744
-system.ruby.network.routers1.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 3.432237
+system.ruby.network.routers1.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 3.259706
system.ruby.network.routers2.msg_count.Request_Control::2 1196
system.ruby.network.routers2.msg_count.Response_Data::4 1179
system.ruby.network.routers2.msg_count.Writeback_Data::4 229
system.ruby.network.routers2.msg_count.Writeback_Control::4 968
-system.ruby.network.routers2.msg_count.Persistent_Control::3 26
+system.ruby.network.routers2.msg_count.Persistent_Control::3 22
system.ruby.network.routers2.msg_bytes.Request_Control::2 9568
system.ruby.network.routers2.msg_bytes.Response_Data::4 84888
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 7744
-system.ruby.network.routers2.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 4.665460
+system.ruby.network.routers2.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized 4.430959
system.ruby.network.routers3.msg_count.Request_Control::1 1383
system.ruby.network.routers3.msg_count.Request_Control::2 1196
system.ruby.network.routers3.msg_count.Response_Data::4 1179
@@ -458,7 +467,7 @@ system.ruby.network.routers3.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers3.msg_count.Response_Control::4 1
system.ruby.network.routers3.msg_count.Writeback_Data::4 1584
system.ruby.network.routers3.msg_count.Writeback_Control::4 968
-system.ruby.network.routers3.msg_count.Persistent_Control::3 52
+system.ruby.network.routers3.msg_count.Persistent_Control::3 44
system.ruby.network.routers3.msg_bytes.Request_Control::1 11064
system.ruby.network.routers3.msg_bytes.Request_Control::2 9568
system.ruby.network.routers3.msg_bytes.Response_Data::4 84888
@@ -466,47 +475,47 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers3.msg_bytes.Response_Control::4 8
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 114048
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 7744
-system.ruby.network.routers3.msg_bytes.Persistent_Control::3 416
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.msg_bytes.Persistent_Control::3 352
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 7737
system.ruby.network.msg_count.Response_Data 3537
system.ruby.network.msg_count.ResponseL2hit_Data 612
system.ruby.network.msg_count.Response_Control 3
system.ruby.network.msg_count.Writeback_Data 4752
system.ruby.network.msg_count.Writeback_Control 2904
-system.ruby.network.msg_count.Persistent_Control 156
+system.ruby.network.msg_count.Persistent_Control 132
system.ruby.network.msg_byte.Request_Control 61896
system.ruby.network.msg_byte.Response_Data 254664
system.ruby.network.msg_byte.ResponseL2hit_Data 44064
system.ruby.network.msg_byte.Response_Control 24
system.ruby.network.msg_byte.Writeback_Data 342144
system.ruby.network.msg_byte.Writeback_Control 23232
-system.ruby.network.msg_byte.Persistent_Control 1248
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 108253 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 5.761503
+system.ruby.network.msg_byte.Persistent_Control 1056
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 113952 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 5.471602
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
-system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 26
+system.ruby.network.routers0.throttle0.msg_count.Persistent_Control::3 22
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers0.throttle1.link_utilization 6.283429
+system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers0.throttle1.link_utilization 5.967425
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 1383
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 1355
-system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 26
+system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 22
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 11064
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 97560
-system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers1.throttle0.link_utilization 6.283429
+system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers1.throttle0.link_utilization 5.967425
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 1383
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 1355
-system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 26
+system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 22
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 11064
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 97560
-system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers1.throttle1.link_utilization 2.799922
+system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers1.throttle1.link_utilization 2.659892
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 1196
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
@@ -517,96 +526,96 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 14
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 7744
-system.ruby.network.routers2.throttle0.link_utilization 1.963456
+system.ruby.network.routers2.throttle0.link_utilization 1.863504
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 1196
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 229
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 968
-system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 26
+system.ruby.network.routers2.throttle0.msg_count.Persistent_Control::3 22
system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 9568
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 7744
-system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers2.throttle1.link_utilization 4.901019
+system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers2.throttle1.link_utilization 4.655908
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 1179
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 84888
-system.ruby.network.routers3.throttle0.link_utilization 5.749494
+system.ruby.network.routers3.throttle0.link_utilization 5.461949
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 1179
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 204
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 84888
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 14688
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers3.throttle1.link_utilization 6.283429
+system.ruby.network.routers3.throttle1.link_utilization 5.967425
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 1383
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 1355
-system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 26
+system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 22
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 11064
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 97560
-system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 208
-system.ruby.network.routers3.throttle2.link_utilization 1.963456
+system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 176
+system.ruby.network.routers3.throttle2.link_utilization 1.863504
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 1196
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 229
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 968
-system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 26
+system.ruby.network.routers3.throttle2.msg_count.Persistent_Control::3 22
system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 9568
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 16488
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 7744
-system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 208
+system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 176
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1185
-system.ruby.LD.latency_hist_seqr::mean 28.779747
-system.ruby.LD.latency_hist_seqr::gmean 6.012520
-system.ruby.LD.latency_hist_seqr::stdev 37.360727
-system.ruby.LD.latency_hist_seqr | 843 71.14% 71.14% | 337 28.44% 99.58% | 2 0.17% 99.75% | 0 0.00% 99.75% | 2 0.17% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 29.824473
+system.ruby.LD.latency_hist_seqr::gmean 6.089961
+system.ruby.LD.latency_hist_seqr::stdev 38.602832
+system.ruby.LD.latency_hist_seqr | 854 72.07% 72.07% | 327 27.59% 99.66% | 2 0.17% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 4
system.ruby.LD.hit_latency_hist_seqr::max_bucket 39
system.ruby.LD.hit_latency_hist_seqr::samples 759
-system.ruby.LD.hit_latency_hist_seqr::mean 4.030303
-system.ruby.LD.hit_latency_hist_seqr::gmean 1.520008
-system.ruby.LD.hit_latency_hist_seqr::stdev 7.784219
-system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 100 13.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::mean 4.025033
+system.ruby.LD.hit_latency_hist_seqr::gmean 1.519643
+system.ruby.LD.hit_latency_hist_seqr::stdev 7.772026
+system.ruby.LD.hit_latency_hist_seqr | 659 86.82% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 0 0.00% 86.82% | 1 0.13% 86.96% | 99 13.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 759
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 426
-system.ruby.LD.miss_latency_hist_seqr::mean 72.875587
-system.ruby.LD.miss_latency_hist_seqr::gmean 69.678801
-system.ruby.LD.miss_latency_hist_seqr::stdev 27.158723
-system.ruby.LD.miss_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 75.791080
+system.ruby.LD.miss_latency_hist_seqr::gmean 72.234894
+system.ruby.LD.miss_latency_hist_seqr::stdev 27.150058
+system.ruby.LD.miss_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 426
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 13.996532
-system.ruby.ST.latency_hist_seqr::gmean 2.581393
-system.ruby.ST.latency_hist_seqr::stdev 26.004028
-system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 78 9.02% 89.60% | 85 9.83% 99.42% | 3 0.35% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 14.804624
+system.ruby.ST.latency_hist_seqr::gmean 2.602855
+system.ruby.ST.latency_hist_seqr::stdev 29.163214
+system.ruby.ST.latency_hist_seqr | 697 80.58% 80.58% | 80 9.25% 89.83% | 83 9.60% 99.42% | 2 0.23% 99.65% | 0 0.00% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 4
system.ruby.ST.hit_latency_hist_seqr::max_bucket 39
system.ruby.ST.hit_latency_hist_seqr::samples 697
-system.ruby.ST.hit_latency_hist_seqr::mean 2.305595
-system.ruby.ST.hit_latency_hist_seqr::gmean 1.210352
-system.ruby.ST.hit_latency_hist_seqr::stdev 5.118132
-system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 21 3.01% 96.84% | 22 3.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.hit_latency_hist_seqr::mean 2.317073
+system.ruby.ST.hit_latency_hist_seqr::gmean 1.210984
+system.ruby.ST.hit_latency_hist_seqr::stdev 5.162159
+system.ruby.ST.hit_latency_hist_seqr | 654 93.83% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 0 0.00% 93.83% | 20 2.87% 96.70% | 23 3.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 697
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 168
-system.ruby.ST.miss_latency_hist_seqr::mean 62.500000
-system.ruby.ST.miss_latency_hist_seqr::gmean 59.782556
-system.ruby.ST.miss_latency_hist_seqr::stdev 21.264516
-system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 66.613095
+system.ruby.ST.miss_latency_hist_seqr::gmean 62.251080
+system.ruby.ST.miss_latency_hist_seqr::stdev 30.627944
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 168
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6413
-system.ruby.IFETCH.latency_hist_seqr::mean 8.354748
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.531676
-system.ruby.IFETCH.latency_hist_seqr::stdev 24.237273
-system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 5 0.08% 99.86% | 3 0.05% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 8.941369
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.542249
+system.ruby.IFETCH.latency_hist_seqr::stdev 26.742382
+system.ruby.IFETCH.latency_hist_seqr | 5828 90.88% 90.88% | 571 8.90% 99.78% | 4 0.06% 99.84% | 2 0.03% 99.88% | 4 0.06% 99.94% | 3 0.05% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 8
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 79
@@ -619,10 +628,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5828
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 585
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 79.200000
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.837583
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.345532
-system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.630769
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.856413
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.234733
+system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 585
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
@@ -634,18 +643,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 7080
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 8
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 79
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 204
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.691176
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.640301
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.636324
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.710784
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.661395
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.615711
system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 10.29% 10.29% | 182 89.22% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 204
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1179
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 74.535199
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 71.564149
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.099799
-system.ruby.Directory.miss_mach_latency_hist_seqr | 162 13.74% 13.74% | 996 84.48% 98.22% | 8 0.68% 98.90% | 4 0.34% 99.24% | 5 0.42% 99.66% | 4 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 79.365564
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 75.701428
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 33.123085
+system.ruby.Directory.miss_mach_latency_hist_seqr | 175 14.84% 14.84% | 983 83.38% 98.22% | 7 0.59% 98.81% | 3 0.25% 99.07% | 5 0.42% 99.49% | 5 0.42% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1179
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
@@ -683,17 +692,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 659
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 100
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 24
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 24.000000
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 100 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.960000
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.956283
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.400000
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 1.00% 1.00% | 99 99.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 100
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 426
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 72.875587
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 69.678801
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.158723
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 84 19.72% 19.72% | 337 79.11% 98.83% | 2 0.47% 99.30% | 0 0.00% 99.30% | 2 0.47% 99.77% | 1 0.23% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 75.791080
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 72.234894
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.150058
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 95 22.30% 22.30% | 327 76.76% 99.06% | 2 0.47% 99.53% | 0 0.00% 99.53% | 0 0.00% 99.53% | 2 0.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 426
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -705,18 +715,18 @@ system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::total 654
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::samples 43
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.162791
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.076919
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.963115
-system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 21 48.84% 48.84% | 22 51.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 22.348837
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 22.264733
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::stdev 1.938135
+system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 46.51% 46.51% | 23 53.49% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 43
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 168
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 62.500000
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 59.782556
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 21.264516
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 78 46.43% 46.43% | 85 50.60% 97.02% | 3 1.79% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 1 0.60% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 66.613095
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 62.251080
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 30.627944
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 80 47.62% 47.62% | 83 49.40% 97.02% | 2 1.19% 98.21% | 0 0.00% 98.21% | 1 0.60% 98.81% | 0 0.00% 98.81% | 1 0.60% 99.40% | 0 0.00% 99.40% | 1 0.60% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 168
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -736,15 +746,15 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 61
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 585
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 79.200000
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.837583
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.345532
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 5 0.85% 98.46% | 3 0.51% 98.97% | 3 0.51% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.630769
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.856413
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.234733
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 571 97.61% 97.61% | 4 0.68% 98.29% | 2 0.34% 98.63% | 4 0.68% 99.32% | 3 0.51% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 585
system.ruby.Directory_Controller.GETX 208 0.00% 0.00%
system.ruby.Directory_Controller.GETS 1017 0.00% 0.00%
-system.ruby.Directory_Controller.Lockdown 13 0.00% 0.00%
-system.ruby.Directory_Controller.Unlockdown 13 0.00% 0.00%
+system.ruby.Directory_Controller.Lockdown 11 0.00% 0.00%
+system.ruby.Directory_Controller.Unlockdown 11 0.00% 0.00%
system.ruby.Directory_Controller.Data_Owner 9 0.00% 0.00%
system.ruby.Directory_Controller.Data_All_Tokens 220 0.00% 0.00%
system.ruby.Directory_Controller.Ack_Owner 29 0.00% 0.00%
@@ -756,12 +766,11 @@ system.ruby.Directory_Controller.O.GETX 168 0.00% 0.00%
system.ruby.Directory_Controller.O.GETS 1011 0.00% 0.00%
system.ruby.Directory_Controller.O.Ack_All_Tokens 34 0.00% 0.00%
system.ruby.Directory_Controller.NO.GETX 17 0.00% 0.00%
-system.ruby.Directory_Controller.NO.Lockdown 2 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_Owner 9 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_All_Tokens 220 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner 29 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner_All_Tokens 905 0.00% 0.00%
-system.ruby.Directory_Controller.L.Unlockdown 13 0.00% 0.00%
+system.ruby.Directory_Controller.L.Unlockdown 11 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETX 23 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETS 6 0.00% 0.00%
system.ruby.Directory_Controller.O_W.Memory_Ack 229 0.00% 0.00%
@@ -775,8 +784,8 @@ system.ruby.L1Cache_Controller.L1_Replacement 1368 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_Shared 161 0.00% 0.00%
system.ruby.L1Cache_Controller.Data_All_Tokens 1222 0.00% 0.00%
system.ruby.L1Cache_Controller.Ack 1 0.00% 0.00%
-system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 26 0.00% 0.00%
-system.ruby.L1Cache_Controller.Request_Timeout 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.Own_Lock_or_Unlock 22 0.00% 0.00%
+system.ruby.L1Cache_Controller.Request_Timeout 11 0.00% 0.00%
system.ruby.L1Cache_Controller.Use_TimeoutNoStarvers 1221 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Load 526 0.00% 0.00%
system.ruby.L1Cache_Controller.NP.Ifetch 646 0.00% 0.00%
@@ -786,15 +795,15 @@ system.ruby.L1Cache_Controller.S.Ifetch 331 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Store 20 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 141 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 181 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 3194 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 3196 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 33 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 946 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 11 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Load 218 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Store 265 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.L1_Replacement 268 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Load 84 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch 2242 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch 2240 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Store 25 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.L1_Replacement 9 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 985 0.00% 0.00%
@@ -807,21 +816,21 @@ system.ruby.L1Cache_Controller.IM.Ack 1 0.00% 0.00%
system.ruby.L1Cache_Controller.SM.Data_All_Tokens 20 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_Shared 161 0.00% 0.00%
system.ruby.L1Cache_Controller.IS.Data_All_Tokens 1011 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 13 0.00% 0.00%
-system.ruby.L1Cache_Controller.IS.Request_Timeout 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Own_Lock_or_Unlock 11 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Request_Timeout 11 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS 1123 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETS_Last_Token 49 0.00% 0.00%
system.ruby.L2Cache_Controller.L1_GETX 211 0.00% 0.00%
system.ruby.L2Cache_Controller.L2_Replacement 1266 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_Shared_Data 84 0.00% 0.00%
system.ruby.L2Cache_Controller.Writeback_All_Tokens 1271 0.00% 0.00%
-system.ruby.L2Cache_Controller.Persistent_GETS 13 0.00% 0.00%
-system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.Persistent_GETS 11 0.00% 0.00%
+system.ruby.L2Cache_Controller.Own_Lock_or_Unlock 11 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETS 1011 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.L1_GETX 166 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_Shared_Data 81 0.00% 0.00%
system.ruby.L2Cache_Controller.NP.Writeback_All_Tokens 1193 0.00% 0.00%
-system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Own_Lock_or_Unlock 11 0.00% 0.00%
system.ruby.L2Cache_Controller.I.L1_GETX 1 0.00% 0.00%
system.ruby.L2Cache_Controller.I.L2_Replacement 69 0.00% 0.00%
system.ruby.L2Cache_Controller.I.Writeback_Shared_Data 3 0.00% 0.00%
@@ -835,6 +844,6 @@ system.ruby.L2Cache_Controller.O.Writeback_All_Tokens 57 0.00%
system.ruby.L2Cache_Controller.M.L1_GETS 112 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L1_GETX 26 0.00% 0.00%
system.ruby.L2Cache_Controller.M.L2_Replacement 1125 0.00% 0.00%
-system.ruby.L2Cache_Controller.I_L.Persistent_GETS 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.I_L.Persistent_GETS 11 0.00% 0.00%
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 2fd013908..293c2e7fd 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
@@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
from_memory_controller_latency=2
full_bit_dir_enabled=false
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
probeFilter=system.ruby.dir_cntrl0.probeFilter
probe_filter_enabled=false
recycle_latency=10
@@ -384,6 +410,7 @@ buffer_size=0
cache_response_latency=10
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
forwardToCache=system.ruby.l1_cntrl0.forwardToCache
issue_latency=2
@@ -391,6 +418,10 @@ l2_cache_hit_latency=10
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
no_mig_atomic=true
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestFromCache=system.ruby.l1_cntrl0.requestFromCache
responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -522,17 +553,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -560,18 +596,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
netifs=
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
ruby_system=system.ruby
topology=Crossbar
@@ -766,32 +807,234 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17
+power_model=Null
router_id=0
virt_nets=6
@@ -925,8 +1168,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17
+power_model=Null
router_id=1
virt_nets=6
@@ -1060,8 +1309,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
router_id=2
virt_nets=6
@@ -1236,9 +1491,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index 2d739759e..df46cff97 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 21:55:52
-gem5 started Mar 14 2016 21:57:33
-gem5 executing on phenom, pid 28167
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+gem5 compiled Oct 13 2016 20:24:36
+gem5 started Oct 13 2016 20:24:58
+gem5 executing on e108600-lin, pid 38872
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 86770 because target called exit()
+Exiting @ tick 93323 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 9d52394d3..56d6a64b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000087 # Number of seconds simulated
-sim_ticks 86770 # Number of ticks simulated
-final_tick 86770 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000093 # Number of seconds simulated
+sim_ticks 93323 # Number of ticks simulated
+final_tick 93323 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 95809 # Simulator instruction rate (inst/s)
-host_op_rate 95795 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1297998 # Simulator tick rate (ticks/s)
-host_mem_usage 453692 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 48908 # Simulator instruction rate (inst/s)
+host_op_rate 48899 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 712591 # Simulator tick rate (ticks/s)
+host_mem_usage 412484 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 74240 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 14080 # Number of bytes written to this memory
@@ -22,29 +22,29 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1160 #
system.mem_ctrls.num_reads::total 1160 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 220 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 220 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 855595252 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 855595252 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 162268065 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 162268065 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1017863317 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1017863317 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 795516646 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 795516646 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 150873847 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 150873847 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 946390493 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 946390493 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1160 # Number of read requests accepted
system.mem_ctrls.writeReqs 220 # Number of write requests accepted
system.mem_ctrls.readBursts 1160 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 220 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 63744 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 10496 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 5504 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM 63488 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 10752 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 5248 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 74240 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 14080 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.servicedByWrQ 168 # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts 109 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 86 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 52 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 82 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 77 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 93 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 90 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 18 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
@@ -54,13 +54,13 @@ system.mem_ctrls.perBankRdBursts::10 54 # Pe
system.mem_ctrls.perBankRdBursts::11 47 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12 22 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13 358 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 61 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 60 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 41 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 19 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 17 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 6 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts
@@ -69,12 +69,12 @@ system.mem_ctrls.perBankWrBursts::9 0 # Pe
system.mem_ctrls.perBankWrBursts::10 2 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 17 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 15 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 42 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 86698 # Total gap between requests
+system.mem_ctrls.totGap 93245 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 220 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 996 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 992 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -136,8 +136,8 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 4 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 4 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19 6 # What write queue length does an incoming req see
@@ -146,10 +146,10 @@ system.mem_ctrls.wrQLenPdf::21 6 # Wh
system.mem_ctrls.wrQLenPdf::22 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 6 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 5 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 5 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 6 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 5 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31 5 # What write queue length does an incoming req see
@@ -185,87 +185,98 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 191 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 358.869110 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 215.937059 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 347.377875 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 57 29.84% 29.84% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 46 24.08% 53.93% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 20 10.47% 64.40% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 14 7.33% 71.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 10 5.24% 76.96% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 4 2.09% 79.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 7 3.66% 82.72% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 8 4.19% 86.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 25 13.09% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 191 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 185 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 364.627027 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 225.304848 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 344.102671 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 47 25.41% 25.41% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 51 27.57% 52.97% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 22 11.89% 64.86% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 11 5.95% 70.81% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 10 5.41% 76.22% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 6 3.24% 79.46% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 6 3.24% 82.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 9 4.86% 87.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 23 12.43% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 185 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 5 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 143.400000 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 107.861440 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 83.476344 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 135.600000 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 103.520831 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 76.774345 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::16-23 1 20.00% 20.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::120-127 1 20.00% 40.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::128-135 1 20.00% 60.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::216-223 2 40.00% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::184-191 1 20.00% 80.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::216-223 1 20.00% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 5 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 5 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 17.200000 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 17.171629 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 1.095445 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 2 40.00% 40.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 3 60.00% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.400000 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.381380 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.894427 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 4 80.00% 80.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 1 20.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 5 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 6142 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 25066 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4980 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.17 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 12811 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 31659 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4960 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 12.91 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.17 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 734.63 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 63.43 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 855.60 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 162.27 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.91 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 680.30 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 56.23 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 795.52 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 150.87 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 6.23 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 5.74 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.50 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 5.75 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 5.31 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.44 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 20.55 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 808 # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen 22.62 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 805 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 78 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.12 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 81.15 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 70.27 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 62.82 # Average gap between requests
-system.mem_ctrls.pageHitRate 80.04 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 476280 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 264600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 5091840 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 259200 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 50178924 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 7527000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 69392004 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 807.766675 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 12759 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 70795 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 967680 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 537600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 7200960 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 632448 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 5594160 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 57849984 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 798000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 73580832 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 856.527274 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 910 # Time in different power states
+system.mem_ctrls.avgGap 67.57 # Average gap between requests
+system.mem_ctrls.pageHitRate 80.05 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 449820 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 235704 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 4672416 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 192096 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 7678128 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 246528 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 28111488 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 4554240 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 1112640 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 54628740 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 585.372738 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 75800 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 328 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 2335 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 11860 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 14026 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 61648 # Time in different power states
+system.mem_ctrls_1.actEnergy 913920 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 479136 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 6660192 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 492768 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 10312440 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 226560 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 31424328 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 462720 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 57733104 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 618.637463 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 69937 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 212 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 82150 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 1205 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 20133 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 68913 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -300,8 +311,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 86770 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 86770 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 93323 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 93323 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6403 # Number of instructions committed
@@ -320,7 +331,7 @@ system.cpu.num_mem_refs 2060 # nu
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 86770 # Number of busy cycles
+system.cpu.num_busy_cycles 93323 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1056 # Number of branches fetched
@@ -360,7 +371,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 8464
@@ -371,10 +382,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8463
-system.ruby.latency_hist_seqr::mean 9.252865
-system.ruby.latency_hist_seqr::gmean 1.840314
-system.ruby.latency_hist_seqr::stdev 22.282539
-system.ruby.latency_hist_seqr | 8231 97.26% 97.26% | 222 2.62% 99.88% | 0 0.00% 99.88% | 1 0.01% 99.89% | 7 0.08% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 10.027177
+system.ruby.latency_hist_seqr::gmean 1.860537
+system.ruby.latency_hist_seqr::stdev 25.112208
+system.ruby.latency_hist_seqr | 8219 97.12% 97.12% | 231 2.73% 99.85% | 1 0.01% 99.86% | 1 0.01% 99.87% | 5 0.06% 99.93% | 5 0.06% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 2
system.ruby.hit_latency_hist_seqr::max_bucket 19
@@ -387,16 +398,16 @@ system.ruby.hit_latency_hist_seqr::total 7303
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1160
-system.ruby.miss_latency_hist_seqr::mean 59.460345
-system.ruby.miss_latency_hist_seqr::gmean 56.276317
-system.ruby.miss_latency_hist_seqr::stdev 26.160126
-system.ruby.miss_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 65.109483
+system.ruby.miss_latency_hist_seqr::gmean 60.947221
+system.ruby.miss_latency_hist_seqr::stdev 32.683425
+system.ruby.miss_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00%
system.ruby.miss_latency_hist_seqr::total 1160
system.ruby.Directory.incomplete_times_seqr 1159
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 1333 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 717 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 2050 # Number of cache demand accesses
@@ -406,12 +417,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 6413
system.ruby.l1_cntrl0.L2cache.demand_hits 203 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 1160 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 1363 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 7 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 5.172295
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 4.809104
system.ruby.network.routers0.msg_count.Request_Control::2 1160
system.ruby.network.routers0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.msg_count.Writeback_Data::5 220
@@ -426,8 +437,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 9280
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 5.172006
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 4.808836
system.ruby.network.routers1.msg_count.Request_Control::2 1160
system.ruby.network.routers1.msg_count.Response_Data::4 1160
system.ruby.network.routers1.msg_count.Writeback_Data::5 220
@@ -442,8 +453,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 9272
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 5.172295
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 4.809104
system.ruby.network.routers2.msg_count.Request_Control::2 1160
system.ruby.network.routers2.msg_count.Response_Data::4 1160
system.ruby.network.routers2.msg_count.Writeback_Data::5 220
@@ -458,7 +469,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 9152
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 9280
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3480
system.ruby.network.msg_count.Response_Data 3480
system.ruby.network.msg_count.Writeback_Data 660
@@ -469,13 +480,13 @@ system.ruby.network.msg_byte.Response_Data 250560
system.ruby.network.msg_byte.Writeback_Data 47520
system.ruby.network.msg_byte.Writeback_Control 77088
system.ruby.network.msg_byte.Unblock_Control 27832
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86770 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 6.675118
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 93323 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 6.206401
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1160
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1144
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 83520
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 9152
-system.ruby.network.routers0.throttle1.link_utilization 3.669471
+system.ruby.network.routers0.throttle1.link_utilization 3.411806
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 1160
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 220
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 1144
@@ -486,7 +497,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 9280
-system.ruby.network.routers1.throttle0.link_utilization 3.668895
+system.ruby.network.routers1.throttle0.link_utilization 3.411271
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 1160
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 220
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 1144
@@ -497,17 +508,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 9272
-system.ruby.network.routers1.throttle1.link_utilization 6.675118
+system.ruby.network.routers1.throttle1.link_utilization 6.206401
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1160
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1144
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 83520
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 9152
-system.ruby.network.routers2.throttle0.link_utilization 6.675118
+system.ruby.network.routers2.throttle0.link_utilization 6.206401
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1160
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1144
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 83520
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 9152
-system.ruby.network.routers2.throttle1.link_utilization 3.669471
+system.ruby.network.routers2.throttle1.link_utilization 3.411806
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 1160
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 220
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 1144
@@ -518,13 +529,13 @@ system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Data::5 15840
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::2 9152
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::5 7392
system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 9280
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::bucket_size 64
+system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1185
-system.ruby.LD.latency_hist_seqr::mean 21.677637
-system.ruby.LD.latency_hist_seqr::gmean 5.060853
-system.ruby.LD.latency_hist_seqr::stdev 30.245768
-system.ruby.LD.latency_hist_seqr | 853 71.98% 71.98% | 244 20.59% 92.57% | 84 7.09% 99.66% | 1 0.08% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 23.222785
+system.ruby.LD.latency_hist_seqr::gmean 5.170883
+system.ruby.LD.latency_hist_seqr::stdev 33.395677
+system.ruby.LD.latency_hist_seqr | 1100 92.83% 92.83% | 82 6.92% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 0 0.00% 99.75% | 3 0.25% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 2
system.ruby.LD.hit_latency_hist_seqr::max_bucket 19
@@ -534,21 +545,21 @@ system.ruby.LD.hit_latency_hist_seqr::gmean 1.390347
system.ruby.LD.hit_latency_hist_seqr::stdev 3.445311
system.ruby.LD.hit_latency_hist_seqr | 659 86.26% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 0 0.00% 86.26% | 105 13.74% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 764
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 421
-system.ruby.LD.miss_latency_hist_seqr::mean 56.707838
-system.ruby.LD.miss_latency_hist_seqr::gmean 52.779793
-system.ruby.LD.miss_latency_hist_seqr::stdev 25.484779
-system.ruby.LD.miss_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 61.057007
+system.ruby.LD.miss_latency_hist_seqr::gmean 56.073786
+system.ruby.LD.miss_latency_hist_seqr::stdev 29.948950
+system.ruby.LD.miss_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 421
system.ruby.ST.latency_hist_seqr::bucket_size 16
system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 10.558382
-system.ruby.ST.latency_hist_seqr::gmean 2.225841
-system.ruby.ST.latency_hist_seqr::stdev 20.458667
-system.ruby.ST.latency_hist_seqr | 707 81.73% 81.73% | 45 5.20% 86.94% | 0 0.00% 86.94% | 76 8.79% 95.72% | 33 3.82% 99.54% | 4 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 11.254335
+system.ruby.ST.latency_hist_seqr::gmean 2.251088
+system.ruby.ST.latency_hist_seqr::stdev 22.172254
+system.ruby.ST.latency_hist_seqr | 707 81.73% 81.73% | 44 5.09% 86.82% | 0 0.00% 86.82% | 73 8.44% 95.26% | 36 4.16% 99.42% | 4 0.46% 99.88% | 1 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 2
system.ruby.ST.hit_latency_hist_seqr::max_bucket 19
@@ -561,18 +572,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 707
system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
system.ruby.ST.miss_latency_hist_seqr::samples 158
-system.ruby.ST.miss_latency_hist_seqr::mean 51.240506
-system.ruby.ST.miss_latency_hist_seqr::gmean 48.407659
-system.ruby.ST.miss_latency_hist_seqr::stdev 15.670342
-system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 55.050633
+system.ruby.ST.miss_latency_hist_seqr::gmean 51.490981
+system.ruby.ST.miss_latency_hist_seqr::stdev 17.990372
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 158
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6413
-system.ruby.IFETCH.latency_hist_seqr::mean 6.780914
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.487888
-system.ruby.IFETCH.latency_hist_seqr::stdev 19.876102
-system.ruby.IFETCH.latency_hist_seqr | 6306 98.33% 98.33% | 100 1.56% 99.89% | 0 0.00% 99.89% | 1 0.02% 99.91% | 4 0.06% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 7.423359
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.501230
+system.ruby.IFETCH.latency_hist_seqr::stdev 22.823134
+system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 108 1.68% 99.84% | 1 0.02% 99.86% | 1 0.02% 99.88% | 5 0.08% 99.95% | 2 0.03% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19
@@ -585,10 +596,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5832
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 581
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 63.690189
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.418649
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 28.087678
-system.ruby.IFETCH.miss_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.781411
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.778682
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.410761
+system.ruby.IFETCH.miss_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 581
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
@@ -607,10 +618,10 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 203
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1160
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.460345
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 56.276317
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 26.160126
-system.ruby.Directory.miss_mach_latency_hist_seqr | 928 80.00% 80.00% | 222 19.14% 99.14% | 0 0.00% 99.14% | 1 0.09% 99.22% | 7 0.60% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 65.109483
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.947221
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.683425
+system.ruby.Directory.miss_mach_latency_hist_seqr | 916 78.97% 78.97% | 231 19.91% 98.88% | 1 0.09% 98.97% | 1 0.09% 99.05% | 5 0.43% 99.48% | 5 0.43% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 0 0.00% 99.91% | 1 0.09% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1160
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
@@ -652,13 +663,13 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 105 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 105
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 421
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.707838
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.779793
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 25.484779
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 89 21.14% 21.14% | 244 57.96% 79.10% | 84 19.95% 99.05% | 1 0.24% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 1 0.24% 99.52% | 2 0.48% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 61.057007
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 56.073786
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 29.948950
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 336 79.81% 79.81% | 82 19.48% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 0 0.00% 99.29% | 3 0.71% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 421
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -677,10 +688,10 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 33
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 158
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.240506
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.407659
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 15.670342
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 45 28.48% 28.48% | 0 0.00% 28.48% | 76 48.10% 76.58% | 33 20.89% 97.47% | 4 2.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.050633
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 51.490981
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 17.990372
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 27.85% 27.85% | 0 0.00% 27.85% | 73 46.20% 74.05% | 36 22.78% 96.84% | 4 2.53% 99.37% | 1 0.63% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 158
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -699,10 +710,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 65
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 581
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 63.690189
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.418649
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 28.087678
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 474 81.58% 81.58% | 100 17.21% 98.80% | 0 0.00% 98.80% | 1 0.17% 98.97% | 4 0.69% 99.66% | 2 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.781411
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.778682
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.410761
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 463 79.69% 79.69% | 108 18.59% 98.28% | 1 0.17% 98.45% | 1 0.17% 98.62% | 5 0.86% 99.48% | 2 0.34% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 581
system.ruby.Directory_Controller.GETX 185 0.00% 0.00%
system.ruby.Directory_Controller.GETS 1021 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 2d08f440e..6b91b5d29 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=12
dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
eventq_index=0
forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestToDir=system.ruby.dir_cntrl0.requestToDir
responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
forwardToCache=system.ruby.l1_cntrl0.forwardToCache
issue_latency=2
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestFromCache=system.ruby.l1_cntrl0.requestFromCache
responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -415,17 +446,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.cacheMemory
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -438,18 +474,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
netifs=
number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
ruby_system=system.ruby
topology=Crossbar
@@ -616,32 +657,206 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
router_id=0
virt_nets=5
@@ -754,8 +969,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
router_id=1
virt_nets=5
@@ -868,8 +1089,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
router_id=2
virt_nets=5
@@ -1016,9 +1243,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index ccfdd3697..f6f6f15a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -4,8 +4,7 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 9c35f4885..89adb8b85 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 21:54:46
-gem5 started Mar 14 2016 21:55:58
-gem5 executing on phenom, pid 28070
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28066
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 107065 because target called exit()
+Exiting @ tick 112490 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index a33abfe97..06dea8ad2 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000107 # Number of seconds simulated
-sim_ticks 107065 # Number of ticks simulated
-final_tick 107065 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000112 # Number of seconds simulated
+sim_ticks 112490 # Number of ticks simulated
+final_tick 112490 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 58028 # Simulator instruction rate (inst/s)
-host_op_rate 58023 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 970128 # Simulator tick rate (ticks/s)
-host_mem_usage 456600 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 94486 # Simulator instruction rate (inst/s)
+host_op_rate 94411 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1658372 # Simulator tick rate (ticks/s)
+host_mem_usage 414356 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6403 # Number of instructions simulated
sim_ops 6403 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 110784 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 110528 # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 1731 #
system.mem_ctrls.num_reads::total 1731 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 1727 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 1727 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 1034735908 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 1034735908 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 1032344837 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 1032344837 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 2067080745 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 2067080745 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 984834207 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 984834207 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 982558450 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 982558450 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1967392657 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1967392657 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 1731 # Number of read requests accepted
system.mem_ctrls.writeReqs 1727 # Number of write requests accepted
system.mem_ctrls.readBursts 1731 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 1727 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 56512 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 54272 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 57856 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM 56704 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 54080 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 57088 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 110784 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 110528 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 848 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 792 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ 845 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 803 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.mem_ctrls.perBankRdBursts::0 85 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::1 47 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::2 74 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::3 68 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 112 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::0 83 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::1 50 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::2 70 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::3 63 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 108 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 23 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7 3 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9 1 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 49 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 33 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 17 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 263 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::14 79 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::15 28 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::0 83 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::1 47 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::2 80 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 68 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 133 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::5 25 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 55 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 36 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 18 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 270 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::14 81 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::15 24 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::0 82 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::1 51 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::2 73 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 60 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 126 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::5 27 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6 1 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 4 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 3 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9 1 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 46 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::11 28 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::12 11 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 50 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::11 33 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::12 12 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13 268 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 81 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::15 28 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::15 24 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 106993 # Total gap between requests
+system.mem_ctrls.totGap 112412 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 1727 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 883 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 886 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -136,15 +136,15 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 9 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 10 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 57 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 56 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 57 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 57 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 56 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 60 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 57 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26 56 # What write queue length does an incoming req see
@@ -152,9 +152,9 @@ system.mem_ctrls.wrQLenPdf::27 56 # Wh
system.mem_ctrls.wrQLenPdf::28 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30 56 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 55 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 56 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32 55 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see
@@ -185,90 +185,100 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 275 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 406.341818 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 258.682678 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 357.059585 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 55 20.00% 20.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 74 26.91% 46.91% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 37 13.45% 60.36% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 16 5.82% 66.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 18 6.55% 72.73% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 12 4.36% 77.09% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 8 2.91% 80.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 6 2.18% 82.18% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 49 17.82% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 275 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 264 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 424 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 260.079273 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 372.426347 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 66 25.00% 25.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 58 21.97% 46.97% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 27 10.23% 57.20% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 16 6.06% 63.26% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 17 6.44% 69.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 8 3.03% 72.73% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 12 4.55% 77.27% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 10 3.79% 81.06% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 50 18.94% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 264 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 55 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 15.781818 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 15.596648 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 2.973282 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 4 7.27% 7.27% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 25 45.45% 52.73% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 21 38.18% 90.91% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 15.818182 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 15.638991 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 2.938196 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::12-13 3 5.45% 5.45% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 24 43.64% 49.09% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 23 41.82% 90.91% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::18-19 4 7.27% 98.18% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::34-35 1 1.82% 100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total 55 # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples 55 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.436364 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.408895 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.995613 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 45 81.82% 81.82% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 2 3.64% 85.45% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::18 2 3.64% 89.09% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 6 10.91% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.218182 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.206001 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 0.658025 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 49 89.09% 89.09% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::17 1 1.82% 90.91% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 4 7.27% 98.18% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 1 1.82% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 55 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 10887 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 27664 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 4415 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 12.33 # Average queueing delay per DRAM burst
+system.mem_ctrls.totQLat 16225 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 33059 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 4430 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 18.31 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 31.33 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 527.83 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 540.38 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 1034.74 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 1032.34 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 37.31 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 504.08 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 507.49 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 984.83 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 982.56 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 8.35 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.12 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 4.22 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 7.90 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 3.94 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 3.96 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 26.13 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 670 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 835 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 75.88 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 89.30 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 30.94 # Average gap between requests
-system.mem_ctrls.pageHitRate 82.78 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 876960 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 487200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 4992000 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 4489344 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 63943740 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 4795800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 86196324 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 849.408975 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 8418 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 90483 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 1156680 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 642600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 5366400 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 4385664 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 65375352 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 3540000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 87077976 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 858.097085 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 5471 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 92641 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.avgWrQLen 26.10 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 674 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 833 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 76.07 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 90.15 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 32.51 # Average gap between requests
+system.mem_ctrls.pageHitRate 83.26 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 735420 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 4581024 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 3532896 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 13923048 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 195072 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 30921360 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 5237376 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 68117556 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 605.543213 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 81406 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 88 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 3640 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 13639 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 27313 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 67810 # Time in different power states
+system.mem_ctrls_1.actEnergy 1199520 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 633696 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 5540640 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 3917088 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 12524952 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 314880 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 33139344 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 4427136 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 70302216 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 624.964139 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 83983 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 260 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 3640 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 11529 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 24387 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 72674 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -303,8 +313,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 107065 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 107065 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 112490 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 112490 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6403 # Number of instructions committed
@@ -323,7 +333,7 @@ system.cpu.num_mem_refs 2060 # nu
system.cpu.num_load_insts 1192 # Number of load instructions
system.cpu.num_store_insts 868 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 107065 # Number of busy cycles
+system.cpu.num_busy_cycles 112490 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 1056 # Number of branches fetched
@@ -363,7 +373,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 6413 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3458 # delay histogram for all message
@@ -379,10 +389,10 @@ system.ruby.outstanding_req_hist_seqr::total 8464
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 8463
-system.ruby.latency_hist_seqr::mean 11.650951
-system.ruby.latency_hist_seqr::gmean 2.202191
-system.ruby.latency_hist_seqr::stdev 25.742711
-system.ruby.latency_hist_seqr | 8220 97.13% 97.13% | 190 2.25% 99.37% | 41 0.48% 99.86% | 1 0.01% 99.87% | 6 0.07% 99.94% | 4 0.05% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 12.291977
+system.ruby.latency_hist_seqr::gmean 2.221869
+system.ruby.latency_hist_seqr::stdev 27.407806
+system.ruby.latency_hist_seqr | 7608 89.90% 89.90% | 798 9.43% 99.33% | 40 0.47% 99.80% | 5 0.06% 99.86% | 6 0.07% 99.93% | 6 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 8463
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
@@ -394,21 +404,21 @@ system.ruby.hit_latency_hist_seqr::total 6732
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 1731
-system.ruby.miss_latency_hist_seqr::mean 53.073368
-system.ruby.miss_latency_hist_seqr::gmean 47.451096
-system.ruby.miss_latency_hist_seqr::stdev 32.911544
-system.ruby.miss_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 56.207395
+system.ruby.miss_latency_hist_seqr::gmean 49.560362
+system.ruby.miss_latency_hist_seqr::stdev 35.333412
+system.ruby.miss_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 1731
system.ruby.Directory.incomplete_times_seqr 1730
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 6732 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 1731 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8463 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 8.074534
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 7.685128
system.ruby.network.routers0.msg_count.Control::2 1731
system.ruby.network.routers0.msg_count.Data::2 1727
system.ruby.network.routers0.msg_count.Response_Data::4 1731
@@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 13848
system.ruby.network.routers0.msg_bytes.Data::2 124344
system.ruby.network.routers0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 13816
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 8.074534
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 7.685128
system.ruby.network.routers1.msg_count.Control::2 1731
system.ruby.network.routers1.msg_count.Data::2 1727
system.ruby.network.routers1.msg_count.Response_Data::4 1731
@@ -427,8 +437,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 13848
system.ruby.network.routers1.msg_bytes.Data::2 124344
system.ruby.network.routers1.msg_bytes.Response_Data::4 124632
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 13816
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 8.074534
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 7.685128
system.ruby.network.routers2.msg_count.Control::2 1731
system.ruby.network.routers2.msg_count.Data::2 1727
system.ruby.network.routers2.msg_count.Response_Data::4 1731
@@ -437,7 +447,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 13848
system.ruby.network.routers2.msg_bytes.Data::2 124344
system.ruby.network.routers2.msg_bytes.Response_Data::4 124632
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 13816
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 5193
system.ruby.network.msg_count.Data 5181
system.ruby.network.msg_count.Response_Data 5193
@@ -446,33 +456,33 @@ system.ruby.network.msg_byte.Control 41544
system.ruby.network.msg_byte.Data 373032
system.ruby.network.msg_byte.Response_Data 373896
system.ruby.network.msg_byte.Writeback_Control 41448
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 107065 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 8.082006
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 112490 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 7.692239
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1731
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1727
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 13816
-system.ruby.network.routers0.throttle1.link_utilization 8.067062
+system.ruby.network.routers0.throttle1.link_utilization 7.678016
system.ruby.network.routers0.throttle1.msg_count.Control::2 1731
system.ruby.network.routers0.throttle1.msg_count.Data::2 1727
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 13848
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 124344
-system.ruby.network.routers1.throttle0.link_utilization 8.067062
+system.ruby.network.routers1.throttle0.link_utilization 7.678016
system.ruby.network.routers1.throttle0.msg_count.Control::2 1731
system.ruby.network.routers1.throttle0.msg_count.Data::2 1727
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 13848
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 124344
-system.ruby.network.routers1.throttle1.link_utilization 8.082006
+system.ruby.network.routers1.throttle1.link_utilization 7.692239
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1731
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1727
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 124632
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 13816
-system.ruby.network.routers2.throttle0.link_utilization 8.082006
+system.ruby.network.routers2.throttle0.link_utilization 7.692239
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1731
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1727
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 124632
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 13816
-system.ruby.network.routers2.throttle1.link_utilization 8.067062
+system.ruby.network.routers2.throttle1.link_utilization 7.678016
system.ruby.network.routers2.throttle1.msg_count.Control::2 1731
system.ruby.network.routers2.throttle1.msg_count.Data::2 1727
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 13848
@@ -490,10 +500,10 @@ system.ruby.delayVCHist.vnet_2::total 1727 # de
system.ruby.LD.latency_hist_seqr::bucket_size 64
system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 1185
-system.ruby.LD.latency_hist_seqr::mean 31.532489
-system.ruby.LD.latency_hist_seqr::gmean 10.421226
-system.ruby.LD.latency_hist_seqr::stdev 34.906160
-system.ruby.LD.latency_hist_seqr | 1091 92.07% 92.07% | 75 6.33% 98.40% | 15 1.27% 99.66% | 0 0.00% 99.66% | 2 0.17% 99.83% | 1 0.08% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 33.356118
+system.ruby.LD.latency_hist_seqr::gmean 10.708915
+system.ruby.LD.latency_hist_seqr::stdev 36.387225
+system.ruby.LD.latency_hist_seqr | 862 72.74% 72.74% | 301 25.40% 98.14% | 16 1.35% 99.49% | 3 0.25% 99.75% | 1 0.08% 99.83% | 2 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 1185
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
@@ -505,18 +515,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 457
system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 728
-system.ruby.LD.miss_latency_hist_seqr::mean 50.699176
-system.ruby.LD.miss_latency_hist_seqr::gmean 45.385232
-system.ruby.LD.miss_latency_hist_seqr::stdev 32.101179
-system.ruby.LD.miss_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 53.667582
+system.ruby.LD.miss_latency_hist_seqr::gmean 47.442261
+system.ruby.LD.miss_latency_hist_seqr::stdev 32.940895
+system.ruby.LD.miss_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 728
system.ruby.ST.latency_hist_seqr::bucket_size 32
system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 865
-system.ruby.ST.latency_hist_seqr::mean 16.426590
-system.ruby.ST.latency_hist_seqr::gmean 3.318487
-system.ruby.ST.latency_hist_seqr::stdev 28.264983
-system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 242 27.98% 96.42% | 21 2.43% 98.84% | 1 0.12% 98.96% | 4 0.46% 99.42% | 4 0.46% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.12% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 17.479769
+system.ruby.ST.latency_hist_seqr::gmean 3.361529
+system.ruby.ST.latency_hist_seqr::stdev 31.340829
+system.ruby.ST.latency_hist_seqr | 592 68.44% 68.44% | 160 18.50% 86.94% | 102 11.79% 98.73% | 0 0.00% 98.73% | 4 0.46% 99.19% | 4 0.46% 99.65% | 1 0.12% 99.77% | 0 0.00% 99.77% | 1 0.12% 99.88% | 1 0.12% 100.00%
system.ruby.ST.latency_hist_seqr::total 865
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@@ -528,18 +538,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 592
system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 273
-system.ruby.ST.miss_latency_hist_seqr::mean 49.879121
-system.ruby.ST.miss_latency_hist_seqr::gmean 44.729882
-system.ruby.ST.miss_latency_hist_seqr::stdev 29.942777
-system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 53.216117
+system.ruby.ST.miss_latency_hist_seqr::gmean 46.594106
+system.ruby.ST.miss_latency_hist_seqr::stdev 35.315815
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 273
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 6413
-system.ruby.IFETCH.latency_hist_seqr::mean 7.333073
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.563492
-system.ruby.IFETCH.latency_hist_seqr::stdev 21.145733
-system.ruby.IFETCH.latency_hist_seqr | 6295 98.16% 98.16% | 93 1.45% 99.61% | 18 0.28% 99.89% | 1 0.02% 99.91% | 3 0.05% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 7.699984
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.571280
+system.ruby.IFETCH.latency_hist_seqr::stdev 22.534194
+system.ruby.IFETCH.latency_hist_seqr | 5994 93.47% 93.47% | 395 6.16% 99.63% | 16 0.25% 99.88% | 1 0.02% 99.89% | 3 0.05% 99.94% | 4 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 6413
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
@@ -551,18 +561,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 5683
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 730
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 56.635616
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 50.712708
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.440483
-system.ruby.IFETCH.miss_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 59.858904
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 52.975537
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 37.310775
+system.ruby.IFETCH.miss_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 730
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1731
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 53.073368
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 47.451096
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.911544
-system.ruby.Directory.miss_mach_latency_hist_seqr | 1488 85.96% 85.96% | 190 10.98% 96.94% | 41 2.37% 99.31% | 1 0.06% 99.36% | 6 0.35% 99.71% | 4 0.23% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 56.207395
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 49.560362
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.333412
+system.ruby.Directory.miss_mach_latency_hist_seqr | 876 50.61% 50.61% | 798 46.10% 96.71% | 40 2.31% 99.02% | 5 0.29% 99.31% | 6 0.35% 99.65% | 6 0.35% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 1731
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
@@ -593,26 +603,26 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 728
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 50.699176
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 45.385232
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.101179
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 634 87.09% 87.09% | 75 10.30% 97.39% | 15 2.06% 99.45% | 0 0.00% 99.45% | 2 0.27% 99.73% | 1 0.14% 99.86% | 1 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 53.667582
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 47.442261
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 32.940895
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 405 55.63% 55.63% | 301 41.35% 96.98% | 16 2.20% 99.18% | 3 0.41% 99.59% | 1 0.14% 99.73% | 2 0.27% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 728
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 273
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 49.879121
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 44.729882
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 29.942777
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 88.64% 88.64% | 21 7.69% 96.34% | 1 0.37% 96.70% | 4 1.47% 98.17% | 4 1.47% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 0 0.00% 99.63% | 1 0.37% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.216117
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.594106
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 35.315815
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 160 58.61% 58.61% | 102 37.36% 95.97% | 0 0.00% 95.97% | 4 1.47% 97.44% | 4 1.47% 98.90% | 1 0.37% 99.27% | 0 0.00% 99.27% | 1 0.37% 99.63% | 1 0.37% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 273
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 730
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 56.635616
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 50.712708
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.440483
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 612 83.84% 83.84% | 93 12.74% 96.58% | 18 2.47% 99.04% | 1 0.14% 99.18% | 3 0.41% 99.59% | 3 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 59.858904
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 52.975537
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 37.310775
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 311 42.60% 42.60% | 395 54.11% 96.71% | 16 2.19% 98.90% | 1 0.14% 99.04% | 3 0.41% 99.45% | 4 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 730
system.ruby.Directory_Controller.GETX 1731 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 1727 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
index ccd9350bc..220cfeeae 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/config.ini
@@ -149,7 +149,7 @@ useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -583,7 +583,7 @@ opClass=InstPrefetch
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -643,7 +643,7 @@ size=48
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -760,6 +760,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -771,7 +772,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -779,29 +780,36 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -821,6 +829,7 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
@@ -830,7 +839,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
@@ -852,9 +861,9 @@ tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
-tXP=0
+tXP=6000
tXPDLL=0
-tXS=0
+tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
index 115f46689..fff19a530 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:24
-gem5 executing on e108600-lin, pid 39579
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:45
+gem5 executing on e108600-lin, pid 28071
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/minor-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 20329000 because target called exit()
+Exiting @ tick 22083000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index 95775a988..a6e87b576 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000021 # Number of seconds simulated
-sim_ticks 20616000 # Number of ticks simulated
-final_tick 20616000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000022 # Number of seconds simulated
+sim_ticks 22083000 # Number of ticks simulated
+final_tick 22083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 91304 # Simulator instruction rate (inst/s)
-host_op_rate 91266 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 727585147 # Simulator tick rate (ticks/s)
-host_mem_usage 252076 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 143746 # Simulator instruction rate (inst/s)
+host_op_rate 143654 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1226490189 # Simulator tick rate (ticks/s)
+host_mem_usage 251004 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 19840 # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu
system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 310 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 698486612 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 263872720 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 962359333 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 698486612 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 698486612 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 698486612 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 263872720 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 962359333 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 652085314 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 246343341 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 898428656 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 652085314 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 652085314 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 652085314 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 246343341 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 898428656 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 310 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 310 # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 20527500 # Total gap between requests
+system.physmem.totGap 21988500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 61 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 62 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
@@ -188,77 +188,87 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 424.585366 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 277.937119 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 331.553388 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 429.268293 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 281.212133 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.776868 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5 12.20% 51.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2 4.88% 56.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 14.63% 70.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6 14.63% 53.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2 4.88% 58.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3 7.32% 65.85% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 2 4.88% 70.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 7 17.07% 87.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2 4.88% 92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation
-system.physmem.totQLat 1590750 # Total ticks spent queuing
-system.physmem.totMemAccLat 7403250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3615250 # Total ticks spent queuing
+system.physmem.totMemAccLat 9427750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1550000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5131.45 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 11662.10 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 23881.45 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 962.36 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30412.10 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 898.43 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 962.36 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 898.43 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 7.52 # Data bus utilization in percentage
-system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads
+system.physmem.busUtil 7.02 # Data bus utilization in percentage
+system.physmem.busUtilRead 7.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 260 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.87 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 66217.74 # Average gap between requests
+system.physmem.avgGap 70930.65 # Average gap between requests
system.physmem.pageHitRate 83.87 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 787800 # Energy for read commands per rank (pJ)
+system.physmem_0.actEnergy 114240 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 45540 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 885360 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 12758055 # Total energy per rank (pJ)
-system.physmem_0.averagePower 805.814306 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 727750 # Time in different power states
+system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1636470 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 32160 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 7529700 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 729120 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 12201870 # Total energy per rank (pJ)
+system.physmem_0.averagePower 552.527084 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 18356500 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 27500 # Time in different power states
system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1162200 # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 1898500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 3124750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 16512250 # Time in different power states
+system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1328040 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 10417320 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 361500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 13250265 # Total energy per rank (pJ)
-system.physmem_1.averagePower 836.902890 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 560000 # Time in different power states
+system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 2565570 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 217440 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 7221900 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 12935685 # Total energy per rank (pJ)
+system.physmem_1.averagePower 585.755816 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 15168500 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 498000 # Time in different power states
system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14766250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 794 # Number of BP lookups
-system.cpu.branchPred.condPredicted 394 # Number of conditional branches predicted
+system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 53000 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 5182750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 15829250 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 793 # Number of BP lookups
+system.cpu.branchPred.condPredicted 395 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 170 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 561 # Number of BTB lookups
system.cpu.branchPred.BTBHits 54 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 9.608541 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 9.625668 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 144 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups 83 # Number of indirect predictor lookups.
@@ -282,10 +292,10 @@ system.cpu.dtb.data_hits 813 # DT
system.cpu.dtb.data_misses 12 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 825 # DTB accesses
-system.cpu.itb.fetch_hits 979 # ITB hits
+system.cpu.itb.fetch_hits 980 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 992 # ITB accesses
+system.cpu.itb.fetch_accesses 993 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -299,16 +309,16 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 20616000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 41232 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 22083000 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 44166 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2585 # Number of instructions committed
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
system.cpu.discardedOps 573 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 15.950484 # CPI: cycles per instruction
-system.cpu.ipc 0.062694 # IPC: instructions per cycle
+system.cpu.cpi 17.085493 # CPI: cycles per instruction
+system.cpu.ipc 0.058529 # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass 189 7.31% 7.31% # Class of committed instruction
system.cpu.op_class_0::IntAlu 1678 64.91% 72.22% # Class of committed instruction
system.cpu.op_class_0::IntMult 1 0.04% 72.26% # Class of committed instruction
@@ -344,25 +354,25 @@ system.cpu.op_class_0::MemWrite 298 11.53% 100.00% # Cl
system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.op_class_0::total 2585 # Class of committed instruction
-system.cpu.tickCycles 5423 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 35809 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.cpu.tickCycles 5429 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 38737 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 48.342284 # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse 48.291787 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 48.342284 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 48.291787 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.011790 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.011790 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1673 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1673 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data 441 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 251 # number of WriteReq hits
@@ -379,14 +389,14 @@ system.cpu.dcache.demand_misses::cpu.data 102 # n
system.cpu.dcache.demand_misses::total 102 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 102 # number of overall misses
system.cpu.dcache.overall_misses::total 102 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4617500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4617500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3301000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3301000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7918500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7918500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7918500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7918500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5143500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5143500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 3553000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3553000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 8696500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 8696500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 8696500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 8696500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 500 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 500 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
@@ -403,14 +413,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.128463
system.cpu.dcache.demand_miss_rate::total 0.128463 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.128463 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.128463 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78262.711864 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 78262.711864 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76767.441860 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 76767.441860 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 77632.352941 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 77632.352941 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 77632.352941 # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87177.966102 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 87177.966102 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82627.906977 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 82627.906977 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 85259.803922 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 85259.803922 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 85259.803922 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -433,14 +443,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4487000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4487000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2044500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2044500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6531500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6531500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6531500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6531500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5007000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5007000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2203500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2203500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7210500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7210500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7210500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7210500 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.116000 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116000 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
@@ -449,67 +459,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.107053
system.cpu.dcache.demand_mshr_miss_rate::total 0.107053 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.107053 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.107053 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77362.068966 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77362.068966 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75722.222222 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75722.222222 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76841.176471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 76841.176471 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86327.586207 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86327.586207 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81611.111111 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81611.111111 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84829.411765 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 84829.411765 # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 119.307121 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 754 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 118.973491 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 755 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 225 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3.351111 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3.355556 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 119.307121 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.058255 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.058255 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 118.973491 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.058093 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.058093 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 225 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.109863 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 2183 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 2183 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 754 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 754 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 754 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 754 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 754 # number of overall hits
-system.cpu.icache.overall_hits::total 754 # number of overall hits
+system.cpu.icache.tags.tag_accesses 2185 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 2185 # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_hits::cpu.inst 755 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 755 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 755 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 755 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 225 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 225 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 225 # number of overall misses
system.cpu.icache.overall_misses::total 225 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17383000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17383000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17383000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17383000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17383000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17383000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 979 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 979 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 979 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 979 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 979 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 979 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229826 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.229826 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.229826 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.229826 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.229826 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.229826 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77257.777778 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 77257.777778 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 77257.777778 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 77257.777778 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 77257.777778 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 18729500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 18729500 # number of ReadReq miss cycles
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+system.cpu.icache.overall_miss_latency::cpu.inst 18729500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 18729500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 980 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 980 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 980 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 980 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229592 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.229592 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.229592 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.229592 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.229592 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.229592 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 83242.222222 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 83242.222222 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 83242.222222 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 83242.222222 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 83242.222222 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -522,43 +532,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 225
system.cpu.icache.demand_mshr_misses::total 225 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 225 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 17158000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 17158000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 17158000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229826 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.229826 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229826 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.229826 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76257.777778 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 76257.777778 # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18504500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 18504500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18504500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 18504500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18504500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 18504500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.229592 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.229592 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.229592 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.229592 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82242.222222 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82242.222222 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82242.222222 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 82242.222222 # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 167.807293 # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse 167.412677 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 310 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.421716 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 48.385576 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003644 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.001477 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.005121 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 119.080474 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data 48.332203 # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003634 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.001475 # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total 0.005109 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 310 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009460 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 2790 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 2790 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses
@@ -571,18 +581,18 @@ system.cpu.l2cache.demand_misses::total 310 # nu
system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses
system.cpu.l2cache.overall_misses::total 310 # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2004000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2004000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16820500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total 16820500 # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4399000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total 4399000 # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 16820500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6403000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 23223500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 16820500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6403000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 23223500 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2163000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2163000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18167000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 18167000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4919000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 4919000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 18167000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7082000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 25249000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 18167000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7082000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 25249000 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 225 # number of ReadCleanReq accesses(hits+misses)
@@ -607,18 +617,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74222.222222 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74222.222222 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74757.777778 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74757.777778 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75844.827586 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75844.827586 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 74914.516129 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74757.777778 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75329.411765 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 74914.516129 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80111.111111 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80111.111111 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80742.222222 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80742.222222 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84810.344828 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84810.344828 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 81448.387097 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80742.222222 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83317.647059 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 81448.387097 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -637,18 +647,18 @@ system.cpu.l2cache.demand_mshr_misses::total 310
system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 310 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1734000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1734000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14570500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14570500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3819000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3819000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14570500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5553000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 20123500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14570500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5553000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 20123500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1893000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1893000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 15917000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 15917000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4339000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4339000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15917000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6232000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 22149000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15917000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6232000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 22149000 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@@ -661,25 +671,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64222.222222 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64222.222222 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64757.777778 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64757.777778 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 65844.827586 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 65844.827586 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64757.777778 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65329.411765 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64914.516129 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70111.111111 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70111.111111 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70742.222222 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70742.222222 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74810.344828 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74810.344828 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70742.222222 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73317.647059 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71448.387097 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
@@ -705,9 +715,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 310 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 155000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 337500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 310 # Total number of requests made to the snoop filter.
@@ -716,7 +726,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 20616000 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 22083000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 283 # Transaction distribution
system.membus.trans_dist::ReadExReq 27 # Transaction distribution
system.membus.trans_dist::ReadExResp 27 # Transaction distribution
@@ -737,9 +747,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 310 # Request fanout histogram
-system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
+system.membus.reqLayer0.occupancy 362500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 1648750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 8.0 # Layer utilization (%)
+system.membus.respLayer1.utilization 7.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 39c72e110..ff6825b17 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -173,7 +173,7 @@ useIndirect=true
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -531,7 +531,7 @@ pipelined=false
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -591,7 +591,7 @@ size=48
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
@@ -708,6 +708,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -719,7 +720,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -727,29 +728,36 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -769,6 +777,7 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
@@ -778,7 +787,7 @@ p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
page_policy=open_adaptive
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
@@ -800,9 +809,9 @@ tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
-tXP=0
+tXP=6000
tXPDLL=0
-tXS=0
+tXS=270000
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 5515360ee..35f169b23 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 19 2016 12:23:51
-gem5 started Jul 19 2016 12:24:24
-gem5 executing on e108600-lin, pid 39577
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:49
+gem5 executing on e108600-lin, pid 28097
command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 12409500 because target called exit()
+Exiting @ tick 13358500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
index cdae5e837..cecea8f6e 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 12542500 # Number of ticks simulated
-final_tick 12542500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13358500 # Number of ticks simulated
+final_tick 13358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60996 # Simulator instruction rate (inst/s)
-host_op_rate 60977 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 320317516 # Simulator tick rate (ticks/s)
-host_mem_usage 253100 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 53089 # Simulator instruction rate (inst/s)
+host_op_rate 53060 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 296795260 # Simulator tick rate (ticks/s)
+host_mem_usage 251260 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory
system.physmem.bytes_read::total 17408 # Number of bytes read from this memory
@@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu
system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory
system.physmem.num_reads::total 272 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 954195735 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 433725334 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1387921068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 954195735 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 954195735 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 954195735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 433725334 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1387921068 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 895908972 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 407231351 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1303140323 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 895908972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 895908972 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 895908972 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 407231351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1303140323 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 272 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue
@@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 12445000 # Total gap between requests
+system.physmem.totGap 13255000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 157 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 155 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 80 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
@@ -188,81 +188,91 @@ system.physmem.wrQLenPdf::61 0 # Wh
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 384 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 235.532687 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 344.140835 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 4 11.11% 44.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 4 11.11% 55.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 6 16.67% 72.22% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2 5.56% 77.78% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1 2.78% 80.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1 2.78% 83.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation
-system.physmem.totQLat 1866000 # Total ticks spent queuing
-system.physmem.totMemAccLat 6966000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3364250 # Total ticks spent queuing
+system.physmem.totMemAccLat 8464250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 6860.29 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 12368.57 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 25610.29 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1387.92 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 31118.57 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1303.14 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1387.92 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1303.14 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 10.84 # Data bus utilization in percentage
-system.physmem.busUtilRead 10.84 # Data bus utilization in percentage for reads
+system.physmem.busUtil 10.18 # Data bus utilization in percentage
+system.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 226 # Number of row buffer hits during reads
+system.physmem.readRowHits 224 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 82.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 45753.68 # Average gap between requests
-system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 48731.62 # Average gap between requests
+system.physmem.pageHitRate 82.35 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 99960 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 37950 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ)
-system.physmem_0.averagePower 832.600901 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
+system.physmem_0.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1355460 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 21600 # Energy for precharge background per rank (pJ)
+system.physmem_0.actPowerDownEnergy 4583370 # Energy for active power-down per rank (pJ)
+system.physmem_0.prePowerDownEnergy 107040 # Energy for precharge power-down per rank (pJ)
+system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_0.totalEnergy 7576860 # Total energy per rank (pJ)
+system.physmem_0.averagePower 567.183307 # Core power per rank (mW)
+system.physmem_0.totalIdleTime 10278500 # Total Idle time Per DRAM Rank
+system.physmem_0.memoryStateTime::IDLE 28500 # Time in different power states
system.physmem_0.memoryStateTime::REF 260000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ)
+system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_0.memoryStateTime::PRE_PDN 279000 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 2735250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT_PDN 10055750 # Time in different power states
+system.physmem_1.actEnergy 242760 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 98670 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1185240 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 5198400 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 267750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 6961155 # Total energy per rank (pJ)
-system.physmem_1.averagePower 865.142768 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 432500 # Time in different power states
+system.physmem_1.refreshEnergy 614640.000000 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1822290 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 183840 # Energy for precharge background per rank (pJ)
+system.physmem_1.actPowerDownEnergy 4050420 # Energy for active power-down per rank (pJ)
+system.physmem_1.prePowerDownEnergy 480 # Energy for precharge power-down per rank (pJ)
+system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.physmem_1.totalEnergy 8198340 # Total energy per rank (pJ)
+system.physmem_1.averagePower 613.705624 # Core power per rank (mW)
+system.physmem_1.totalIdleTime 8246250 # Total Idle time Per DRAM Rank
+system.physmem_1.memoryStateTime::IDLE 450500 # Time in different power states
system.physmem_1.memoryStateTime::REF 260000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 7367500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 1001 # Number of BP lookups
-system.cpu.branchPred.condPredicted 492 # Number of conditional branches predicted
+system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
+system.physmem_1.memoryStateTime::PRE_PDN 1250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 3767500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT_PDN 8879250 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states
+system.cpu.branchPred.lookups 994 # Number of BP lookups
+system.cpu.branchPred.condPredicted 488 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 213 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 687 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 176 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 684 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 175 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 25.618632 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 25.584795 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 18 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 100 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 3 # Number of indirect target hits.
+system.cpu.branchPred.indirectLookups 99 # Number of indirect predictor lookups.
+system.cpu.branchPred.indirectHits 2 # Number of indirect target hits.
system.cpu.branchPred.indirectMisses 97 # Number of indirect misses.
system.cpu.branchPredindirectMispredicted 33 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
@@ -270,22 +280,22 @@ system.cpu.dtb.fetch_hits 0 # IT
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 712 # DTB read hits
-system.cpu.dtb.read_misses 13 # DTB read misses
+system.cpu.dtb.read_hits 705 # DTB read hits
+system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 725 # DTB read accesses
+system.cpu.dtb.read_accesses 715 # DTB read accesses
system.cpu.dtb.write_hits 349 # DTB write hits
-system.cpu.dtb.write_misses 17 # DTB write misses
+system.cpu.dtb.write_misses 16 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 366 # DTB write accesses
-system.cpu.dtb.data_hits 1061 # DTB hits
-system.cpu.dtb.data_misses 30 # DTB misses
+system.cpu.dtb.write_accesses 365 # DTB write accesses
+system.cpu.dtb.data_hits 1054 # DTB hits
+system.cpu.dtb.data_misses 26 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 1091 # DTB accesses
-system.cpu.itb.fetch_hits 877 # ITB hits
+system.cpu.dtb.data_accesses 1080 # DTB accesses
+system.cpu.itb.fetch_hits 872 # ITB hits
system.cpu.itb.fetch_misses 32 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 909 # ITB accesses
+system.cpu.itb.fetch_accesses 904 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -299,193 +309,193 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 12542500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 25086 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 13358500 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 26718 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 4377 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 6059 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 1001 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 399 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1174 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles 4379 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 6026 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 994 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 395 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 1172 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 472 # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingTrapStallCycles 1202 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 877 # Number of cache lines fetched
+system.cpu.fetch.CacheLines 872 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 147 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 6970 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.869297 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.271813 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 7018 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.858649 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.260497 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 5938 85.19% 85.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 27 0.39% 85.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 100 1.43% 87.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 87 1.25% 88.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 141 2.02% 90.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 81 1.16% 91.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 45 0.65% 92.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 76 1.09% 93.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 475 6.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 5993 85.39% 85.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 27 0.38% 85.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 97 1.38% 87.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 87 1.24% 88.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 140 1.99% 90.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 81 1.15% 91.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 45 0.64% 92.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 75 1.07% 93.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 473 6.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 6970 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.039903 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.241529 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 5221 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 627 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 919 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking
+system.cpu.fetch.rateDist::total 7018 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.037203 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.225541 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 5261 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 642 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 913 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 39 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 163 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 5274 # Number of instructions handled by decode
+system.cpu.decode.DecodedInsts 5228 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 263 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 163 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 5296 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 881 # Number of cycles rename is running
+system.cpu.rename.IdleCycles 5336 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 333 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 302 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 873 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 11 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 5069 # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts 5015 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RenamedOperands 3638 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5669 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 5662 # Number of integer rename lookups
+system.cpu.rename.RenamedOperands 3598 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5603 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 5596 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1870 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 1830 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 8 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 62 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 846 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 428 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
+system.cpu.memDep0.insertedLoads 838 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 424 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 4387 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 4336 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 3758 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 28 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 2005 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1025 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 3724 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1954 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 987 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 6970 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.539168 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.278867 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 7018 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.530636 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.266302 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 5524 79.25% 79.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 467 6.70% 85.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 343 4.92% 90.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 254 3.64% 94.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 193 2.77% 97.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 103 1.48% 98.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 56 0.80% 99.57% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 20 0.29% 99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 10 0.14% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 5580 79.51% 79.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 466 6.64% 86.15% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 341 4.86% 91.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 254 3.62% 94.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 190 2.71% 97.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 104 1.48% 98.82% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 55 0.78% 99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 20 0.28% 99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 6970 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 7018 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6 9.84% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 31 50.82% 60.66% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 24 39.34% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 10.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 30 50.00% 60.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 24 40.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 2627 69.90% 69.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.03% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 757 20.14% 90.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 373 9.93% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 2606 69.98% 69.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 1 0.03% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 745 20.01% 90.01% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 372 9.99% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 3758 # Type of FU issued
-system.cpu.iq.rate 0.149805 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 61 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.016232 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 14562 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 6395 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 3419 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 3724 # Type of FU issued
+system.cpu.iq.rate 0.139382 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 60 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.016112 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 14532 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 6293 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 3394 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 3812 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 3777 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 431 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 423 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 134 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 130 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 42 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 163 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 299 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 304 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 4700 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 4648 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 846 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 428 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 838 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 424 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
@@ -493,41 +503,41 @@ system.cpu.iew.memOrderViolationEvents 4 # Nu
system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 132 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 165 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 3634 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 727 # Number of load instructions executed
+system.cpu.iew.iewExecutedInsts 3600 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 717 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 124 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 307 # number of nop insts executed
-system.cpu.iew.exec_refs 1093 # number of memory reference insts executed
-system.cpu.iew.exec_branches 599 # Number of branches executed
-system.cpu.iew.exec_stores 366 # Number of stores executed
-system.cpu.iew.exec_rate 0.144862 # Inst execution rate
-system.cpu.iew.wb_sent 3483 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 3425 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1633 # num instructions producing a value
-system.cpu.iew.wb_consumers 2097 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.136530 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.778732 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 2122 # The number of squashed insts skipped by commit
+system.cpu.iew.exec_nop 306 # number of nop insts executed
+system.cpu.iew.exec_refs 1082 # number of memory reference insts executed
+system.cpu.iew.exec_branches 595 # Number of branches executed
+system.cpu.iew.exec_stores 365 # Number of stores executed
+system.cpu.iew.exec_rate 0.134741 # Inst execution rate
+system.cpu.iew.wb_sent 3453 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 3400 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1619 # num instructions producing a value
+system.cpu.iew.wb_consumers 2076 # num instructions consuming a value
+system.cpu.iew.wb_rate 0.127255 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.779865 # average fanout of values written-back
+system.cpu.commit.commitSquashedInsts 2070 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 140 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 6555 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.392982 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.248476 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 6610 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.389713 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.245121 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 5684 86.71% 86.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 198 3.02% 89.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 318 4.85% 94.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 118 1.80% 96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 63 0.96% 97.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 53 0.81% 98.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 37 0.56% 98.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 23 0.35% 99.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 61 0.93% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 5740 86.84% 86.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 197 2.98% 89.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 319 4.83% 94.64% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 117 1.77% 96.41% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 63 0.95% 97.37% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 53 0.80% 98.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 36 0.54% 98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 23 0.35% 99.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 62 0.94% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 6555 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 6610 # Number of insts commited each cycle
system.cpu.commit.committedInsts 2576 # Number of instructions committed
system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -573,47 +583,47 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
-system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 10945 # The number of ROB reads
-system.cpu.rob.rob_writes 9815 # The number of ROB writes
+system.cpu.commit.bw_lim_events 62 # number cycles where commit BW limit reached
+system.cpu.rob.rob_reads 10947 # The number of ROB reads
+system.cpu.rob.rob_writes 9704 # The number of ROB writes
system.cpu.timesIdled 154 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 18116 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 19700 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 10.509426 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 10.509426 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.095153 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.095153 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 4383 # number of integer regfile reads
-system.cpu.int_regfile_writes 2640 # number of integer regfile writes
+system.cpu.cpi 11.193129 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 11.193129 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.089341 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.089341 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 4344 # number of integer regfile reads
+system.cpu.int_regfile_writes 2618 # number of integer regfile writes
system.cpu.fp_regfile_reads 6 # number of floating regfile reads
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 45.419736 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 735 # Total number of references to valid blocks.
+system.cpu.dcache.tags.tagsinuse 45.378002 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 8.647059 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 45.419736 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.011089 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.011089 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data 45.378002 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.011079 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.011079 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1919 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1919 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 522 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 522 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 1935 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1935 # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_hits::cpu.data 530 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 530 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 735 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 735 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 735 # number of overall hits
-system.cpu.dcache.overall_hits::total 735 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits
+system.cpu.dcache.overall_hits::total 743 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
@@ -622,43 +632,43 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n
system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses
system.cpu.dcache.overall_misses::total 182 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 6754500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 6754500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5744000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5744000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12498500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12498500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12498500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 623 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 623 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 7124500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7124500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 6134000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 6134000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13258500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13258500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13258500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13258500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 631 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 631 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 917 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 917 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 917 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 917 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.162119 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.162119 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 925 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 925 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 925 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 925 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.160063 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.160063 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.198473 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.198473 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.198473 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.198473 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66876.237624 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 66876.237624 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70913.580247 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 70913.580247 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 68673.076923 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 68673.076923 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 68673.076923 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 260 # number of cycles access was blocked
+system.cpu.dcache.demand_miss_rate::cpu.data 0.196757 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.196757 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.196757 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.196757 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70539.603960 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 70539.603960 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75728.395062 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 75728.395062 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72848.901099 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 72848.901099 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72848.901099 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 269 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.333333 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.250000 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits
@@ -676,138 +686,138 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85
system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4858000 # number of ReadReq MSHR miss cycles
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@@ -820,18 +830,18 @@ system.cpu.l2cache.demand_misses::total 272 # nu
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-system.cpu.l2cache.demand_miss_latency::total 20883500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 14279500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6604000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20883500 # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1966500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1966500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 15354000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 15354000 # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5066000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 5066000 # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 15354000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7032500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22386500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 15354000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7032500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22386500 # number of overall miss cycles
system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 187 # number of ReadCleanReq accesses(hits+misses)
@@ -856,18 +866,18 @@ system.cpu.l2cache.demand_miss_rate::total 1 #
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76562.500000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76562.500000 # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76360.962567 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76360.962567 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78139.344262 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78139.344262 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 76777.573529 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76360.962567 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77694.117647 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 76777.573529 # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81937.500000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81937.500000 # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82106.951872 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82106.951872 # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83049.180328 # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83049.180328 # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 82303.308824 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82106.951872 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82735.294118 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 82303.308824 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -886,18 +896,18 @@ system.cpu.l2cache.demand_mshr_misses::total 272
system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1597500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1597500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12409500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12409500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4156500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4156500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12409500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5754000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 18163500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12409500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5754000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 18163500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1726500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1726500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13484000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13484000 # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4456000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4456000 # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13484000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6182500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 19666500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13484000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6182500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 19666500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
@@ -910,25 +920,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66562.500000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66562.500000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66360.962567 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66360.962567 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68139.344262 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68139.344262 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66360.962567 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67694.117647 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66777.573529 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71937.500000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71937.500000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72106.951872 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72106.951872 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73049.180328 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73049.180328 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72106.951872 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72735.294118 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72303.308824 # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 24 # Transaction distribution
@@ -954,9 +964,9 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 #
system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
+system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 280500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 127500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
system.membus.snoop_filter.tot_requests 272 # Total number of requests made to the snoop filter.
@@ -965,7 +975,7 @@ system.membus.snoop_filter.hit_multi_requests 0
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 12542500 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 13358500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 248 # Transaction distribution
system.membus.trans_dist::ReadExReq 24 # Transaction distribution
system.membus.trans_dist::ReadExResp 24 # Transaction distribution
@@ -987,8 +997,8 @@ system.membus.snoop_fanout::min_value 0 # Re
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 272 # Request fanout histogram
system.membus.reqLayer0.occupancy 337500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.7 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1440000 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 11.5 # Layer utilization (%)
+system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
+system.membus.respLayer1.occupancy 1437500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 10.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
index 214f11946..41209dc7f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,10 +270,15 @@ children=directory requestToDir responseFromDir responseFromMemory responseToDir
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=6
eventq_index=0
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestToDir=system.ruby.dir_cntrl0.requestToDir
responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -311,6 +337,7 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
enable_prefetch=false
eventq_index=0
l1_request_latency=2
@@ -319,6 +346,10 @@ l2_select_num_bits=0
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
optionalQueue=system.ruby.l1_cntrl0.optionalQueue
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
prefetcher=system.ruby.l1_cntrl0.prefetcher
recycle_latency=10
requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -447,17 +478,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -480,10 +516,15 @@ L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
l2_request_latency=2
l2_response_latency=2
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -574,18 +615,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
ruby_system=system.ruby
topology=Crossbar
@@ -748,42 +794,216 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
router_id=0
virt_nets=3
@@ -875,8 +1095,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
router_id=1
virt_nets=3
@@ -968,8 +1194,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
router_id=2
virt_nets=3
@@ -1061,8 +1293,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
router_id=3
virt_nets=3
@@ -1195,9 +1433,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
index 321d1816d..fcadeb2be 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simout
+Redirecting stderr to build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:01:33
-gem5 started Jan 21 2016 14:02:10
-gem5 executing on zizzer, pid 44711
-command line: build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
+gem5 compiled Oct 13 2016 20:28:06
+gem5 started Oct 13 2016 20:28:32
+gem5 executing on e108600-lin, pid 8237
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MESI_Two_Level/gem5.opt -d build/ALPHA_MESI_Two_Level/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_Two_Level
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 45733 because target called exit()
+Exiting @ tick 48659 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
index 5ca935512..d4dee56c3 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_Two_Level/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000046 # Number of seconds simulated
-sim_ticks 45733 # Number of ticks simulated
-final_tick 45733 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000049 # Number of seconds simulated
+sim_ticks 48659 # Number of ticks simulated
+final_tick 48659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 61876 # Simulator instruction rate (inst/s)
-host_op_rate 61863 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1097622 # Simulator tick rate (ticks/s)
-host_mem_usage 452416 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 43978 # Simulator instruction rate (inst/s)
+host_op_rate 43962 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 829814 # Simulator tick rate (ticks/s)
+host_mem_usage 410700 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 35008 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 35008 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 6592 # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 547 #
system.mem_ctrls.num_reads::total 547 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 103 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 103 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 765486629 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 765486629 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 144140992 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 144140992 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 909627621 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 909627621 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 719455805 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 719455805 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 135473396 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 135473396 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 854929201 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 854929201 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 547 # Number of read requests accepted
system.mem_ctrls.writeReqs 103 # Number of write requests accepted
system.mem_ctrls.readBursts 547 # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 45654 # Total gap between requests
+system.mem_ctrls.totGap 48574 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 74 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 358.054054 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 233.275053 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 307.922241 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 18 24.32% 24.32% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 18 24.32% 48.65% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 8 10.81% 59.46% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 4 5.41% 64.86% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 9 12.16% 77.03% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 7 9.46% 86.49% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 3 4.05% 90.54% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 1 1.35% 91.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 6 8.11% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 74 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 83 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 339.277108 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 221.785975 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 292.728223 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 23 27.71% 27.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 19 22.89% 50.60% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 6 7.23% 57.83% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 10 12.05% 69.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 11 13.25% 83.13% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 4.82% 87.95% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 3 3.61% 91.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 3.61% 95.18% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 4 4.82% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 83 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 268 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 268.000000 # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 2733 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 11055 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat 5659 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 13981 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 2190 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.24 # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat 12.92 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.24 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 612.95 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 22.39 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 765.49 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 144.14 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.92 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 576.09 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 21.04 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 719.46 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 135.47 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 4.96 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.79 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 4.67 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.50 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.16 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen 22.48 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 356 # Number of row buffer hits during reads
+system.mem_ctrls.readRowHits 349 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 81.28 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 79.68 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 70.24 # Average gap between requests
-system.mem_ctrls.pageHitRate 76.65 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 143640 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 79800 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 1797120 # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap 74.73 # Average gap between requests
+system.mem_ctrls.pageHitRate 75.21 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 199920 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 92736 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 2124864 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 26498844 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 269400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 31331604 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 799.479561 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 528 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 37581 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 362880 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 201600 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 2882880 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 26204040 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 528000 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 32888088 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 839.195917 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 754 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 37150 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.mem_ctrls_0.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 3071616 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 85248 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 18833256 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 153600 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 28249080 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 580.552005 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 41659 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 54 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::REF 1560 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 400 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 5344 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 41301 # Time in different power states
+system.mem_ctrls_1.actEnergy 442680 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 227976 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 2878848 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 3687840.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 4289136 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 272256 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 17021568 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 466944 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 29420880 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 604.633881 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 37647 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 541 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::REF 1560 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 1216 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 8014 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 37328 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 45733 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 45733 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 48659 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 48659 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 45733 # Number of busy cycles
+system.cpu.num_busy_cycles 48659 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 396 # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 3612 # delay histogram for all message
@@ -374,10 +384,10 @@ system.ruby.outstanding_req_hist_seqr::total 3295
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 3294
-system.ruby.latency_hist_seqr::mean 12.883728
-system.ruby.latency_hist_seqr::gmean 2.062291
-system.ruby.latency_hist_seqr::stdev 28.863704
-system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 432 13.11% 99.82% | 1 0.03% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 13.772010
+system.ruby.latency_hist_seqr::gmean 2.084389
+system.ruby.latency_hist_seqr::stdev 31.264017
+system.ruby.latency_hist_seqr | 2856 86.70% 86.70% | 431 13.08% 99.79% | 1 0.03% 99.82% | 0 0.00% 99.82% | 2 0.06% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 3294
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
@@ -389,12 +399,12 @@ system.ruby.hit_latency_hist_seqr::total 2722
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 572
-system.ruby.miss_latency_hist_seqr::mean 69.435315
-system.ruby.miss_latency_hist_seqr::gmean 64.604000
-system.ruby.miss_latency_hist_seqr::stdev 30.458568
-system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 432 75.52% 98.95% | 1 0.17% 99.13% | 0 0.00% 99.13% | 1 0.17% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 74.550699
+system.ruby.miss_latency_hist_seqr::gmean 68.693513
+system.ruby.miss_latency_hist_seqr::stdev 34.041428
+system.ruby.miss_latency_hist_seqr | 134 23.43% 23.43% | 431 75.35% 98.78% | 1 0.17% 98.95% | 0 0.00% 98.95% | 2 0.35% 99.30% | 4 0.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 572
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 437 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 272 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
@@ -410,15 +420,15 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu
system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched
system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages
system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 25 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 547 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 572 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 4.350250
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 4.088658
system.ruby.network.routers0.msg_count.Control::0 572
system.ruby.network.routers0.msg_count.Request_Control::2 431
system.ruby.network.routers0.msg_count.Response_Data::1 572
@@ -435,8 +445,8 @@ system.ruby.network.routers0.msg_bytes.Response_Control::2 2176
system.ruby.network.routers0.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers0.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 8.380163
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 7.876241
system.ruby.network.routers1.msg_count.Control::0 1119
system.ruby.network.routers1.msg_count.Request_Control::2 431
system.ruby.network.routers1.msg_count.Response_Data::1 1222
@@ -453,16 +463,16 @@ system.ruby.network.routers1.msg_bytes.Response_Control::2 2176
system.ruby.network.routers1.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers1.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 4.029913
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 3.787583
system.ruby.network.routers2.msg_count.Control::0 547
system.ruby.network.routers2.msg_count.Response_Data::1 650
system.ruby.network.routers2.msg_count.Response_Control::1 975
system.ruby.network.routers2.msg_bytes.Control::0 4376
system.ruby.network.routers2.msg_bytes.Response_Data::1 46800
system.ruby.network.routers2.msg_bytes.Response_Control::1 7800
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 5.586775
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized 5.250827
system.ruby.network.routers3.msg_count.Control::0 1119
system.ruby.network.routers3.msg_count.Request_Control::2 431
system.ruby.network.routers3.msg_count.Response_Data::1 1222
@@ -479,7 +489,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2 2176
system.ruby.network.routers3.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers3.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 632
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 3357
system.ruby.network.msg_count.Request_Control 1293
system.ruby.network.msg_count.Response_Data 3666
@@ -492,15 +502,15 @@ system.ruby.network.msg_byte.Response_Data 263952
system.ruby.network.msg_byte.Response_Control 41760
system.ruby.network.msg_byte.Writeback_Data 23112
system.ruby.network.msg_byte.Writeback_Control 1896
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 45733 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 6.235104
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 48659 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 5.860170
system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 431
system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 572
system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 124
system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 3448
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 41184
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 992
-system.ruby.network.routers0.throttle1.link_utilization 2.465397
+system.ruby.network.routers0.throttle1.link_utilization 2.317146
system.ruby.network.routers0.throttle1.msg_count.Control::0 572
system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 369
system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 272
@@ -513,7 +523,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 217
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers1.throttle0.link_utilization 8.437015
+system.ruby.network.routers1.throttle0.link_utilization 7.929674
system.ruby.network.routers1.throttle0.msg_count.Control::0 572
system.ruby.network.routers1.throttle0.msg_count.Response_Data::1 547
system.ruby.network.routers1.throttle0.msg_count.Response_Control::1 908
@@ -528,7 +538,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Response_Control::2 217
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers1.throttle1.link_utilization 8.323311
+system.ruby.network.routers1.throttle1.link_utilization 7.822808
system.ruby.network.routers1.throttle1.msg_count.Control::0 547
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 431
system.ruby.network.routers1.throttle1.msg_count.Response_Data::1 675
@@ -537,26 +547,26 @@ system.ruby.network.routers1.throttle1.msg_bytes.Control::0 4376
system.ruby.network.routers1.throttle1.msg_bytes.Request_Control::2 3448
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 48600
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 4480
-system.ruby.network.routers2.throttle0.link_utilization 2.088208
+system.ruby.network.routers2.throttle0.link_utilization 1.962638
system.ruby.network.routers2.throttle0.msg_count.Control::0 547
system.ruby.network.routers2.throttle0.msg_count.Response_Data::1 103
system.ruby.network.routers2.throttle0.msg_count.Response_Control::1 436
system.ruby.network.routers2.throttle0.msg_bytes.Control::0 4376
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::1 7416
system.ruby.network.routers2.throttle0.msg_bytes.Response_Control::1 3488
-system.ruby.network.routers2.throttle1.link_utilization 5.971618
+system.ruby.network.routers2.throttle1.link_utilization 5.612528
system.ruby.network.routers2.throttle1.msg_count.Response_Data::1 547
system.ruby.network.routers2.throttle1.msg_count.Response_Control::1 539
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::1 39384
system.ruby.network.routers2.throttle1.msg_bytes.Response_Control::1 4312
-system.ruby.network.routers3.throttle0.link_utilization 6.235104
+system.ruby.network.routers3.throttle0.link_utilization 5.860170
system.ruby.network.routers3.throttle0.msg_count.Request_Control::2 431
system.ruby.network.routers3.throttle0.msg_count.Response_Data::1 572
system.ruby.network.routers3.throttle0.msg_count.Response_Control::1 124
system.ruby.network.routers3.throttle0.msg_bytes.Request_Control::2 3448
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::1 41184
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::1 992
-system.ruby.network.routers3.throttle1.link_utilization 8.437015
+system.ruby.network.routers3.throttle1.link_utilization 7.929674
system.ruby.network.routers3.throttle1.msg_count.Control::0 572
system.ruby.network.routers3.throttle1.msg_count.Response_Data::1 547
system.ruby.network.routers3.throttle1.msg_count.Response_Control::1 908
@@ -571,7 +581,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::2 217
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::0 3240
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::1 4464
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 632
-system.ruby.network.routers3.throttle2.link_utilization 2.088208
+system.ruby.network.routers3.throttle2.link_utilization 1.962638
system.ruby.network.routers3.throttle2.msg_count.Control::0 547
system.ruby.network.routers3.throttle2.msg_count.Response_Data::1 103
system.ruby.network.routers3.throttle2.msg_count.Response_Control::1 436
@@ -597,13 +607,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
system.ruby.delayVCHist.vnet_2::samples 431 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 431 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 431 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::bucket_size 64
+system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 415
-system.ruby.LD.latency_hist_seqr::mean 31.356627
-system.ruby.LD.latency_hist_seqr::gmean 7.342788
-system.ruby.LD.latency_hist_seqr::stdev 35.995277
-system.ruby.LD.latency_hist_seqr | 223 53.73% 53.73% | 75 18.07% 71.81% | 106 25.54% 97.35% | 10 2.41% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 33.824096
+system.ruby.LD.latency_hist_seqr::gmean 7.531942
+system.ruby.LD.latency_hist_seqr::stdev 41.807535
+system.ruby.LD.latency_hist_seqr | 298 71.81% 71.81% | 115 27.71% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 415
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
@@ -612,21 +622,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 211 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 211
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 204
-system.ruby.LD.miss_latency_hist_seqr::mean 62.754902
-system.ruby.LD.miss_latency_hist_seqr::gmean 57.734169
-system.ruby.LD.miss_latency_hist_seqr::stdev 26.340677
-system.ruby.LD.miss_latency_hist_seqr | 12 5.88% 5.88% | 75 36.76% 42.65% | 106 51.96% 94.61% | 10 4.90% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 0 0.00% 99.51% | 1 0.49% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 67.774510
+system.ruby.LD.miss_latency_hist_seqr::gmean 60.800044
+system.ruby.LD.miss_latency_hist_seqr::stdev 35.866860
+system.ruby.LD.miss_latency_hist_seqr | 87 42.65% 42.65% | 115 56.37% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 0 0.00% 99.02% | 2 0.98% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 204
-system.ruby.ST.latency_hist_seqr::bucket_size 64
-system.ruby.ST.latency_hist_seqr::max_bucket 639
+system.ruby.ST.latency_hist_seqr::bucket_size 16
+system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 294
-system.ruby.ST.latency_hist_seqr::mean 14.789116
-system.ruby.ST.latency_hist_seqr::gmean 2.517478
-system.ruby.ST.latency_hist_seqr::stdev 31.573573
-system.ruby.ST.latency_hist_seqr | 264 89.80% 89.80% | 29 9.86% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 14.469388
+system.ruby.ST.latency_hist_seqr::gmean 2.523301
+system.ruby.ST.latency_hist_seqr::stdev 26.779037
+system.ruby.ST.latency_hist_seqr | 226 76.87% 76.87% | 4 1.36% 78.23% | 33 11.22% 89.46% | 1 0.34% 89.80% | 14 4.76% 94.56% | 14 4.76% 99.32% | 2 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 294
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@@ -635,21 +645,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 226 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 226
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
+system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
system.ruby.ST.miss_latency_hist_seqr::samples 68
-system.ruby.ST.miss_latency_hist_seqr::mean 60.617647
-system.ruby.ST.miss_latency_hist_seqr::gmean 54.148546
-system.ruby.ST.miss_latency_hist_seqr::stdev 39.831747
-system.ruby.ST.miss_latency_hist_seqr | 38 55.88% 55.88% | 29 42.65% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 0 0.00% 98.53% | 1 1.47% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 59.235294
+system.ruby.ST.miss_latency_hist_seqr::gmean 54.692111
+system.ruby.ST.miss_latency_hist_seqr::stdev 22.140068
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 4 5.88% 5.88% | 33 48.53% 54.41% | 1 1.47% 55.88% | 14 20.59% 76.47% | 14 20.59% 97.06% | 2 2.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 68
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 2585
-system.ruby.IFETCH.latency_hist_seqr::mean 9.701354
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.644214
-system.ruby.IFETCH.latency_hist_seqr::stdev 25.994801
-system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 287 11.10% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 3 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 10.473501
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.659469
+system.ruby.IFETCH.latency_hist_seqr::stdev 28.438724
+system.ruby.IFETCH.latency_hist_seqr | 2294 88.74% 88.74% | 286 11.06% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 2585
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
@@ -661,10 +671,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2285
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 300
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 75.976667
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 72.583942
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.223784
-system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 287 95.67% 98.67% | 1 0.33% 99.00% | 0 0.00% 99.00% | 0 0.00% 99.00% | 3 1.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 82.630000
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 78.596235
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 32.857141
+system.ruby.IFETCH.miss_latency_hist_seqr | 9 3.00% 3.00% | 286 95.33% 98.33% | 1 0.33% 98.67% | 0 0.00% 98.67% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 300
system.ruby.Directory_Controller.Fetch 547 0.00% 0.00%
system.ruby.Directory_Controller.Data 103 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 2ad2eb8ea..70212c16a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,11 +270,16 @@ children=directory forwardFromDir requestToDir responseFromDir responseFromMemor
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=6
eventq_index=0
forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestToDir=system.ruby.dir_cntrl0.requestToDir
responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -320,10 +346,15 @@ L1Icache=system.ruby.l1_cntrl0.L1Icache
buffer_size=0
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
l2_select_num_bits=0
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
requestToL1Cache=system.ruby.l1_cntrl0.requestToL1Cache
@@ -433,17 +464,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -466,8 +502,13 @@ L2cache=system.ruby.l2_cntrl0.L2cache
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
request_latency=2
responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
@@ -566,18 +607,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
ruby_system=system.ruby
topology=Crossbar
@@ -740,42 +786,216 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers18]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers19]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11
+power_model=Null
router_id=0
virt_nets=3
@@ -867,8 +1087,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11
+power_model=Null
router_id=1
virt_nets=3
@@ -960,8 +1186,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11
+power_model=Null
router_id=2
virt_nets=3
@@ -1053,8 +1285,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17
+power_model=Null
router_id=3
virt_nets=3
@@ -1187,9 +1425,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 28c1f1cb8..42fdb4cc6 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:06:59
-gem5 started Jan 21 2016 14:07:35
-gem5 executing on zizzer, pid 50069
-command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+gem5 compiled Oct 13 2016 20:30:58
+gem5 started Oct 13 2016 20:31:25
+gem5 executing on e108600-lin, pid 17791
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 41712 because target called exit()
+Exiting @ tick 44230 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 1d68008a1..9bed4b569 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000042 # Number of seconds simulated
-sim_ticks 41712 # Number of ticks simulated
-final_tick 41712 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000044 # Number of seconds simulated
+sim_ticks 44230 # Number of ticks simulated
+final_tick 44230 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 62826 # Simulator instruction rate (inst/s)
-host_op_rate 62813 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1016484 # Simulator tick rate (ticks/s)
-host_mem_usage 457644 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 44627 # Simulator instruction rate (inst/s)
+host_op_rate 44610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 765394 # Simulator tick rate (ticks/s)
+host_mem_usage 414624 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 29696 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 29696 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 4992 # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 464 #
system.mem_ctrls.num_reads::total 464 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 78 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 78 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 711929421 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 711929421 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 119677791 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 119677791 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 831607211 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 831607211 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 671399503 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 671399503 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 112864572 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 112864572 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 784264074 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 784264074 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 464 # Number of read requests accepted
system.mem_ctrls.writeReqs 78 # Number of write requests accepted
system.mem_ctrls.readBursts 464 # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 41632 # Total gap between requests
+system.mem_ctrls.totGap 44144 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 336 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 226.772547 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 284.954160 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 17 23.61% 23.61% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 17 23.61% 47.22% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 12 16.67% 63.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 7 9.72% 80.56% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 6 8.33% 88.89% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2 2.78% 91.67% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 3 4.17% 95.83% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 3 4.17% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 75 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 308.906667 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 203.362375 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 281.413861 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 21 28.00% 28.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 20 26.67% 54.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 8 10.67% 65.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 8 10.67% 76.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 6 8.00% 84.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 3 4.00% 88.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 4 5.33% 93.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 1 1.33% 94.67% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 4 5.33% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 75 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 248 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 248.000000 # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 2393 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 9689 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat 4911 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 12207 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 1920 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.23 # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat 12.79 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.23 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 589.18 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 24.55 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 711.93 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 119.68 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.79 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 555.64 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 23.15 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 671.40 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 112.86 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 4.79 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.60 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 4.52 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.34 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.18 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 21.63 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 305 # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen 21.61 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 79.43 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 78.65 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 76.81 # Average gap between requests
-system.mem_ctrls.pageHitRate 74.42 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 1809600 # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap 81.45 # Average gap between requests
+system.mem_ctrls.pageHitRate 73.72 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 1793568 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 24398280 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 2114400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 31112040 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 793.795989 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 3488 # Time in different power states
+system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 2736456 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 72192 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 16199400 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 966144 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 25100604 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 567.501786 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 37998 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 48 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 34510 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 214200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 2708160 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 26293644 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 449400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 32759652 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 835.918653 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 623 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 2516 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 4841 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 35525 # Time in different power states
+system.mem_ctrls_1.actEnergy 414120 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 208656 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 2593248 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 3830856 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 258048 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 15964560 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 56448 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 26532768 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 599.881709 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 34371 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 532 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 37281 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 147 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 7241 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 35010 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 41712 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 41712 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 44230 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 44230 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 41712 # Number of busy cycles
+system.cpu.num_busy_cycles 44230 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 396 # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 3295
@@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 3295
-system.ruby.latency_hist_seqr::bucket_size 32
-system.ruby.latency_hist_seqr::max_bucket 319
+system.ruby.latency_hist_seqr::bucket_size 64
+system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 3294
-system.ruby.latency_hist_seqr::mean 11.663024
-system.ruby.latency_hist_seqr::gmean 1.954156
-system.ruby.latency_hist_seqr::stdev 27.142816
-system.ruby.latency_hist_seqr | 2830 85.91% 85.91% | 80 2.43% 88.34% | 359 10.90% 99.24% | 18 0.55% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 1 0.03% 99.91% | 3 0.09% 100.00%
+system.ruby.latency_hist_seqr::mean 12.427444
+system.ruby.latency_hist_seqr::gmean 1.971908
+system.ruby.latency_hist_seqr::stdev 29.452789
+system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 377 11.45% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 3294
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
@@ -379,30 +389,30 @@ system.ruby.hit_latency_hist_seqr::mean 1
system.ruby.hit_latency_hist_seqr::gmean 1
system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 2750
-system.ruby.miss_latency_hist_seqr::bucket_size 32
-system.ruby.miss_latency_hist_seqr::max_bucket 319
+system.ruby.miss_latency_hist_seqr::bucket_size 64
+system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 544
-system.ruby.miss_latency_hist_seqr::mean 65.566176
-system.ruby.miss_latency_hist_seqr::gmean 57.783054
-system.ruby.miss_latency_hist_seqr::stdev 31.323348
-system.ruby.miss_latency_hist_seqr | 80 14.71% 14.71% | 80 14.71% 29.41% | 359 65.99% 95.40% | 18 3.31% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 1 0.18% 99.26% | 0 0.00% 99.26% | 1 0.18% 99.45% | 3 0.55% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 70.194853
+system.ruby.miss_latency_hist_seqr::gmean 61.035379
+system.ruby.miss_latency_hist_seqr::stdev 35.442152
+system.ruby.miss_latency_hist_seqr | 160 29.41% 29.41% | 377 69.30% 98.71% | 2 0.37% 99.08% | 0 0.00% 99.08% | 3 0.55% 99.63% | 2 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 544
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 435 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 274 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 80 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 464 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 544 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 6.800201
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 6.413068
system.ruby.network.routers0.msg_count.Request_Control::0 544
system.ruby.network.routers0.msg_count.Response_Data::2 464
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::2 80
@@ -415,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::2 5760
system.ruby.network.routers0.msg_bytes.Writeback_Data::2 34704
system.ruby.network.routers0.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers0.msg_bytes.Unblock_Control::2 4512
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 10.372914
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 9.782388
system.ruby.network.routers1.msg_count.Request_Control::0 544
system.ruby.network.routers1.msg_count.Request_Control::1 464
system.ruby.network.routers1.msg_count.Response_Data::2 928
@@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Data::2 40320
system.ruby.network.routers1.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers1.msg_bytes.Writeback_Control::1 1248
system.ruby.network.routers1.msg_bytes.Unblock_Control::2 8216
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 3.572713
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 3.369319
system.ruby.network.routers2.msg_count.Request_Control::1 464
system.ruby.network.routers2.msg_count.Response_Data::2 464
system.ruby.network.routers2.msg_count.Writeback_Data::2 78
@@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::2 33408
system.ruby.network.routers2.msg_bytes.Writeback_Data::2 5616
system.ruby.network.routers2.msg_bytes.Writeback_Control::1 1248
system.ruby.network.routers2.msg_bytes.Unblock_Control::2 3704
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 6.915276
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized 6.521592
system.ruby.network.routers3.msg_count.Request_Control::0 544
system.ruby.network.routers3.msg_count.Request_Control::1 464
system.ruby.network.routers3.msg_count.Response_Data::2 928
@@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Writeback_Data::2 40320
system.ruby.network.routers3.msg_bytes.Writeback_Control::0 8032
system.ruby.network.routers3.msg_bytes.Writeback_Control::1 1248
system.ruby.network.routers3.msg_bytes.Unblock_Control::2 8216
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 3024
system.ruby.network.msg_count.Response_Data 2784
system.ruby.network.msg_count.ResponseL2hit_Data 240
@@ -476,15 +486,15 @@ system.ruby.network.msg_byte.ResponseL2hit_Data 17280
system.ruby.network.msg_byte.Writeback_Data 120960
system.ruby.network.msg_byte.Writeback_Control 27840
system.ruby.network.msg_byte.Unblock_Control 24648
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41712 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 6.470560
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 44230 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 6.102193
system.ruby.network.routers0.throttle0.msg_count.Response_Data::2 464
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2 80
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::0 502
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::2 33408
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::2 5760
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::0 4016
-system.ruby.network.routers0.throttle1.link_utilization 7.129843
+system.ruby.network.routers0.throttle1.link_utilization 6.723943
system.ruby.network.routers0.throttle1.msg_count.Request_Control::0 544
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::2 482
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 502
@@ -493,7 +503,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::0 4352
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::2 34704
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::0 4016
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::2 4512
-system.ruby.network.routers1.throttle0.link_utilization 12.229095
+system.ruby.network.routers1.throttle0.link_utilization 11.532896
system.ruby.network.routers1.throttle0.msg_count.Request_Control::0 544
system.ruby.network.routers1.throttle0.msg_count.Response_Data::2 464
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::2 482
@@ -506,7 +516,7 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::2 34704
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::0 4016
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::1 624
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::2 4512
-system.ruby.network.routers1.throttle1.link_utilization 8.516734
+system.ruby.network.routers1.throttle1.link_utilization 8.031879
system.ruby.network.routers1.throttle1.msg_count.Request_Control::1 464
system.ruby.network.routers1.throttle1.msg_count.Response_Data::2 464
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::2 80
@@ -521,7 +531,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::2 5616
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 4016
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::1 624
system.ruby.network.routers1.throttle1.msg_bytes.Unblock_Control::2 3704
-system.ruby.network.routers2.throttle0.link_utilization 2.046174
+system.ruby.network.routers2.throttle0.link_utilization 1.929686
system.ruby.network.routers2.throttle0.msg_count.Request_Control::1 464
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::2 78
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::1 78
@@ -530,19 +540,19 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::1 3712
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::2 5616
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::1 624
system.ruby.network.routers2.throttle0.msg_bytes.Unblock_Control::2 3704
-system.ruby.network.routers2.throttle1.link_utilization 5.099252
+system.ruby.network.routers2.throttle1.link_utilization 4.808953
system.ruby.network.routers2.throttle1.msg_count.Response_Data::2 464
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::1 78
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::2 33408
system.ruby.network.routers2.throttle1.msg_bytes.Writeback_Control::1 624
-system.ruby.network.routers3.throttle0.link_utilization 6.470560
+system.ruby.network.routers3.throttle0.link_utilization 6.102193
system.ruby.network.routers3.throttle0.msg_count.Response_Data::2 464
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::2 80
system.ruby.network.routers3.throttle0.msg_count.Writeback_Control::0 502
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::2 33408
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::2 5760
system.ruby.network.routers3.throttle0.msg_bytes.Writeback_Control::0 4016
-system.ruby.network.routers3.throttle1.link_utilization 12.229095
+system.ruby.network.routers3.throttle1.link_utilization 11.532896
system.ruby.network.routers3.throttle1.msg_count.Request_Control::0 544
system.ruby.network.routers3.throttle1.msg_count.Response_Data::2 464
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::2 482
@@ -555,7 +565,7 @@ system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::2 34704
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::0 4016
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 624
system.ruby.network.routers3.throttle1.msg_bytes.Unblock_Control::2 4512
-system.ruby.network.routers3.throttle2.link_utilization 2.046174
+system.ruby.network.routers3.throttle2.link_utilization 1.929686
system.ruby.network.routers3.throttle2.msg_count.Request_Control::1 464
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::2 78
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::1 78
@@ -564,13 +574,13 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::1 3712
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::2 5616
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::1 624
system.ruby.network.routers3.throttle2.msg_bytes.Unblock_Control::2 3704
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::bucket_size 64
+system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 415
-system.ruby.LD.latency_hist_seqr::mean 25.657831
-system.ruby.LD.latency_hist_seqr::gmean 5.487426
-system.ruby.LD.latency_hist_seqr::stdev 34.035908
-system.ruby.LD.latency_hist_seqr | 275 66.27% 66.27% | 45 10.84% 77.11% | 85 20.48% 97.59% | 8 1.93% 99.52% | 1 0.24% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 27.790361
+system.ruby.LD.latency_hist_seqr::gmean 5.600782
+system.ruby.LD.latency_hist_seqr::stdev 40.269706
+system.ruby.LD.latency_hist_seqr | 320 77.11% 77.11% | 92 22.17% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 1 0.24% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 415
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
@@ -579,21 +589,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 233 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 233
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 182
-system.ruby.LD.miss_latency_hist_seqr::mean 57.225275
-system.ruby.LD.miss_latency_hist_seqr::gmean 48.520263
-system.ruby.LD.miss_latency_hist_seqr::stdev 29.410954
-system.ruby.LD.miss_latency_hist_seqr | 42 23.08% 23.08% | 45 24.73% 47.80% | 85 46.70% 94.51% | 8 4.40% 98.90% | 1 0.55% 99.45% | 0 0.00% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 62.087912
+system.ruby.LD.miss_latency_hist_seqr::gmean 50.836003
+system.ruby.LD.miss_latency_hist_seqr::stdev 40.030554
+system.ruby.LD.miss_latency_hist_seqr | 87 47.80% 47.80% | 92 50.55% 98.35% | 1 0.55% 98.90% | 0 0.00% 98.90% | 1 0.55% 99.45% | 1 0.55% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 182
system.ruby.ST.latency_hist_seqr::bucket_size 16
system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 294
-system.ruby.ST.latency_hist_seqr::mean 18.809524
-system.ruby.ST.latency_hist_seqr::gmean 3.456048
-system.ruby.ST.latency_hist_seqr::stdev 29.072895
-system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 38 12.93% 97.62% | 6 2.04% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 19.755102
+system.ruby.ST.latency_hist_seqr::gmean 3.497030
+system.ruby.ST.latency_hist_seqr::stdev 31.010753
+system.ruby.ST.latency_hist_seqr | 202 68.71% 68.71% | 12 4.08% 72.79% | 34 11.56% 84.35% | 1 0.34% 84.69% | 0 0.00% 84.69% | 44 14.97% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 294
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@@ -605,18 +615,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 202
system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
system.ruby.ST.miss_latency_hist_seqr::samples 92
-system.ruby.ST.miss_latency_hist_seqr::mean 57.913043
-system.ruby.ST.miss_latency_hist_seqr::gmean 52.615480
-system.ruby.ST.miss_latency_hist_seqr::stdev 21.714254
-system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 38 41.30% 92.39% | 6 6.52% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 60.934783
+system.ruby.ST.miss_latency_hist_seqr::gmean 54.635401
+system.ruby.ST.miss_latency_hist_seqr::stdev 24.518127
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 12 13.04% 13.04% | 34 36.96% 50.00% | 1 1.09% 51.09% | 0 0.00% 51.09% | 44 47.83% 98.91% | 1 1.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 92
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
+system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
+system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 2585
-system.ruby.IFETCH.latency_hist_seqr::mean 8.603482
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.551701
-system.ruby.IFETCH.latency_hist_seqr::stdev 24.714457
-system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 0 0.00% 90.56% | 230 8.90% 99.46% | 9 0.35% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 1 0.04% 99.88% | 3 0.12% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 9.127660
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.562445
+system.ruby.IFETCH.latency_hist_seqr::stdev 26.109704
+system.ruby.IFETCH.latency_hist_seqr | 2341 90.56% 90.56% | 240 9.28% 99.85% | 1 0.04% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 2585
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
@@ -625,13 +635,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::mean 1
system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1
system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 2315 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 2315
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 270
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 73.796296
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.113694
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.225253
-system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 0 0.00% 9.63% | 230 85.19% 94.81% | 9 3.33% 98.15% | 1 0.37% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 0 0.00% 98.52% | 1 0.37% 98.89% | 3 1.11% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.814815
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 71.697206
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 33.251813
+system.ruby.IFETCH.miss_latency_hist_seqr | 26 9.63% 9.63% | 240 88.89% 98.52% | 1 0.37% 98.89% | 0 0.00% 98.89% | 2 0.74% 99.63% | 1 0.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 270
system.ruby.Directory_Controller.GETX 80 0.00% 0.00%
system.ruby.Directory_Controller.GETS 384 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index c78531ccf..cf25b799b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir persistentFromDir persiste
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=5
distributed_persistent=true
@@ -258,8 +280,12 @@ eventq_index=0
fixed_timeout_latency=100
l2_select_num_bits=0
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
persistentFromDir=system.ruby.dir_cntrl0.persistentFromDir
persistentToDir=system.ruby.dir_cntrl0.persistentToDir
+power_model=Null
recycle_latency=10
reissue_wakeup_latency=10
requestFromDir=system.ruby.dir_cntrl0.requestFromDir
@@ -361,6 +387,7 @@ N_tokens=2
buffer_size=0
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
dynamic_timeout_enabled=true
eventq_index=0
fixed_timeout_latency=300
@@ -370,8 +397,12 @@ l2_select_num_bits=0
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
no_mig_atomic=true
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
persistentFromL1Cache=system.ruby.l1_cntrl0.persistentFromL1Cache
persistentToL1Cache=system.ruby.l1_cntrl0.persistentToL1Cache
+power_model=Null
recycle_latency=10
reissue_wakeup_latency=10
requestFromL1Cache=system.ruby.l1_cntrl0.requestFromL1Cache
@@ -497,17 +528,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -524,12 +560,17 @@ N_tokens=2
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
filtering_enabled=true
l2_request_latency=5
l2_response_latency=5
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
persistentToL2Cache=system.ruby.l2_cntrl0.persistentToL2Cache
+power_model=Null
recycle_latency=10
responseFromL2Cache=system.ruby.l2_cntrl0.responseFromL2Cache
responseToL2Cache=system.ruby.l2_cntrl0.responseToL2Cache
@@ -626,18 +667,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3
+children=ext_links0 ext_links1 ext_links2 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_link_buffers48 int_link_buffers49 int_link_buffers50 int_link_buffers51 int_link_buffers52 int_link_buffers53 int_link_buffers54 int_link_buffers55 int_link_buffers56 int_link_buffers57 int_link_buffers58 int_link_buffers59 int_link_buffers60 int_link_buffers61 int_link_buffers62 int_link_buffers63 int_link_buffers64 int_link_buffers65 int_link_buffers66 int_link_buffers67 int_link_buffers68 int_link_buffers69 int_link_buffers70 int_link_buffers71 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 routers0 routers1 routers2 routers3
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47 system.ruby.network.int_link_buffers48 system.ruby.network.int_link_buffers49 system.ruby.network.int_link_buffers50 system.ruby.network.int_link_buffers51 system.ruby.network.int_link_buffers52 system.ruby.network.int_link_buffers53 system.ruby.network.int_link_buffers54 system.ruby.network.int_link_buffers55 system.ruby.network.int_link_buffers56 system.ruby.network.int_link_buffers57 system.ruby.network.int_link_buffers58 system.ruby.network.int_link_buffers59 system.ruby.network.int_link_buffers60 system.ruby.network.int_link_buffers61 system.ruby.network.int_link_buffers62 system.ruby.network.int_link_buffers63 system.ruby.network.int_link_buffers64 system.ruby.network.int_link_buffers65 system.ruby.network.int_link_buffers66 system.ruby.network.int_link_buffers67 system.ruby.network.int_link_buffers68 system.ruby.network.int_link_buffers69 system.ruby.network.int_link_buffers70 system.ruby.network.int_link_buffers71
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3 system.ruby.network.int_links4 system.ruby.network.int_links5
netifs=
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2 system.ruby.network.routers3
ruby_system=system.ruby
topology=Crossbar
@@ -926,42 +972,342 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers48]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers49]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers50]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers51]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers52]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers53]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers54]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers55]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers56]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers57]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers58]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers59]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers60]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers61]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers62]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers63]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers64]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers65]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers66]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers67]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers68]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers69]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers70]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers71]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=4
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers1
+src_outport=
weight=1
[system.ruby.network.int_links2]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers3
eventq_index=0
latency=1
link_id=5
-node_a=system.ruby.network.routers2
-node_b=system.ruby.network.routers3
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=6
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=7
+src_node=system.ruby.network.routers3
+src_outport=
+weight=1
+
+[system.ruby.network.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
+eventq_index=0
+latency=1
+link_id=8
+src_node=system.ruby.network.routers3
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17 system.ruby.network.routers0.port_buffers18 system.ruby.network.routers0.port_buffers19 system.ruby.network.routers0.port_buffers20 system.ruby.network.routers0.port_buffers21 system.ruby.network.routers0.port_buffers22 system.ruby.network.routers0.port_buffers23
+power_model=Null
router_id=0
virt_nets=6
@@ -1137,8 +1483,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17 system.ruby.network.routers1.port_buffers18 system.ruby.network.routers1.port_buffers19 system.ruby.network.routers1.port_buffers20 system.ruby.network.routers1.port_buffers21 system.ruby.network.routers1.port_buffers22 system.ruby.network.routers1.port_buffers23
+power_model=Null
router_id=1
virt_nets=6
@@ -1314,8 +1666,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
router_id=2
virt_nets=6
@@ -1491,8 +1849,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers3.port_buffers00 system.ruby.network.routers3.port_buffers01 system.ruby.network.routers3.port_buffers02 system.ruby.network.routers3.port_buffers03 system.ruby.network.routers3.port_buffers04 system.ruby.network.routers3.port_buffers05 system.ruby.network.routers3.port_buffers06 system.ruby.network.routers3.port_buffers07 system.ruby.network.routers3.port_buffers08 system.ruby.network.routers3.port_buffers09 system.ruby.network.routers3.port_buffers10 system.ruby.network.routers3.port_buffers11 system.ruby.network.routers3.port_buffers12 system.ruby.network.routers3.port_buffers13 system.ruby.network.routers3.port_buffers14 system.ruby.network.routers3.port_buffers15 system.ruby.network.routers3.port_buffers16 system.ruby.network.routers3.port_buffers17 system.ruby.network.routers3.port_buffers18 system.ruby.network.routers3.port_buffers19 system.ruby.network.routers3.port_buffers20 system.ruby.network.routers3.port_buffers21 system.ruby.network.routers3.port_buffers22 system.ruby.network.routers3.port_buffers23 system.ruby.network.routers3.port_buffers24 system.ruby.network.routers3.port_buffers25 system.ruby.network.routers3.port_buffers26 system.ruby.network.routers3.port_buffers27 system.ruby.network.routers3.port_buffers28 system.ruby.network.routers3.port_buffers29 system.ruby.network.routers3.port_buffers30 system.ruby.network.routers3.port_buffers31 system.ruby.network.routers3.port_buffers32 system.ruby.network.routers3.port_buffers33 system.ruby.network.routers3.port_buffers34 system.ruby.network.routers3.port_buffers35
+power_model=Null
router_id=3
virt_nets=6
@@ -1751,9 +2115,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index 9a1a80ba2..57e88573f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 14:12:23
-gem5 started Jan 21 2016 14:13:00
-gem5 executing on zizzer, pid 55410
-command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+gem5 compiled Oct 13 2016 20:33:48
+gem5 started Oct 13 2016 20:34:16
+gem5 executing on e108600-lin, pid 27527
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 40527 because target called exit()
+Exiting @ tick 42756 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 20325d4b9..0254766b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000041 # Number of seconds simulated
-sim_ticks 40527 # Number of ticks simulated
-final_tick 40527 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000043 # Number of seconds simulated
+sim_ticks 42756 # Number of ticks simulated
+final_tick 42756 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 89328 # Simulator instruction rate (inst/s)
-host_op_rate 89293 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1403832 # Simulator tick rate (ticks/s)
-host_mem_usage 454496 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 50628 # Simulator instruction rate (inst/s)
+host_op_rate 50604 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 839232 # Simulator tick rate (ticks/s)
+host_mem_usage 411504 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28672 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 28672 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5376 # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 448 #
system.mem_ctrls.num_reads::total 448 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 84 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 84 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 707478965 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 707478965 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 132652306 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 132652306 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 840131271 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 840131271 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 670595940 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 670595940 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 125736739 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 125736739 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 796332678 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 796332678 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 448 # Number of read requests accepted
system.mem_ctrls.writeReqs 84 # Number of write requests accepted
system.mem_ctrls.readBursts 448 # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 40452 # Total gap between requests
+system.mem_ctrls.totGap 42675 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -185,20 +185,20 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 73 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 334.027397 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 221.884458 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 291.386817 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 19 26.03% 26.03% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 15 20.55% 46.58% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 13 17.81% 64.38% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 6 8.22% 72.60% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 7 9.59% 82.19% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 5 6.85% 89.04% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 1 1.37% 90.41% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 2 2.74% 93.15% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 73 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::samples 72 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 326.222222 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 214.888456 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 283.209683 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 20 27.78% 27.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 16 22.22% 50.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 10 13.89% 63.89% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 5 6.94% 70.83% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 9 12.50% 83.33% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 2 2.78% 86.11% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 6 8.33% 94.44% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 2 2.78% 97.22% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 2 2.78% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 72 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean 245 # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean 245.000000 # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 2601 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 9726 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat 4832 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 11957 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.94 # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat 12.89 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.94 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 592.20 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 25.27 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 707.48 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 132.65 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.89 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 561.32 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 23.95 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 670.60 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 125.74 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 4.82 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.63 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.20 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 4.57 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.39 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.19 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 21.86 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 297 # Number of row buffer hits during reads
+system.mem_ctrls.avgWrQLen 21.84 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 296 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 79.20 # Row buffer hit rate for reads
+system.mem_ctrls.readRowHitRate 78.93 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 76.04 # Average gap between requests
-system.mem_ctrls.pageHitRate 74.11 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 158760 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 88200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 1896960 # Energy for read commands per rank (pJ)
+system.mem_ctrls.avgGap 80.22 # Average gap between requests
+system.mem_ctrls.pageHitRate 73.87 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 178500 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 81144 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 1816416 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 25074756 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 1518600 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 31280076 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 798.164736 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 2492 # Time in different power states
+system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 2612424 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 73344 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 15837336 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 808320 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 24480684 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 572.567219 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 36801 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 51 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 35499 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 393120 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 218400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 2658240 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 26158212 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 568200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 32704860 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 834.520541 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 821 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 2105 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 4569 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 34731 # Time in different power states
+system.mem_ctrls_1.actEnergy 392700 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 197064 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 2467584 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 3542208 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 293376 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 15524520 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 68736 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 25693020 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 600.921976 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 33391 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 512 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 37083 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 179 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 6720 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 34045 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 40527 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 40527 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 42756 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 42756 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 40527 # Number of busy cycles
+system.cpu.num_busy_cycles 42756 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 396 # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 3295
@@ -367,44 +377,44 @@ system.ruby.outstanding_req_hist_seqr::total 3295
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 3294
-system.ruby.latency_hist_seqr::mean 11.303279
-system.ruby.latency_hist_seqr::gmean 1.905847
-system.ruby.latency_hist_seqr::stdev 27.108694
-system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 0 0.00% 99.85% | 3 0.09% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 11.979964
+system.ruby.latency_hist_seqr::gmean 1.922311
+system.ruby.latency_hist_seqr::stdev 28.863148
+system.ruby.latency_hist_seqr | 2919 88.62% 88.62% | 368 11.17% 99.79% | 2 0.06% 99.85% | 1 0.03% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 3294
system.ruby.hit_latency_hist_seqr::bucket_size 4
system.ruby.hit_latency_hist_seqr::max_bucket 39
system.ruby.hit_latency_hist_seqr::samples 2846
-system.ruby.hit_latency_hist_seqr::mean 1.554814
-system.ruby.hit_latency_hist_seqr::gmean 1.080771
-system.ruby.hit_latency_hist_seqr::stdev 3.499483
-system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 9 0.32% 97.86% | 61 2.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.hit_latency_hist_seqr::mean 1.555868
+system.ruby.hit_latency_hist_seqr::gmean 1.080822
+system.ruby.hit_latency_hist_seqr::stdev 3.505788
+system.ruby.hit_latency_hist_seqr | 2776 97.54% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 0 0.00% 97.54% | 8 0.28% 97.82% | 62 2.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 2846
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 448
-system.ruby.miss_latency_hist_seqr::mean 73.232143
-system.ruby.miss_latency_hist_seqr::gmean 69.999992
-system.ruby.miss_latency_hist_seqr::stdev 29.782878
-system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 78.200893
+system.ruby.miss_latency_hist_seqr::gmean 74.547837
+system.ruby.miss_latency_hist_seqr::stdev 31.179064
+system.ruby.miss_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 448
system.ruby.Directory.incomplete_times_seqr 447
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 461 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 248 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
system.ruby.l1_cntrl0.L1Icache.demand_hits 2315 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Icache.demand_misses 270 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.ruby.l2_cntrl0.L2cache.demand_hits 64 # Number of cache demand hits
system.ruby.l2_cntrl0.L2cache.demand_misses 454 # Number of cache demand misses
system.ruby.l2_cntrl0.L2cache.demand_accesses 518 # Number of cache demand accesses
-system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.ruby.l2_cntrl0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 5.992918
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 5.680489
system.ruby.network.routers0.msg_count.Request_Control::1 518
system.ruby.network.routers0.msg_count.Response_Data::4 448
system.ruby.network.routers0.msg_count.ResponseL2hit_Data::4 70
@@ -417,8 +427,8 @@ system.ruby.network.routers0.msg_bytes.ResponseL2hit_Data::4 5040
system.ruby.network.routers0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.msg_bytes.Writeback_Data::4 36144
system.ruby.network.routers0.msg_bytes.Persistent_Control::3 128
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 4.472327
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 4.239171
system.ruby.network.routers1.msg_count.Request_Control::1 518
system.ruby.network.routers1.msg_count.Request_Control::2 454
system.ruby.network.routers1.msg_count.ResponseL2hit_Data::4 70
@@ -433,8 +443,8 @@ system.ruby.network.routers1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.msg_bytes.Writeback_Data::4 42192
system.ruby.network.routers1.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers1.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 3.463740
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 3.283165
system.ruby.network.routers2.msg_count.Request_Control::2 454
system.ruby.network.routers2.msg_count.Response_Data::4 448
system.ruby.network.routers2.msg_count.Writeback_Data::4 84
@@ -445,8 +455,8 @@ system.ruby.network.routers2.msg_bytes.Response_Data::4 32256
system.ruby.network.routers2.msg_bytes.Writeback_Data::4 6048
system.ruby.network.routers2.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers2.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers3.percent_links_utilized 4.642995
+system.ruby.network.routers3.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers3.percent_links_utilized 4.400942
system.ruby.network.routers3.msg_count.Request_Control::1 518
system.ruby.network.routers3.msg_count.Request_Control::2 454
system.ruby.network.routers3.msg_count.Response_Data::4 448
@@ -463,7 +473,7 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4 8
system.ruby.network.routers3.msg_bytes.Writeback_Data::4 42192
system.ruby.network.routers3.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers3.msg_bytes.Persistent_Control::3 128
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 2916
system.ruby.network.msg_count.Response_Data 1344
system.ruby.network.msg_count.ResponseL2hit_Data 210
@@ -478,8 +488,8 @@ system.ruby.network.msg_byte.Response_Control 24
system.ruby.network.msg_byte.Writeback_Data 126576
system.ruby.network.msg_byte.Writeback_Control 8760
system.ruby.network.msg_byte.Persistent_Control 384
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 40527 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 5.762825
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 42756 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 5.462391
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 448
system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4 70
system.ruby.network.routers0.throttle0.msg_count.Response_Control::4 1
@@ -488,21 +498,21 @@ system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 32256
system.ruby.network.routers0.throttle0.msg_bytes.ResponseL2hit_Data::4 5040
system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::4 8
system.ruby.network.routers0.throttle0.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers0.throttle1.link_utilization 6.223012
+system.ruby.network.routers0.throttle1.link_utilization 5.898587
system.ruby.network.routers0.throttle1.msg_count.Request_Control::1 518
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::4 502
system.ruby.network.routers0.throttle1.msg_count.Persistent_Control::3 8
system.ruby.network.routers0.throttle1.msg_bytes.Request_Control::1 4144
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::4 36144
system.ruby.network.routers0.throttle1.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers1.throttle0.link_utilization 6.223012
+system.ruby.network.routers1.throttle0.link_utilization 5.898587
system.ruby.network.routers1.throttle0.msg_count.Request_Control::1 518
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::4 502
system.ruby.network.routers1.throttle0.msg_count.Persistent_Control::3 8
system.ruby.network.routers1.throttle0.msg_bytes.Request_Control::1 4144
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::4 36144
system.ruby.network.routers1.throttle0.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers1.throttle1.link_utilization 2.721642
+system.ruby.network.routers1.throttle1.link_utilization 2.579755
system.ruby.network.routers1.throttle1.msg_count.Request_Control::2 454
system.ruby.network.routers1.throttle1.msg_count.ResponseL2hit_Data::4 70
system.ruby.network.routers1.throttle1.msg_count.Response_Control::4 1
@@ -513,7 +523,7 @@ system.ruby.network.routers1.throttle1.msg_bytes.ResponseL2hit_Data::4 5
system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::4 8
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::4 6048
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::4 2920
-system.ruby.network.routers2.throttle0.link_utilization 1.953019
+system.ruby.network.routers2.throttle0.link_utilization 1.851202
system.ruby.network.routers2.throttle0.msg_count.Request_Control::2 454
system.ruby.network.routers2.throttle0.msg_count.Writeback_Data::4 84
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::4 365
@@ -522,24 +532,24 @@ system.ruby.network.routers2.throttle0.msg_bytes.Request_Control::2 3632
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Data::4 6048
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers2.throttle0.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers2.throttle1.link_utilization 4.974461
+system.ruby.network.routers2.throttle1.link_utilization 4.715128
system.ruby.network.routers2.throttle1.msg_count.Response_Data::4 448
system.ruby.network.routers2.throttle1.msg_bytes.Response_Data::4 32256
-system.ruby.network.routers3.throttle0.link_utilization 5.752955
+system.ruby.network.routers3.throttle0.link_utilization 5.453036
system.ruby.network.routers3.throttle0.msg_count.Response_Data::4 448
system.ruby.network.routers3.throttle0.msg_count.ResponseL2hit_Data::4 70
system.ruby.network.routers3.throttle0.msg_count.Response_Control::4 1
system.ruby.network.routers3.throttle0.msg_bytes.Response_Data::4 32256
system.ruby.network.routers3.throttle0.msg_bytes.ResponseL2hit_Data::4 5040
system.ruby.network.routers3.throttle0.msg_bytes.Response_Control::4 8
-system.ruby.network.routers3.throttle1.link_utilization 6.223012
+system.ruby.network.routers3.throttle1.link_utilization 5.898587
system.ruby.network.routers3.throttle1.msg_count.Request_Control::1 518
system.ruby.network.routers3.throttle1.msg_count.Writeback_Data::4 502
system.ruby.network.routers3.throttle1.msg_count.Persistent_Control::3 8
system.ruby.network.routers3.throttle1.msg_bytes.Request_Control::1 4144
system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Data::4 36144
system.ruby.network.routers3.throttle1.msg_bytes.Persistent_Control::3 64
-system.ruby.network.routers3.throttle2.link_utilization 1.953019
+system.ruby.network.routers3.throttle2.link_utilization 1.851202
system.ruby.network.routers3.throttle2.msg_count.Request_Control::2 454
system.ruby.network.routers3.throttle2.msg_count.Writeback_Data::4 84
system.ruby.network.routers3.throttle2.msg_count.Writeback_Control::4 365
@@ -548,36 +558,36 @@ system.ruby.network.routers3.throttle2.msg_bytes.Request_Control::2 3632
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Data::4 6048
system.ruby.network.routers3.throttle2.msg_bytes.Writeback_Control::4 2920
system.ruby.network.routers3.throttle2.msg_bytes.Persistent_Control::3 64
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::bucket_size 16
+system.ruby.LD.latency_hist_seqr::max_bucket 159
system.ruby.LD.latency_hist_seqr::samples 415
-system.ruby.LD.latency_hist_seqr::mean 27.009639
-system.ruby.LD.latency_hist_seqr::gmean 5.745092
-system.ruby.LD.latency_hist_seqr::stdev 35.695436
-system.ruby.LD.latency_hist_seqr | 266 64.10% 64.10% | 50 12.05% 76.14% | 86 20.72% 96.87% | 10 2.41% 99.28% | 2 0.48% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 0 0.00% 99.76% | 1 0.24% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 27.997590
+system.ruby.LD.latency_hist_seqr::gmean 5.837138
+system.ruby.LD.latency_hist_seqr::stdev 35.585408
+system.ruby.LD.latency_hist_seqr | 233 56.14% 56.14% | 33 7.95% 64.10% | 48 11.57% 75.66% | 2 0.48% 76.14% | 68 16.39% 92.53% | 18 4.34% 96.87% | 10 2.41% 99.28% | 1 0.24% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00%
system.ruby.LD.latency_hist_seqr::total 415
system.ruby.LD.hit_latency_hist_seqr::bucket_size 4
system.ruby.LD.hit_latency_hist_seqr::max_bucket 39
system.ruby.LD.hit_latency_hist_seqr::samples 266
-system.ruby.LD.hit_latency_hist_seqr::mean 3.834586
-system.ruby.LD.hit_latency_hist_seqr::gmean 1.482071
-system.ruby.LD.hit_latency_hist_seqr::stdev 7.549265
-system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 2 0.75% 88.35% | 31 11.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.hit_latency_hist_seqr::mean 3.845865
+system.ruby.LD.hit_latency_hist_seqr::gmean 1.482816
+system.ruby.LD.hit_latency_hist_seqr::stdev 7.577195
+system.ruby.LD.hit_latency_hist_seqr | 233 87.59% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 0 0.00% 87.59% | 1 0.38% 87.97% | 32 12.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 266
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 16
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 159
system.ruby.LD.miss_latency_hist_seqr::samples 149
-system.ruby.LD.miss_latency_hist_seqr::mean 68.382550
-system.ruby.LD.miss_latency_hist_seqr::gmean 64.532565
-system.ruby.LD.miss_latency_hist_seqr::stdev 27.813471
-system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 71.114094
+system.ruby.LD.miss_latency_hist_seqr::gmean 67.393219
+system.ruby.LD.miss_latency_hist_seqr::stdev 22.792700
+system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 149
system.ruby.ST.latency_hist_seqr::bucket_size 16
system.ruby.ST.latency_hist_seqr::max_bucket 159
system.ruby.ST.latency_hist_seqr::samples 294
-system.ruby.ST.latency_hist_seqr::mean 12.595238
-system.ruby.ST.latency_hist_seqr::gmean 2.381363
-system.ruby.ST.latency_hist_seqr::stdev 23.818056
+system.ruby.ST.latency_hist_seqr::mean 13.153061
+system.ruby.ST.latency_hist_seqr::gmean 2.398410
+system.ruby.ST.latency_hist_seqr::stdev 25.296880
system.ruby.ST.latency_hist_seqr | 228 77.55% 77.55% | 14 4.76% 82.31% | 20 6.80% 89.12% | 3 1.02% 90.14% | 23 7.82% 97.96% | 6 2.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 294
system.ruby.ST.hit_latency_hist_seqr::bucket_size 4
@@ -591,18 +601,18 @@ system.ruby.ST.hit_latency_hist_seqr::total 242
system.ruby.ST.miss_latency_hist_seqr::bucket_size 16
system.ruby.ST.miss_latency_hist_seqr::max_bucket 159
system.ruby.ST.miss_latency_hist_seqr::samples 52
-system.ruby.ST.miss_latency_hist_seqr::mean 60.865385
-system.ruby.ST.miss_latency_hist_seqr::gmean 58.719474
-system.ruby.ST.miss_latency_hist_seqr::stdev 16.012286
+system.ruby.ST.miss_latency_hist_seqr::mean 64.019231
+system.ruby.ST.miss_latency_hist_seqr::gmean 61.135942
+system.ruby.ST.miss_latency_hist_seqr::stdev 18.838311
system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 52
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 2585
-system.ruby.IFETCH.latency_hist_seqr::mean 8.634816
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.556513
-system.ruby.IFETCH.latency_hist_seqr::stdev 24.922226
-system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 243 9.40% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 9.275048
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.568384
+system.ruby.IFETCH.latency_hist_seqr::stdev 27.157574
+system.ruby.IFETCH.latency_hist_seqr | 2338 90.44% 90.44% | 242 9.36% 99.81% | 0 0.00% 99.81% | 1 0.04% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 2585
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 4
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 39
@@ -615,10 +625,10 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2338
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 247
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 78.761134
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 76.290474
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 31.873920
-system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 85.461538
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 82.604305
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.418255
+system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 247
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
@@ -630,18 +640,18 @@ system.ruby.L1Cache.hit_mach_latency_hist_seqr::total 2776
system.ruby.L2Cache.hit_mach_latency_hist_seqr::bucket_size 4
system.ruby.L2Cache.hit_mach_latency_hist_seqr::max_bucket 39
system.ruby.L2Cache.hit_mach_latency_hist_seqr::samples 70
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.557143
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.524270
-system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.199465
-system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9 12.86% 12.86% | 61 87.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 23.600000
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 23.569187
+system.ruby.L2Cache.hit_mach_latency_hist_seqr::stdev 1.159710
+system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8 11.43% 11.43% | 62 88.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 70
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 448
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 73.232143
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 69.999992
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 29.782878
-system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 0 0.00% 98.88% | 3 0.67% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 78.200893
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 74.547837
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 31.179064
+system.ruby.Directory.miss_mach_latency_hist_seqr | 73 16.29% 16.29% | 368 82.14% 98.44% | 2 0.45% 98.88% | 1 0.22% 99.11% | 0 0.00% 99.11% | 4 0.89% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 448
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
@@ -679,18 +689,18 @@ system.ruby.LD.L1Cache.hit_type_mach_latency_hist_seqr::total 233
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::bucket_size 4
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::max_bucket 39
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::samples 33
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.848485
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.840140
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.618527
-system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 6.06% 6.06% | 31 93.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::mean 23.939394
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::gmean 23.936802
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::stdev 0.348155
+system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 3.03% 3.03% | 32 96.97% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 33
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 149
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 68.382550
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 64.532565
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 27.813471
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 50 33.56% 33.56% | 86 57.72% 91.28% | 10 6.71% 97.99% | 2 1.34% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 0 0.00% 99.33% | 1 0.67% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 71.114094
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 67.393219
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.792700
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 48 32.21% 32.21% | 2 1.34% 33.56% | 68 45.64% 79.19% | 18 12.08% 91.28% | 10 6.71% 97.99% | 1 0.67% 98.66% | 0 0.00% 98.66% | 2 1.34% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 149
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -710,9 +720,9 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 14
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 52
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 60.865385
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 58.719474
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 16.012286
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 64.019231
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 61.135942
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.838311
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 20 38.46% 38.46% | 3 5.77% 44.23% | 23 44.23% 88.46% | 6 11.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 52
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
@@ -732,10 +742,10 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 23
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 247
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 78.761134
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 76.290474
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 31.873920
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 243 98.38% 98.38% | 0 0.00% 98.38% | 0 0.00% 98.38% | 2 0.81% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 85.461538
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 82.604305
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.418255
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 242 97.98% 97.98% | 0 0.00% 97.98% | 1 0.40% 98.38% | 0 0.00% 98.38% | 4 1.62% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 247
system.ruby.Directory_Controller.GETX 61 0.00% 0.00%
system.ruby.Directory_Controller.GETS 398 0.00% 0.00%
@@ -752,6 +762,7 @@ system.ruby.Directory_Controller.O.GETX 52 0.00% 0.00%
system.ruby.Directory_Controller.O.GETS 396 0.00% 0.00%
system.ruby.Directory_Controller.O.Ack_All_Tokens 15 0.00% 0.00%
system.ruby.Directory_Controller.NO.GETX 6 0.00% 0.00%
+system.ruby.Directory_Controller.NO.Lockdown 1 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_Owner 3 0.00% 0.00%
system.ruby.Directory_Controller.NO.Data_All_Tokens 81 0.00% 0.00%
system.ruby.Directory_Controller.NO.Ack_Owner 16 0.00% 0.00%
@@ -760,9 +771,9 @@ system.ruby.Directory_Controller.L.Unlockdown 4 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETX 3 0.00% 0.00%
system.ruby.Directory_Controller.O_W.GETS 2 0.00% 0.00%
system.ruby.Directory_Controller.O_W.Memory_Ack 84 0.00% 0.00%
-system.ruby.Directory_Controller.L_NO_W.Memory_Data 4 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Lockdown 4 0.00% 0.00%
-system.ruby.Directory_Controller.NO_W.Memory_Data 444 0.00% 0.00%
+system.ruby.Directory_Controller.L_NO_W.Memory_Data 3 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Lockdown 3 0.00% 0.00%
+system.ruby.Directory_Controller.NO_W.Memory_Data 445 0.00% 0.00%
system.ruby.L1Cache_Controller.Load 415 0.00% 0.00%
system.ruby.L1Cache_Controller.Ifetch 2585 0.00% 0.00%
system.ruby.L1Cache_Controller.Store 294 0.00% 0.00%
@@ -781,7 +792,7 @@ system.ruby.L1Cache_Controller.S.Ifetch 158 0.00% 0.00%
system.ruby.L1Cache_Controller.S.Store 8 0.00% 0.00%
system.ruby.L1Cache_Controller.S.L1_Replacement 48 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Load 66 0.00% 0.00%
-system.ruby.L1Cache_Controller.M.Ifetch 1099 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 1098 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Store 29 0.00% 0.00%
system.ruby.L1Cache_Controller.M.L1_Replacement 358 0.00% 0.00%
system.ruby.L1Cache_Controller.M.Own_Lock_or_Unlock 4 0.00% 0.00%
@@ -789,7 +800,7 @@ system.ruby.L1Cache_Controller.MM.Load 96 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.Store 103 0.00% 0.00%
system.ruby.L1Cache_Controller.MM.L1_Replacement 96 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Load 36 0.00% 0.00%
-system.ruby.L1Cache_Controller.M_W.Ifetch 1058 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch 1059 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Store 3 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.L1_Replacement 1 0.00% 0.00%
system.ruby.L1Cache_Controller.M_W.Use_TimeoutNoStarvers 392 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 18d7c2ab4..8207d6ac7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir probeFilter
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
@@ -257,6 +279,10 @@ forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
from_memory_controller_latency=2
full_bit_dir_enabled=false
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
probeFilter=system.ruby.dir_cntrl0.probeFilter
probe_filter_enabled=false
recycle_latency=10
@@ -384,6 +410,7 @@ buffer_size=0
cache_response_latency=10
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
forwardToCache=system.ruby.l1_cntrl0.forwardToCache
issue_latency=2
@@ -391,6 +418,10 @@ l2_cache_hit_latency=10
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
no_mig_atomic=true
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestFromCache=system.ruby.l1_cntrl0.requestFromCache
responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -522,17 +553,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.L1Dcache
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.L1Icache
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -560,18 +596,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_link_buffers40 int_link_buffers41 int_link_buffers42 int_link_buffers43 int_link_buffers44 int_link_buffers45 int_link_buffers46 int_link_buffers47 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 system.ruby.network.int_link_buffers40 system.ruby.network.int_link_buffers41 system.ruby.network.int_link_buffers42 system.ruby.network.int_link_buffers43 system.ruby.network.int_link_buffers44 system.ruby.network.int_link_buffers45 system.ruby.network.int_link_buffers46 system.ruby.network.int_link_buffers47
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
netifs=
number_of_virtual_networks=6
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
ruby_system=system.ruby
topology=Crossbar
@@ -766,32 +807,234 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers40]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers41]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers42]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers43]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers44]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers45]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers46]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers47]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14 system.ruby.network.routers0.port_buffers15 system.ruby.network.routers0.port_buffers16 system.ruby.network.routers0.port_buffers17
+power_model=Null
router_id=0
virt_nets=6
@@ -925,8 +1168,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14 system.ruby.network.routers1.port_buffers15 system.ruby.network.routers1.port_buffers16 system.ruby.network.routers1.port_buffers17
+power_model=Null
router_id=1
virt_nets=6
@@ -1060,8 +1309,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19 system.ruby.network.routers2.port_buffers20 system.ruby.network.routers2.port_buffers21 system.ruby.network.routers2.port_buffers22 system.ruby.network.routers2.port_buffers23
+power_model=Null
router_id=2
virt_nets=6
@@ -1236,9 +1491,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 2cf0cc885..35b481dda 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:56:08
-gem5 started Jan 21 2016 13:56:42
-gem5 executing on zizzer, pid 39363
-command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+gem5 compiled Oct 13 2016 20:24:36
+gem5 started Oct 13 2016 20:24:58
+gem5 executing on e108600-lin, pid 38874
+command line: /work/curdun01/gem5-external.hg/build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 32936 because target called exit()
+Exiting @ tick 35056 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index 71e93d920..4d9201d35 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000033 # Number of seconds simulated
-sim_ticks 32936 # Number of ticks simulated
-final_tick 32936 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000035 # Number of seconds simulated
+sim_ticks 35056 # Number of ticks simulated
+final_tick 35056 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 91605 # Simulator instruction rate (inst/s)
-host_op_rate 91573 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1170024 # Simulator tick rate (ticks/s)
-host_mem_usage 453424 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 50934 # Simulator instruction rate (inst/s)
+host_op_rate 50910 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 692254 # Simulator tick rate (ticks/s)
+host_mem_usage 411180 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 28224 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 28224 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 5184 # Number of bytes written to this memory
@@ -22,12 +22,12 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 441 #
system.mem_ctrls.num_reads::total 441 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 81 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 81 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 856934661 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 856934661 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 157396162 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 157396162 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1014330823 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1014330823 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 805111821 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 805111821 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 147877681 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 147877681 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 952989503 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 952989503 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 441 # Number of read requests accepted
system.mem_ctrls.writeReqs 81 # Number of write requests accepted
system.mem_ctrls.readBursts 441 # Number of DRAM read bursts, including those serviced by the write queue
@@ -74,7 +74,7 @@ system.mem_ctrls.perBankWrBursts::14 0 # Pe
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 32872 # Total gap between requests
+system.mem_ctrls.totGap 34986 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -186,17 +186,17 @@ system.mem_ctrls.wrQLenPdf::61 0 # Wh
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples 67 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 358.208955 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 229.774303 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 311.560906 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 18 26.87% 26.87% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 13 19.40% 46.27% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 8 11.94% 58.21% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 68.66% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 5 7.46% 76.12% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 6 8.96% 85.07% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 2 2.99% 88.06% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 4 5.97% 94.03% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 356.298507 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 230.035457 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 306.978482 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 19 28.36% 28.36% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 11 16.42% 44.78% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 10 14.93% 59.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 7 10.45% 70.15% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 6 8.96% 79.10% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 4 5.97% 85.07% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 3 4.48% 89.55% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 3 4.48% 94.03% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151 4 5.97% 100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total 67 # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples 1 # Reads before turning the bus around for writes
@@ -211,57 +211,67 @@ system.mem_ctrls.wrPerTurnAround::gmean 16.000000 # Wr
system.mem_ctrls.wrPerTurnAround::stdev nan # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::16 1 100.00% 100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total 1 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 2381 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 9506 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totQLat 4501 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 11626 # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.totBusLat 1875 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 6.35 # Average queueing delay per DRAM burst
+system.mem_ctrls.avgQLat 12.00 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 25.35 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 728.69 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 31.09 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 856.93 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 157.40 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 31.00 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 684.62 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 29.21 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 805.11 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 147.88 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 5.94 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 5.69 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 0.24 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 5.58 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 5.35 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 0.23 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 21.54 # Average write queue length when enqueuing
+system.mem_ctrls.avgWrQLen 21.49 # Average write queue length when enqueuing
system.mem_ctrls.readRowHits 302 # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits 15 # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate 80.53 # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate 32.61 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 62.97 # Average gap between requests
+system.mem_ctrls.avgGap 67.02 # Average gap between requests
system.mem_ctrls.pageHitRate 75.30 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 151200 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 84000 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 1859520 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.actEnergy 164220 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 77280 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 1839264 # Energy for read commands per rank (pJ)
system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 21272400 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 182400 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 25583760 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 814.665648 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 206 # Time in different power states
+system.mem_ctrls_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 2689032 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 56064 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 13011960 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 183552 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 20479932 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 584.206184 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 29013 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 34 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1040 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 30172 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 197400 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 2620800 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 165888 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 20904408 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 505200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 26783256 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 852.861292 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 1046 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 478 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 4969 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 28535 # Time in different power states
+system.mem_ctrls_1.actEnergy 364140 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 181608 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 2444736 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 133632 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 3405408 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 211968 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 12011952 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 266496 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 21478500 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 612.691123 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 26306 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 440 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 1040 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 29634 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 694 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 6540 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 26342 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -296,8 +306,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 32936 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 32936 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 35056 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 35056 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
@@ -316,7 +326,7 @@ system.cpu.num_mem_refs 717 # nu
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 32936 # Number of busy cycles
+system.cpu.num_busy_cycles 35056 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 396 # Number of branches fetched
@@ -356,7 +366,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
system.ruby.outstanding_req_hist_seqr::bucket_size 1
system.ruby.outstanding_req_hist_seqr::max_bucket 9
system.ruby.outstanding_req_hist_seqr::samples 3295
@@ -364,13 +374,13 @@ system.ruby.outstanding_req_hist_seqr::mean 1
system.ruby.outstanding_req_hist_seqr::gmean 1
system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 3295 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.outstanding_req_hist_seqr::total 3295
-system.ruby.latency_hist_seqr::bucket_size 64
-system.ruby.latency_hist_seqr::max_bucket 639
+system.ruby.latency_hist_seqr::bucket_size 32
+system.ruby.latency_hist_seqr::max_bucket 319
system.ruby.latency_hist_seqr::samples 3294
-system.ruby.latency_hist_seqr::mean 8.998786
-system.ruby.latency_hist_seqr::gmean 1.800750
-system.ruby.latency_hist_seqr::stdev 22.386902
-system.ruby.latency_hist_seqr | 3204 97.27% 97.27% | 86 2.61% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 2 0.06% 99.94% | 2 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 9.642380
+system.ruby.latency_hist_seqr::gmean 1.819734
+system.ruby.latency_hist_seqr::stdev 23.663336
+system.ruby.latency_hist_seqr | 2910 88.34% 88.34% | 293 8.89% 97.24% | 85 2.58% 99.82% | 2 0.06% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 4 0.12% 100.00%
system.ruby.latency_hist_seqr::total 3294
system.ruby.hit_latency_hist_seqr::bucket_size 2
system.ruby.hit_latency_hist_seqr::max_bucket 19
@@ -380,19 +390,19 @@ system.ruby.hit_latency_hist_seqr::gmean 1.059708
system.ruby.hit_latency_hist_seqr::stdev 1.536503
system.ruby.hit_latency_hist_seqr | 2784 97.58% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 0 0.00% 97.58% | 69 2.42% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.hit_latency_hist_seqr::total 2853
-system.ruby.miss_latency_hist_seqr::bucket_size 64
-system.ruby.miss_latency_hist_seqr::max_bucket 639
+system.ruby.miss_latency_hist_seqr::bucket_size 32
+system.ruby.miss_latency_hist_seqr::max_bucket 319
system.ruby.miss_latency_hist_seqr::samples 441
-system.ruby.miss_latency_hist_seqr::mean 59.181406
-system.ruby.miss_latency_hist_seqr::gmean 55.608631
-system.ruby.miss_latency_hist_seqr::stdev 28.659343
-system.ruby.miss_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 63.988662
+system.ruby.miss_latency_hist_seqr::gmean 60.139666
+system.ruby.miss_latency_hist_seqr::stdev 27.525151
+system.ruby.miss_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00%
system.ruby.miss_latency_hist_seqr::total 441
system.ruby.Directory.incomplete_times_seqr 440
system.ruby.dir_cntrl0.probeFilter.demand_hits 0 # Number of cache demand hits
system.ruby.dir_cntrl0.probeFilter.demand_misses 0 # Number of cache demand misses
system.ruby.dir_cntrl0.probeFilter.demand_accesses 0 # Number of cache demand accesses
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.L1Dcache.demand_hits 469 # Number of cache demand hits
system.ruby.l1_cntrl0.L1Dcache.demand_misses 240 # Number of cache demand misses
system.ruby.l1_cntrl0.L1Dcache.demand_accesses 709 # Number of cache demand accesses
@@ -402,12 +412,12 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses 2585
system.ruby.l1_cntrl0.L2cache.demand_hits 69 # Number of cache demand hits
system.ruby.l1_cntrl0.L2cache.demand_misses 441 # Number of cache demand misses
system.ruby.l1_cntrl0.L2cache.demand_accesses 510 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.fully_busy_cycles 5 # cycles for which number of transistions == max transitions
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 5.141031
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 4.830129
system.ruby.network.routers0.msg_count.Request_Control::2 441
system.ruby.network.routers0.msg_count.Response_Data::4 441
system.ruby.network.routers0.msg_count.Writeback_Data::5 81
@@ -422,8 +432,8 @@ system.ruby.network.routers0.msg_bytes.Writeback_Control::2 3400
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 3400
system.ruby.network.routers0.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers0.msg_bytes.Unblock_Control::5 3520
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 5.141031
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 4.830129
system.ruby.network.routers1.msg_count.Request_Control::2 441
system.ruby.network.routers1.msg_count.Response_Data::4 441
system.ruby.network.routers1.msg_count.Writeback_Data::5 81
@@ -438,8 +448,8 @@ system.ruby.network.routers1.msg_bytes.Writeback_Control::2 3400
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 3400
system.ruby.network.routers1.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers1.msg_bytes.Unblock_Control::5 3520
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 5.141031
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 4.830129
system.ruby.network.routers2.msg_count.Request_Control::2 441
system.ruby.network.routers2.msg_count.Response_Data::4 441
system.ruby.network.routers2.msg_count.Writeback_Data::5 81
@@ -454,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2 3400
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 3400
system.ruby.network.routers2.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers2.msg_bytes.Unblock_Control::5 3520
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Request_Control 1323
system.ruby.network.msg_count.Response_Data 1323
system.ruby.network.msg_count.Writeback_Data 243
@@ -465,13 +475,13 @@ system.ruby.network.msg_byte.Response_Data 95256
system.ruby.network.msg_byte.Writeback_Data 17496
system.ruby.network.msg_byte.Writeback_Control 28656
system.ruby.network.msg_byte.Unblock_Control 10560
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 32936 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 6.670513
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 35056 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 6.267115
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 441
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 425
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 31752
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 3400
-system.ruby.network.routers0.throttle1.link_utilization 3.611550
+system.ruby.network.routers0.throttle1.link_utilization 3.393142
system.ruby.network.routers0.throttle1.msg_count.Request_Control::2 441
system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::5 81
system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::2 425
@@ -482,7 +492,7 @@ system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Data::5 5832
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::2 3400
system.ruby.network.routers0.throttle1.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers0.throttle1.msg_bytes.Unblock_Control::5 3520
-system.ruby.network.routers1.throttle0.link_utilization 3.611550
+system.ruby.network.routers1.throttle0.link_utilization 3.393142
system.ruby.network.routers1.throttle0.msg_count.Request_Control::2 441
system.ruby.network.routers1.throttle0.msg_count.Writeback_Data::5 81
system.ruby.network.routers1.throttle0.msg_count.Writeback_Control::2 425
@@ -493,17 +503,17 @@ system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Data::5 5832
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::2 3400
system.ruby.network.routers1.throttle0.msg_bytes.Writeback_Control::5 2752
system.ruby.network.routers1.throttle0.msg_bytes.Unblock_Control::5 3520
-system.ruby.network.routers1.throttle1.link_utilization 6.670513
+system.ruby.network.routers1.throttle1.link_utilization 6.267115
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 441
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 425
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 31752
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 3400
-system.ruby.network.routers2.throttle0.link_utilization 6.670513
+system.ruby.network.routers2.throttle0.link_utilization 6.267115
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 441
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 425
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 31752
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 3400
-system.ruby.network.routers2.throttle1.link_utilization 3.611550
+system.ruby.network.routers2.throttle1.link_utilization 3.393142
system.ruby.network.routers2.throttle1.msg_count.Request_Control::2 441
system.ruby.network.routers2.throttle1.msg_count.Writeback_Data::5 81
system.ruby.network.routers2.throttle1.msg_count.Writeback_Control::2 425
@@ -517,10 +527,10 @@ system.ruby.network.routers2.throttle1.msg_bytes.Unblock_Control::5 3520
system.ruby.LD.latency_hist_seqr::bucket_size 16
system.ruby.LD.latency_hist_seqr::max_bucket 159
system.ruby.LD.latency_hist_seqr::samples 415
-system.ruby.LD.latency_hist_seqr::mean 19.850602
-system.ruby.LD.latency_hist_seqr::gmean 4.833066
-system.ruby.LD.latency_hist_seqr::stdev 26.151303
-system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 70 16.87% 92.53% | 20 4.82% 97.35% | 11 2.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 21.354217
+system.ruby.LD.latency_hist_seqr::gmean 4.945859
+system.ruby.LD.latency_hist_seqr::stdev 28.670834
+system.ruby.LD.latency_hist_seqr | 269 64.82% 64.82% | 42 10.12% 74.94% | 3 0.72% 75.66% | 69 16.63% 92.29% | 18 4.34% 96.63% | 14 3.37% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 415
system.ruby.LD.hit_latency_hist_seqr::bucket_size 2
system.ruby.LD.hit_latency_hist_seqr::max_bucket 19
@@ -533,18 +543,18 @@ system.ruby.LD.hit_latency_hist_seqr::total 269
system.ruby.LD.miss_latency_hist_seqr::bucket_size 16
system.ruby.LD.miss_latency_hist_seqr::max_bucket 159
system.ruby.LD.miss_latency_hist_seqr::samples 146
-system.ruby.LD.miss_latency_hist_seqr::mean 52.116438
-system.ruby.LD.miss_latency_hist_seqr::gmean 48.763829
-system.ruby.LD.miss_latency_hist_seqr::stdev 17.717519
-system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 56.390411
+system.ruby.LD.miss_latency_hist_seqr::gmean 52.068669
+system.ruby.LD.miss_latency_hist_seqr::stdev 20.461022
+system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 146
-system.ruby.ST.latency_hist_seqr::bucket_size 32
-system.ruby.ST.latency_hist_seqr::max_bucket 319
+system.ruby.ST.latency_hist_seqr::bucket_size 8
+system.ruby.ST.latency_hist_seqr::max_bucket 79
system.ruby.ST.latency_hist_seqr::samples 294
-system.ruby.ST.latency_hist_seqr::mean 10.064626
-system.ruby.ST.latency_hist_seqr::gmean 2.035894
-system.ruby.ST.latency_hist_seqr::stdev 25.936505
-system.ruby.ST.latency_hist_seqr | 262 89.12% 89.12% | 22 7.48% 96.60% | 9 3.06% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 9.778912
+system.ruby.ST.latency_hist_seqr::gmean 2.043604
+system.ruby.ST.latency_hist_seqr::stdev 20.538869
+system.ruby.ST.latency_hist_seqr | 236 80.27% 80.27% | 11 3.74% 84.01% | 0 0.00% 84.01% | 15 5.10% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 0 0.00% 89.12% | 22 7.48% 96.60% | 5 1.70% 98.30% | 5 1.70% 100.00%
system.ruby.ST.latency_hist_seqr::total 294
system.ruby.ST.hit_latency_hist_seqr::bucket_size 2
system.ruby.ST.hit_latency_hist_seqr::max_bucket 19
@@ -554,21 +564,21 @@ system.ruby.ST.hit_latency_hist_seqr::gmean 1.112699
system.ruby.ST.hit_latency_hist_seqr::stdev 2.066980
system.ruby.ST.hit_latency_hist_seqr | 236 95.55% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 0 0.00% 95.55% | 11 4.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 247
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 8
+system.ruby.ST.miss_latency_hist_seqr::max_bucket 79
system.ruby.ST.miss_latency_hist_seqr::samples 47
-system.ruby.ST.miss_latency_hist_seqr::mean 55.361702
-system.ruby.ST.miss_latency_hist_seqr::gmean 48.711518
-system.ruby.ST.miss_latency_hist_seqr::stdev 42.031265
-system.ruby.ST.miss_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 53.574468
+system.ruby.ST.miss_latency_hist_seqr::gmean 49.876949
+system.ruby.ST.miss_latency_hist_seqr::stdev 18.206240
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 47
-system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
-system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
+system.ruby.IFETCH.latency_hist_seqr::bucket_size 32
+system.ruby.IFETCH.latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.latency_hist_seqr::samples 2585
-system.ruby.IFETCH.latency_hist_seqr::mean 7.135397
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.515500
-system.ruby.IFETCH.latency_hist_seqr::stdev 20.744191
-system.ruby.IFETCH.latency_hist_seqr | 2536 98.10% 98.10% | 46 1.78% 99.88% | 0 0.00% 99.88% | 0 0.00% 99.88% | 1 0.04% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 7.746615
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.529553
+system.ruby.IFETCH.latency_hist_seqr::stdev 22.548460
+system.ruby.IFETCH.latency_hist_seqr | 2337 90.41% 90.41% | 199 7.70% 98.10% | 43 1.66% 99.77% | 2 0.08% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 0 0.00% 99.85% | 4 0.15% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 2585
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 2
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 19
@@ -578,13 +588,13 @@ system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1.022830
system.ruby.IFETCH.hit_latency_hist_seqr::stdev 0.965875
system.ruby.IFETCH.hit_latency_hist_seqr | 2315 99.06% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 0 0.00% 99.06% | 22 0.94% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.hit_latency_hist_seqr::total 2337
-system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
-system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
+system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 32
+system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.miss_latency_hist_seqr::samples 248
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.064516
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 61.606137
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 29.893804
-system.ruby.IFETCH.miss_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.435484
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 67.827440
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 30.751253
+system.ruby.IFETCH.miss_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 248
system.ruby.L1Cache.hit_mach_latency_hist_seqr::bucket_size 1
system.ruby.L1Cache.hit_mach_latency_hist_seqr::max_bucket 9
@@ -600,13 +610,13 @@ system.ruby.L2Cache.hit_mach_latency_hist_seqr::mean 11
system.ruby.L2Cache.hit_mach_latency_hist_seqr::gmean 11.000000
system.ruby.L2Cache.hit_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 69 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.L2Cache.hit_mach_latency_hist_seqr::total 69
-system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
-system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
+system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 32
+system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 319
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 441
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.181406
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.608631
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 28.659343
-system.ruby.Directory.miss_mach_latency_hist_seqr | 351 79.59% 79.59% | 86 19.50% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 2 0.45% 99.55% | 2 0.45% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 63.988662
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 60.139666
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 27.525151
+system.ruby.Directory.miss_mach_latency_hist_seqr | 57 12.93% 12.93% | 293 66.44% 79.37% | 85 19.27% 98.64% | 2 0.45% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 0 0.00% 99.09% | 4 0.91% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 441
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
@@ -651,10 +661,10 @@ system.ruby.LD.L2Cache.hit_type_mach_latency_hist_seqr::total 36
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 16
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 159
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 146
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 52.116438
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 48.763829
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 17.717519
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 70 47.95% 78.77% | 20 13.70% 92.47% | 11 7.53% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.390411
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.068669
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 20.461022
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 42 28.77% 28.77% | 3 2.05% 30.82% | 69 47.26% 78.08% | 18 12.33% 90.41% | 14 9.59% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 146
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.ST.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -670,13 +680,13 @@ system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.L2Cache.hit_type_mach_latency_hist_seqr::total 11
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 8
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 79
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 47
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.361702
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.711518
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 42.031265
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 15 31.91% 31.91% | 22 46.81% 78.72% | 9 19.15% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 0 0.00% 97.87% | 1 2.13% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 53.574468
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 49.876949
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 18.206240
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 15 31.91% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 0 0.00% 31.91% | 22 46.81% 78.72% | 5 10.64% 89.36% | 5 10.64% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 47
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.L1Cache.hit_type_mach_latency_hist_seqr::max_bucket 9
@@ -692,13 +702,13 @@ system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::mean 11
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::gmean 11.000000
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 22 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.L2Cache.hit_type_mach_latency_hist_seqr::total 22
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 248
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.064516
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 61.606137
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 29.893804
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 199 80.24% 80.24% | 46 18.55% 98.79% | 0 0.00% 98.79% | 0 0.00% 98.79% | 1 0.40% 99.19% | 2 0.81% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.435484
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 67.827440
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 30.751253
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 199 80.24% 80.24% | 43 17.34% 97.58% | 2 0.81% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 0 0.00% 98.39% | 4 1.61% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 248
system.ruby.Directory_Controller.GETX 51 0.00% 0.00%
system.ruby.Directory_Controller.GETS 410 0.00% 0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 538bb6cd3..7199cc5b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -22,11 +23,15 @@ kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
-mem_ranges=0:268435455
+mem_ranges=0:268435455:0:0:0:0
memories=system.mem_ctrls
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu.clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -122,7 +132,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
kvmInSE=false
@@ -145,27 +155,27 @@ transition_latency=100000
[system.mem_ctrls]
type=DRAMCtrl
-IDD0=0.075000
+IDD0=0.055000
IDD02=0.000000
-IDD2N=0.050000
+IDD2N=0.032000
IDD2N2=0.000000
IDD2P0=0.000000
IDD2P02=0.000000
-IDD2P1=0.000000
+IDD2P1=0.032000
IDD2P12=0.000000
-IDD3N=0.057000
+IDD3N=0.038000
IDD3N2=0.000000
IDD3P0=0.000000
IDD3P02=0.000000
-IDD3P1=0.000000
+IDD3P1=0.038000
IDD3P12=0.000000
-IDD4R=0.187000
+IDD4R=0.157000
IDD4R2=0.000000
-IDD4W=0.165000
+IDD4W=0.125000
IDD4W2=0.000000
-IDD5=0.220000
+IDD5=0.235000
IDD52=0.000000
-IDD6=0.000000
+IDD6=0.020000
IDD62=0.000000
VDD=1.500000
VDD2=0.000000
@@ -177,6 +187,7 @@ burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
device_bus_width=8
device_rowbuffer_size=1024
device_size=536870912
@@ -184,12 +195,17 @@ devices_per_rank=8
dll=true
eventq_index=0
in_addr_map=true
+kvm_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
page_policy=open_adaptive
-range=0:268435455
+power_model=Null
+range=0:268435455:5:19:0:0
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10
@@ -211,9 +227,9 @@ tRTW=3
tWR=15
tWTR=8
tXAW=30
-tXP=0
+tXP=6
tXPDLL=0
-tXS=0
+tXS=270
tXSDLL=0
write_buffer_size=64
write_high_thresh_perc=85
@@ -227,12 +243,17 @@ access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hot_lines=false
memory_size_bits=48
num_of_sequencers=1
number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
phys_mem=Null
+power_model=Null
randomization=false
[system.ruby.clk_domain]
@@ -249,6 +270,7 @@ children=directory dmaRequestToDir dmaResponseFromDir forwardFromDir requestToDi
buffer_size=0
clk_domain=system.ruby.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
directory=system.ruby.dir_cntrl0.directory
directory_latency=12
dmaRequestToDir=system.ruby.dir_cntrl0.dmaRequestToDir
@@ -256,6 +278,10 @@ dmaResponseFromDir=system.ruby.dir_cntrl0.dmaResponseFromDir
eventq_index=0
forwardFromDir=system.ruby.dir_cntrl0.forwardFromDir
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestToDir=system.ruby.dir_cntrl0.requestToDir
responseFromDir=system.ruby.dir_cntrl0.responseFromDir
@@ -329,11 +355,16 @@ cacheMemory=system.ruby.l1_cntrl0.cacheMemory
cache_response_latency=12
clk_domain=system.cpu.clk_domain
cluster_id=0
+default_p_state=UNDEFINED
eventq_index=0
forwardToCache=system.ruby.l1_cntrl0.forwardToCache
issue_latency=2
mandatoryQueue=system.ruby.l1_cntrl0.mandatoryQueue
number_of_TBEs=256
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
recycle_latency=10
requestFromCache=system.ruby.l1_cntrl0.requestFromCache
responseFromCache=system.ruby.l1_cntrl0.responseFromCache
@@ -415,17 +446,22 @@ coreid=99
dcache=system.ruby.l1_cntrl0.cacheMemory
dcache_hit_latency=1
deadlock_threshold=500000
+default_p_state=UNDEFINED
eventq_index=0
+garnet_standalone=false
icache=system.ruby.l1_cntrl0.cacheMemory
icache_hit_latency=1
is_cpu_sequencer=true
max_outstanding_requests=16
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
system=system
-using_network_tester=false
using_ruby_tester=false
version=0
slave=system.cpu.icache_port system.cpu.dcache_port
@@ -438,18 +474,23 @@ eventq_index=0
[system.ruby.network]
type=SimpleNetwork
-children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_links0 int_links1 routers0 routers1 routers2
+children=ext_links0 ext_links1 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 int_links2 int_links3 routers0 routers1 routers2
adaptive_routing=false
buffer_size=0
clk_domain=system.ruby.clk_domain
control_msg_size=8
+default_p_state=UNDEFINED
endpoint_bandwidth=1000
eventq_index=0
ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1
-int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19
-int_links=system.ruby.network.int_links0 system.ruby.network.int_links1
+int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39
+int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 system.ruby.network.int_links2 system.ruby.network.int_links3
netifs=
number_of_virtual_networks=5
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
routers=system.ruby.network.routers0 system.ruby.network.routers1 system.ruby.network.routers2
ruby_system=system.ruby
topology=Crossbar
@@ -616,32 +657,206 @@ eventq_index=0
ordered=true
randomization=false
+[system.ruby.network.int_link_buffers20]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers21]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers22]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers23]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers24]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers25]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers26]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers27]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers28]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers29]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers30]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers31]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers32]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers33]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers34]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers35]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers36]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers37]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers38]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
+[system.ruby.network.int_link_buffers39]
+type=MessageBuffer
+buffer_size=0
+eventq_index=0
+ordered=true
+randomization=false
+
[system.ruby.network.int_links0]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=2
-node_a=system.ruby.network.routers0
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers0
+src_outport=
weight=1
[system.ruby.network.int_links1]
type=SimpleIntLink
bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers2
eventq_index=0
latency=1
link_id=3
-node_a=system.ruby.network.routers1
-node_b=system.ruby.network.routers2
+src_node=system.ruby.network.routers1
+src_outport=
+weight=1
+
+[system.ruby.network.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers0
+eventq_index=0
+latency=1
+link_id=4
+src_node=system.ruby.network.routers2
+src_outport=
+weight=1
+
+[system.ruby.network.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+dst_inport=
+dst_node=system.ruby.network.routers1
+eventq_index=0
+latency=1
+link_id=5
+src_node=system.ruby.network.routers2
+src_outport=
weight=1
[system.ruby.network.routers0]
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers0.port_buffers00 system.ruby.network.routers0.port_buffers01 system.ruby.network.routers0.port_buffers02 system.ruby.network.routers0.port_buffers03 system.ruby.network.routers0.port_buffers04 system.ruby.network.routers0.port_buffers05 system.ruby.network.routers0.port_buffers06 system.ruby.network.routers0.port_buffers07 system.ruby.network.routers0.port_buffers08 system.ruby.network.routers0.port_buffers09 system.ruby.network.routers0.port_buffers10 system.ruby.network.routers0.port_buffers11 system.ruby.network.routers0.port_buffers12 system.ruby.network.routers0.port_buffers13 system.ruby.network.routers0.port_buffers14
+power_model=Null
router_id=0
virt_nets=5
@@ -754,8 +969,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers1.port_buffers00 system.ruby.network.routers1.port_buffers01 system.ruby.network.routers1.port_buffers02 system.ruby.network.routers1.port_buffers03 system.ruby.network.routers1.port_buffers04 system.ruby.network.routers1.port_buffers05 system.ruby.network.routers1.port_buffers06 system.ruby.network.routers1.port_buffers07 system.ruby.network.routers1.port_buffers08 system.ruby.network.routers1.port_buffers09 system.ruby.network.routers1.port_buffers10 system.ruby.network.routers1.port_buffers11 system.ruby.network.routers1.port_buffers12 system.ruby.network.routers1.port_buffers13 system.ruby.network.routers1.port_buffers14
+power_model=Null
router_id=1
virt_nets=5
@@ -868,8 +1089,14 @@ randomization=false
type=Switch
children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19
clk_domain=system.ruby.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
+latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
port_buffers=system.ruby.network.routers2.port_buffers00 system.ruby.network.routers2.port_buffers01 system.ruby.network.routers2.port_buffers02 system.ruby.network.routers2.port_buffers03 system.ruby.network.routers2.port_buffers04 system.ruby.network.routers2.port_buffers05 system.ruby.network.routers2.port_buffers06 system.ruby.network.routers2.port_buffers07 system.ruby.network.routers2.port_buffers08 system.ruby.network.routers2.port_buffers09 system.ruby.network.routers2.port_buffers10 system.ruby.network.routers2.port_buffers11 system.ruby.network.routers2.port_buffers12 system.ruby.network.routers2.port_buffers13 system.ruby.network.routers2.port_buffers14 system.ruby.network.routers2.port_buffers15 system.ruby.network.routers2.port_buffers16 system.ruby.network.routers2.port_buffers17 system.ruby.network.routers2.port_buffers18 system.ruby.network.routers2.port_buffers19
+power_model=Null
router_id=2
virt_nets=5
@@ -1016,9 +1243,14 @@ randomization=false
[system.sys_port_proxy]
type=RubyPortProxy
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_cpu_sequencer=true
no_retry_on_stall=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000
+p_state_clk_gate_min=1
+power_model=Null
ruby_system=system.ruby
support_data_reqs=true
support_inst_reqs=true
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 1c18978fa..63982fce4 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -4,9 +4,8 @@ warn: rounding error > tolerance
1.250000 rounded to 1
warn: rounding error > tolerance
1.250000 rounded to 1
-warn: rounding error > tolerance
- 1.250000 rounded to 1
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files!
warn: ignoring syscall sigprocmask(1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 98025cd1e..d4c6f5ba8 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:26
-gem5 executing on zizzer, pid 34072
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
+gem5 compiled Oct 11 2016 00:00:58
+gem5 started Oct 13 2016 20:19:46
+gem5 executing on e108600-lin, pid 28078
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 41659 because target called exit()
+Exiting @ tick 43520 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index f97a14626..535942f10 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -1,19 +1,19 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000042 # Number of seconds simulated
-sim_ticks 41659 # Number of ticks simulated
-final_tick 41659 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000044 # Number of seconds simulated
+sim_ticks 43520 # Number of ticks simulated
+final_tick 43520 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 54027 # Simulator instruction rate (inst/s)
-host_op_rate 54016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 873053 # Simulator tick rate (ticks/s)
-host_mem_usage 453224 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 93431 # Simulator instruction rate (inst/s)
+host_op_rate 93392 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1576605 # Simulator tick rate (ticks/s)
+host_mem_usage 411000 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1 # Clock period in ticks
-system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::ruby.dir_cntrl0 40064 # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total 40064 # Number of bytes read from this memory
system.mem_ctrls.bytes_written::ruby.dir_cntrl0 39808 # Number of bytes written to this memory
@@ -22,59 +22,59 @@ system.mem_ctrls.num_reads::ruby.dir_cntrl0 626 #
system.mem_ctrls.num_reads::total 626 # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::ruby.dir_cntrl0 622 # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total 622 # Number of write requests responded to by this memory
-system.mem_ctrls.bw_read::ruby.dir_cntrl0 961712955 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_read::total 961712955 # Total read bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::ruby.dir_cntrl0 955567824 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_write::total 955567824 # Write bandwidth from this memory (bytes/s)
-system.mem_ctrls.bw_total::ruby.dir_cntrl0 1917280780 # Total bandwidth to/from this memory (bytes/s)
-system.mem_ctrls.bw_total::total 1917280780 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_read::ruby.dir_cntrl0 920588235 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_read::total 920588235 # Total read bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::ruby.dir_cntrl0 914705882 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_write::total 914705882 # Write bandwidth from this memory (bytes/s)
+system.mem_ctrls.bw_total::ruby.dir_cntrl0 1835294118 # Total bandwidth to/from this memory (bytes/s)
+system.mem_ctrls.bw_total::total 1835294118 # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.readReqs 626 # Number of read requests accepted
system.mem_ctrls.writeReqs 622 # Number of write requests accepted
system.mem_ctrls.readBursts 626 # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts 622 # Number of DRAM write bursts, including those merged in the write queue
-system.mem_ctrls.bytesReadDRAM 24960 # Total number of bytes read from DRAM
-system.mem_ctrls.bytesReadWrQ 15104 # Total number of bytes read from write queue
-system.mem_ctrls.bytesWritten 24000 # Total number of bytes written to DRAM
+system.mem_ctrls.bytesReadDRAM 24512 # Total number of bytes read from DRAM
+system.mem_ctrls.bytesReadWrQ 15552 # Total number of bytes read from write queue
+system.mem_ctrls.bytesWritten 23424 # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys 40064 # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys 39808 # Total written bytes from the system interface side
-system.mem_ctrls.servicedByWrQ 236 # Number of DRAM read bursts serviced by the write queue
-system.mem_ctrls.mergedWrBursts 219 # Number of DRAM write bursts merged with an existing one
+system.mem_ctrls.servicedByWrQ 243 # Number of DRAM read bursts serviced by the write queue
+system.mem_ctrls.mergedWrBursts 231 # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3 30 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::4 23 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::4 24 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::6 58 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::7 62 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::8 63 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::9 4 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::10 24 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::11 15 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::12 32 # Per bank write bursts
-system.mem_ctrls.perBankRdBursts::13 66 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::6 53 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::7 53 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::8 68 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::9 5 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::10 25 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::11 14 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::12 30 # Per bank write bursts
+system.mem_ctrls.perBankRdBursts::13 68 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14 10 # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15 1 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1 1 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::3 31 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::4 22 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::3 32 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::4 23 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::6 54 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::7 57 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::8 65 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::9 3 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::10 21 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::6 48 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::7 43 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::8 68 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::9 5 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::10 23 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11 15 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12 31 # Per bank write bursts
-system.mem_ctrls.perBankWrBursts::13 63 # Per bank write bursts
+system.mem_ctrls.perBankWrBursts::13 65 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14 10 # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15 1 # Per bank write bursts
system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry
-system.mem_ctrls.totGap 41626 # Total gap between requests
+system.mem_ctrls.totGap 43487 # Total gap between requests
system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2)
system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2)
@@ -89,7 +89,7 @@ system.mem_ctrls.writePktSize::3 0 # Wr
system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2)
system.mem_ctrls.writePktSize::6 622 # Write request sizes (log2)
-system.mem_ctrls.rdQLenPdf::0 390 # What read queue length does an incoming req see
+system.mem_ctrls.rdQLenPdf::0 383 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see
@@ -136,24 +136,24 @@ system.mem_ctrls.wrQLenPdf::11 1 # Wh
system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::17 18 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::18 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::19 27 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::20 27 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::21 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::22 25 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::23 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::24 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::25 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::26 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::27 24 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::28 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::29 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::30 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::31 23 # What write queue length does an incoming req see
-system.mem_ctrls.wrQLenPdf::32 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::16 7 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::17 17 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::18 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::19 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::20 26 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::21 28 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::22 24 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::23 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::24 23 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::25 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::26 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::27 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::28 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::29 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::30 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::31 22 # What write queue length does an incoming req see
+system.mem_ctrls.wrQLenPdf::32 22 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see
@@ -185,89 +185,98 @@ system.mem_ctrls.wrQLenPdf::60 0 # Wh
system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.mem_ctrls.bytesPerActivate::samples 105 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::mean 455.923810 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::gmean 317.170384 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::stdev 344.729986 # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::0-127 11 10.48% 10.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::128-255 29 27.62% 38.10% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::256-383 10 9.52% 47.62% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::384-511 10 9.52% 57.14% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::512-639 14 13.33% 70.48% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::640-767 5 4.76% 75.24% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::768-895 4 3.81% 79.05% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::896-1023 5 4.76% 83.81% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::1024-1151 17 16.19% 100.00% # Bytes accessed per row activation
-system.mem_ctrls.bytesPerActivate::total 105 # Bytes accessed per row activation
-system.mem_ctrls.rdPerTurnAround::samples 23 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::mean 16.434783 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::gmean 16.058223 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::stdev 4.388270 # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::12-13 3 13.04% 13.04% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::14-15 10 43.48% 56.52% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::16-17 5 21.74% 78.26% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::18-19 4 17.39% 95.65% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::34-35 1 4.35% 100.00% # Reads before turning the bus around for writes
-system.mem_ctrls.rdPerTurnAround::total 23 # Reads before turning the bus around for writes
-system.mem_ctrls.wrPerTurnAround::samples 23 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::mean 16.304348 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::gmean 16.283756 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::stdev 0.875670 # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::16 20 86.96% 86.96% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::17 1 4.35% 91.30% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::19 2 8.70% 100.00% # Writes before turning the bus around for reads
-system.mem_ctrls.wrPerTurnAround::total 23 # Writes before turning the bus around for reads
-system.mem_ctrls.totQLat 4371 # Total ticks spent queuing
-system.mem_ctrls.totMemAccLat 11781 # Total ticks spent from burst creation until serviced by the DRAM
-system.mem_ctrls.totBusLat 1950 # Total ticks spent in databus transfers
-system.mem_ctrls.avgQLat 11.21 # Average queueing delay per DRAM burst
+system.mem_ctrls.bytesPerActivate::samples 113 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::mean 404.389381 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::gmean 273.588270 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::stdev 327.373952 # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::0-127 20 17.70% 17.70% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::128-255 26 23.01% 40.71% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::256-383 16 14.16% 54.87% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::384-511 15 13.27% 68.14% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::512-639 5 4.42% 72.57% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::640-767 6 5.31% 77.88% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::768-895 8 7.08% 84.96% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::896-1023 5 4.42% 89.38% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::1024-1151 12 10.62% 100.00% # Bytes accessed per row activation
+system.mem_ctrls.bytesPerActivate::total 113 # Bytes accessed per row activation
+system.mem_ctrls.rdPerTurnAround::samples 22 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::mean 17 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::gmean 16.662586 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::stdev 4.253850 # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::14-15 8 36.36% 36.36% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::16-17 8 36.36% 72.73% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::18-19 5 22.73% 95.45% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::34-35 1 4.55% 100.00% # Reads before turning the bus around for writes
+system.mem_ctrls.rdPerTurnAround::total 22 # Reads before turning the bus around for writes
+system.mem_ctrls.wrPerTurnAround::samples 22 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::mean 16.636364 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::gmean 16.596436 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::stdev 1.216766 # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::16 17 77.27% 77.27% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::18 1 4.55% 81.82% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::19 4 18.18% 100.00% # Writes before turning the bus around for reads
+system.mem_ctrls.wrPerTurnAround::total 22 # Writes before turning the bus around for reads
+system.mem_ctrls.totQLat 6435 # Total ticks spent queuing
+system.mem_ctrls.totMemAccLat 13712 # Total ticks spent from burst creation until serviced by the DRAM
+system.mem_ctrls.totBusLat 1915 # Total ticks spent in databus transfers
+system.mem_ctrls.avgQLat 16.80 # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst
-system.mem_ctrls.avgMemAccLat 30.21 # Average memory access latency per DRAM burst
-system.mem_ctrls.avgRdBW 599.15 # Average DRAM read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBW 576.11 # Average achieved write bandwidth in MiByte/s
-system.mem_ctrls.avgRdBWSys 961.71 # Average system read bandwidth in MiByte/s
-system.mem_ctrls.avgWrBWSys 955.57 # Average system write bandwidth in MiByte/s
+system.mem_ctrls.avgMemAccLat 35.80 # Average memory access latency per DRAM burst
+system.mem_ctrls.avgRdBW 563.24 # Average DRAM read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBW 538.24 # Average achieved write bandwidth in MiByte/s
+system.mem_ctrls.avgRdBWSys 920.59 # Average system read bandwidth in MiByte/s
+system.mem_ctrls.avgWrBWSys 914.71 # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.mem_ctrls.busUtil 9.18 # Data bus utilization in percentage
-system.mem_ctrls.busUtilRead 4.68 # Data bus utilization in percentage for reads
-system.mem_ctrls.busUtilWrite 4.50 # Data bus utilization in percentage for writes
+system.mem_ctrls.busUtil 8.61 # Data bus utilization in percentage
+system.mem_ctrls.busUtilRead 4.40 # Data bus utilization in percentage for reads
+system.mem_ctrls.busUtilWrite 4.20 # Data bus utilization in percentage for writes
system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.mem_ctrls.avgWrQLen 24.82 # Average write queue length when enqueuing
-system.mem_ctrls.readRowHits 298 # Number of row buffer hits during reads
-system.mem_ctrls.writeRowHits 355 # Number of row buffer hits during writes
-system.mem_ctrls.readRowHitRate 76.41 # Row buffer hit rate for reads
-system.mem_ctrls.writeRowHitRate 88.09 # Row buffer hit rate for writes
-system.mem_ctrls.avgGap 33.35 # Average gap between requests
-system.mem_ctrls.pageHitRate 82.35 # Row buffer hit rate, read and write combined
-system.mem_ctrls_0.actEnergy 234360 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_0.preEnergy 130200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_0.readEnergy 1971840 # Energy for read commands per rank (pJ)
-system.mem_ctrls_0.writeEnergy 1555200 # Energy for write commands per rank (pJ)
-system.mem_ctrls_0.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_0.actBackEnergy 26028252 # Energy for active background per rank (pJ)
-system.mem_ctrls_0.preBackEnergy 682200 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_0.totalEnergy 33144852 # Total energy per rank (pJ)
-system.mem_ctrls_0.averagePower 845.747691 # Core power per rank (mW)
-system.mem_ctrls_0.memoryStateTime::IDLE 1011 # Time in different power states
+system.mem_ctrls.avgWrQLen 24.70 # Average write queue length when enqueuing
+system.mem_ctrls.readRowHits 286 # Number of row buffer hits during reads
+system.mem_ctrls.writeRowHits 342 # Number of row buffer hits during writes
+system.mem_ctrls.readRowHitRate 74.67 # Row buffer hit rate for reads
+system.mem_ctrls.writeRowHitRate 87.47 # Row buffer hit rate for writes
+system.mem_ctrls.avgGap 34.85 # Average gap between requests
+system.mem_ctrls.pageHitRate 81.14 # Row buffer hit rate, read and write combined
+system.mem_ctrls_0.actEnergy 264180 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_0.preEnergy 127512 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_0.readEnergy 1850688 # Energy for read commands per rank (pJ)
+system.mem_ctrls_0.writeEnergy 1236096 # Energy for write commands per rank (pJ)
+system.mem_ctrls_0.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_0.actBackEnergy 3917040 # Energy for active background per rank (pJ)
+system.mem_ctrls_0.preBackEnergy 69120 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_0.actPowerDownEnergy 15256848 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_0.prePowerDownEnergy 496128 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_0.totalEnergy 26290812 # Total energy per rank (pJ)
+system.mem_ctrls_0.averagePower 604.108732 # Core power per rank (mW)
+system.mem_ctrls_0.totalIdleTime 34684 # Total Idle time Per DRAM Rank
+system.mem_ctrls_0.memoryStateTime::IDLE 40 # Time in different power states
system.mem_ctrls_0.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT 36893 # Time in different power states
-system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.mem_ctrls_1.actEnergy 536760 # Energy for activate commands per rank (pJ)
-system.mem_ctrls_1.preEnergy 298200 # Energy for precharge commands per rank (pJ)
-system.mem_ctrls_1.readEnergy 2608320 # Energy for read commands per rank (pJ)
-system.mem_ctrls_1.writeEnergy 2166912 # Energy for write commands per rank (pJ)
-system.mem_ctrls_1.refreshEnergy 2542800 # Energy for refresh commands per rank (pJ)
-system.mem_ctrls_1.actBackEnergy 26345628 # Energy for active background per rank (pJ)
-system.mem_ctrls_1.preBackEnergy 403800 # Energy for precharge background per rank (pJ)
-system.mem_ctrls_1.totalEnergy 34902420 # Total energy per rank (pJ)
-system.mem_ctrls_1.averagePower 890.595050 # Core power per rank (mW)
-system.mem_ctrls_1.memoryStateTime::IDLE 832 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::PRE_PDN 1292 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT 7430 # Time in different power states
+system.mem_ctrls_0.memoryStateTime::ACT_PDN 33458 # Time in different power states
+system.mem_ctrls_1.actEnergy 599760 # Energy for activate commands per rank (pJ)
+system.mem_ctrls_1.preEnergy 309120 # Energy for precharge commands per rank (pJ)
+system.mem_ctrls_1.readEnergy 2524704 # Energy for read commands per rank (pJ)
+system.mem_ctrls_1.writeEnergy 1820736 # Energy for write commands per rank (pJ)
+system.mem_ctrls_1.refreshEnergy 3073200.000000 # Energy for refresh commands per rank (pJ)
+system.mem_ctrls_1.actBackEnergy 5746968 # Energy for active background per rank (pJ)
+system.mem_ctrls_1.preBackEnergy 231168 # Energy for precharge background per rank (pJ)
+system.mem_ctrls_1.actPowerDownEnergy 13781232 # Energy for active power-down per rank (pJ)
+system.mem_ctrls_1.prePowerDownEnergy 35712 # Energy for precharge power-down per rank (pJ)
+system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
+system.mem_ctrls_1.totalEnergy 28122600 # Total energy per rank (pJ)
+system.mem_ctrls_1.averagePower 646.199449 # Core power per rank (mW)
+system.mem_ctrls_1.totalIdleTime 29649 # Total Idle time Per DRAM Rank
+system.mem_ctrls_1.memoryStateTime::IDLE 448 # Time in different power states
system.mem_ctrls_1.memoryStateTime::REF 1300 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT 37357 # Time in different power states
-system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::PRE_PDN 93 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT 11457 # Time in different power states
+system.mem_ctrls_1.memoryStateTime::ACT_PDN 30222 # Time in different power states
+system.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
system.cpu.clk_domain.clock 1 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
@@ -302,8 +311,8 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 41659 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 41659 # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON 43520 # Cumulative time (in ticks) in various power states
+system.cpu.numCycles 43520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2577 # Number of instructions committed
@@ -322,7 +331,7 @@ system.cpu.num_mem_refs 717 # nu
system.cpu.num_load_insts 419 # Number of load instructions
system.cpu.num_store_insts 298 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 41659 # Number of busy cycles
+system.cpu.num_busy_cycles 43520 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.Branches 396 # Number of branches fetched
@@ -362,7 +371,7 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 2585 # Class of executed instruction
system.ruby.clk_domain.clock 1 # Clock period in ticks
-system.ruby.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.ruby.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
system.ruby.delayHist::bucket_size 1 # delay histogram for all message
system.ruby.delayHist::max_bucket 9 # delay histogram for all message
system.ruby.delayHist::samples 1248 # delay histogram for all message
@@ -378,10 +387,10 @@ system.ruby.outstanding_req_hist_seqr::total 3295
system.ruby.latency_hist_seqr::bucket_size 64
system.ruby.latency_hist_seqr::max_bucket 639
system.ruby.latency_hist_seqr::samples 3294
-system.ruby.latency_hist_seqr::mean 11.646934
-system.ruby.latency_hist_seqr::gmean 2.114776
-system.ruby.latency_hist_seqr::stdev 26.263922
-system.ruby.latency_hist_seqr | 3185 96.69% 96.69% | 90 2.73% 99.42% | 14 0.43% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.latency_hist_seqr::mean 12.211900
+system.ruby.latency_hist_seqr::gmean 2.131468
+system.ruby.latency_hist_seqr::stdev 27.594720
+system.ruby.latency_hist_seqr | 2924 88.77% 88.77% | 353 10.72% 99.48% | 12 0.36% 99.85% | 0 0.00% 99.85% | 2 0.06% 99.91% | 3 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.latency_hist_seqr::total 3294
system.ruby.hit_latency_hist_seqr::bucket_size 1
system.ruby.hit_latency_hist_seqr::max_bucket 9
@@ -393,21 +402,21 @@ system.ruby.hit_latency_hist_seqr::total 2668
system.ruby.miss_latency_hist_seqr::bucket_size 64
system.ruby.miss_latency_hist_seqr::max_bucket 639
system.ruby.miss_latency_hist_seqr::samples 626
-system.ruby.miss_latency_hist_seqr::mean 57.023962
-system.ruby.miss_latency_hist_seqr::gmean 51.467697
-system.ruby.miss_latency_hist_seqr::stdev 32.986607
-system.ruby.miss_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.miss_latency_hist_seqr::mean 59.996805
+system.ruby.miss_latency_hist_seqr::gmean 53.641558
+system.ruby.miss_latency_hist_seqr::stdev 34.472574
+system.ruby.miss_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.miss_latency_hist_seqr::total 626
system.ruby.Directory.incomplete_times_seqr 625
-system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
system.ruby.l1_cntrl0.cacheMemory.demand_hits 2668 # Number of cache demand hits
system.ruby.l1_cntrl0.cacheMemory.demand_misses 626 # Number of cache demand misses
system.ruby.l1_cntrl0.cacheMemory.demand_accesses 3294 # Number of cache demand accesses
-system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
-system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
+system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks
-system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.percent_links_utilized 7.489378
+system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.percent_links_utilized 7.169118
system.ruby.network.routers0.msg_count.Control::2 626
system.ruby.network.routers0.msg_count.Data::2 622
system.ruby.network.routers0.msg_count.Response_Data::4 626
@@ -416,8 +425,8 @@ system.ruby.network.routers0.msg_bytes.Control::2 5008
system.ruby.network.routers0.msg_bytes.Data::2 44784
system.ruby.network.routers0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers0.msg_bytes.Writeback_Control::3 4976
-system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers1.percent_links_utilized 7.489378
+system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers1.percent_links_utilized 7.169118
system.ruby.network.routers1.msg_count.Control::2 626
system.ruby.network.routers1.msg_count.Data::2 622
system.ruby.network.routers1.msg_count.Response_Data::4 626
@@ -426,8 +435,8 @@ system.ruby.network.routers1.msg_bytes.Control::2 5008
system.ruby.network.routers1.msg_bytes.Data::2 44784
system.ruby.network.routers1.msg_bytes.Response_Data::4 45072
system.ruby.network.routers1.msg_bytes.Writeback_Control::3 4976
-system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers2.percent_links_utilized 7.489378
+system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers2.percent_links_utilized 7.169118
system.ruby.network.routers2.msg_count.Control::2 626
system.ruby.network.routers2.msg_count.Data::2 622
system.ruby.network.routers2.msg_count.Response_Data::4 626
@@ -436,7 +445,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 5008
system.ruby.network.routers2.msg_bytes.Data::2 44784
system.ruby.network.routers2.msg_bytes.Response_Data::4 45072
system.ruby.network.routers2.msg_bytes.Writeback_Control::3 4976
-system.ruby.network.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
+system.ruby.network.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
system.ruby.network.msg_count.Control 1878
system.ruby.network.msg_count.Data 1866
system.ruby.network.msg_count.Response_Data 1878
@@ -445,33 +454,33 @@ system.ruby.network.msg_byte.Control 15024
system.ruby.network.msg_byte.Data 134352
system.ruby.network.msg_byte.Response_Data 135216
system.ruby.network.msg_byte.Writeback_Control 14928
-system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 41659 # Cumulative time (in ticks) in various power states
-system.ruby.network.routers0.throttle0.link_utilization 7.508582
+system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 43520 # Cumulative time (in ticks) in various power states
+system.ruby.network.routers0.throttle0.link_utilization 7.187500
system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 626
system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 622
system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 4976
-system.ruby.network.routers0.throttle1.link_utilization 7.470175
+system.ruby.network.routers0.throttle1.link_utilization 7.150735
system.ruby.network.routers0.throttle1.msg_count.Control::2 626
system.ruby.network.routers0.throttle1.msg_count.Data::2 622
system.ruby.network.routers0.throttle1.msg_bytes.Control::2 5008
system.ruby.network.routers0.throttle1.msg_bytes.Data::2 44784
-system.ruby.network.routers1.throttle0.link_utilization 7.470175
+system.ruby.network.routers1.throttle0.link_utilization 7.150735
system.ruby.network.routers1.throttle0.msg_count.Control::2 626
system.ruby.network.routers1.throttle0.msg_count.Data::2 622
system.ruby.network.routers1.throttle0.msg_bytes.Control::2 5008
system.ruby.network.routers1.throttle0.msg_bytes.Data::2 44784
-system.ruby.network.routers1.throttle1.link_utilization 7.508582
+system.ruby.network.routers1.throttle1.link_utilization 7.187500
system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 626
system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 622
system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 45072
system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 4976
-system.ruby.network.routers2.throttle0.link_utilization 7.508582
+system.ruby.network.routers2.throttle0.link_utilization 7.187500
system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 626
system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 622
system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 45072
system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 4976
-system.ruby.network.routers2.throttle1.link_utilization 7.470175
+system.ruby.network.routers2.throttle1.link_utilization 7.150735
system.ruby.network.routers2.throttle1.msg_count.Control::2 626
system.ruby.network.routers2.throttle1.msg_count.Data::2 622
system.ruby.network.routers2.throttle1.msg_bytes.Control::2 5008
@@ -486,13 +495,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 #
system.ruby.delayVCHist.vnet_2::samples 622 # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2 | 622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2
system.ruby.delayVCHist.vnet_2::total 622 # delay histogram for vnet_2
-system.ruby.LD.latency_hist_seqr::bucket_size 32
-system.ruby.LD.latency_hist_seqr::max_bucket 319
+system.ruby.LD.latency_hist_seqr::bucket_size 64
+system.ruby.LD.latency_hist_seqr::max_bucket 639
system.ruby.LD.latency_hist_seqr::samples 415
-system.ruby.LD.latency_hist_seqr::mean 30.537349
-system.ruby.LD.latency_hist_seqr::gmean 9.686440
-system.ruby.LD.latency_hist_seqr::stdev 30.265140
-system.ruby.LD.latency_hist_seqr | 170 40.96% 40.96% | 203 48.92% 89.88% | 35 8.43% 98.31% | 3 0.72% 99.04% | 3 0.72% 99.76% | 1 0.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.latency_hist_seqr::mean 33.354217
+system.ruby.LD.latency_hist_seqr::gmean 9.992707
+system.ruby.LD.latency_hist_seqr::stdev 38.395820
+system.ruby.LD.latency_hist_seqr | 297 71.57% 71.57% | 114 27.47% 99.04% | 2 0.48% 99.52% | 0 0.00% 99.52% | 0 0.00% 99.52% | 2 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.latency_hist_seqr::total 415
system.ruby.LD.hit_latency_hist_seqr::bucket_size 1
system.ruby.LD.hit_latency_hist_seqr::max_bucket 9
@@ -501,21 +510,21 @@ system.ruby.LD.hit_latency_hist_seqr::mean 1
system.ruby.LD.hit_latency_hist_seqr::gmean 1
system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 170 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.hit_latency_hist_seqr::total 170
-system.ruby.LD.miss_latency_hist_seqr::bucket_size 32
-system.ruby.LD.miss_latency_hist_seqr::max_bucket 319
+system.ruby.LD.miss_latency_hist_seqr::bucket_size 64
+system.ruby.LD.miss_latency_hist_seqr::max_bucket 639
system.ruby.LD.miss_latency_hist_seqr::samples 245
-system.ruby.LD.miss_latency_hist_seqr::mean 51.032653
-system.ruby.LD.miss_latency_hist_seqr::gmean 46.821080
-system.ruby.LD.miss_latency_hist_seqr::stdev 22.902478
-system.ruby.LD.miss_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.miss_latency_hist_seqr::mean 55.804082
+system.ruby.LD.miss_latency_hist_seqr::gmean 49.356103
+system.ruby.LD.miss_latency_hist_seqr::stdev 35.580698
+system.ruby.LD.miss_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.miss_latency_hist_seqr::total 245
-system.ruby.ST.latency_hist_seqr::bucket_size 64
-system.ruby.ST.latency_hist_seqr::max_bucket 639
+system.ruby.ST.latency_hist_seqr::bucket_size 32
+system.ruby.ST.latency_hist_seqr::max_bucket 319
system.ruby.ST.latency_hist_seqr::samples 294
-system.ruby.ST.latency_hist_seqr::mean 16.663265
-system.ruby.ST.latency_hist_seqr::gmean 3.036238
-system.ruby.ST.latency_hist_seqr::stdev 32.952425
-system.ruby.ST.latency_hist_seqr | 283 96.26% 96.26% | 6 2.04% 98.30% | 4 1.36% 99.66% | 0 0.00% 99.66% | 0 0.00% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.latency_hist_seqr::mean 16.173469
+system.ruby.ST.latency_hist_seqr::gmean 3.033104
+system.ruby.ST.latency_hist_seqr::stdev 28.208400
+system.ruby.ST.latency_hist_seqr | 210 71.43% 71.43% | 44 14.97% 86.39% | 36 12.24% 98.64% | 1 0.34% 98.98% | 2 0.68% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.latency_hist_seqr::total 294
system.ruby.ST.hit_latency_hist_seqr::bucket_size 1
system.ruby.ST.hit_latency_hist_seqr::max_bucket 9
@@ -524,21 +533,21 @@ system.ruby.ST.hit_latency_hist_seqr::mean 1
system.ruby.ST.hit_latency_hist_seqr::gmean 1
system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 210 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.hit_latency_hist_seqr::total 210
-system.ruby.ST.miss_latency_hist_seqr::bucket_size 64
-system.ruby.ST.miss_latency_hist_seqr::max_bucket 639
+system.ruby.ST.miss_latency_hist_seqr::bucket_size 32
+system.ruby.ST.miss_latency_hist_seqr::max_bucket 319
system.ruby.ST.miss_latency_hist_seqr::samples 84
-system.ruby.ST.miss_latency_hist_seqr::mean 55.821429
-system.ruby.ST.miss_latency_hist_seqr::gmean 48.772534
-system.ruby.ST.miss_latency_hist_seqr::stdev 40.751129
-system.ruby.ST.miss_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.miss_latency_hist_seqr::mean 54.107143
+system.ruby.ST.miss_latency_hist_seqr::gmean 48.596564
+system.ruby.ST.miss_latency_hist_seqr::stdev 27.751487
+system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.miss_latency_hist_seqr::total 84
system.ruby.IFETCH.latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.latency_hist_seqr::samples 2585
-system.ruby.IFETCH.latency_hist_seqr::mean 8.043714
-system.ruby.IFETCH.latency_hist_seqr::gmean 1.589638
-system.ruby.IFETCH.latency_hist_seqr::stdev 23.152025
-system.ruby.IFETCH.latency_hist_seqr | 2529 97.83% 97.83% | 46 1.78% 99.61% | 6 0.23% 99.85% | 0 0.00% 99.85% | 2 0.08% 99.92% | 2 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.latency_hist_seqr::mean 8.367118
+system.ruby.IFETCH.latency_hist_seqr::gmean 1.597827
+system.ruby.IFETCH.latency_hist_seqr::stdev 23.571466
+system.ruby.IFETCH.latency_hist_seqr | 2373 91.80% 91.80% | 202 7.81% 99.61% | 7 0.27% 99.88% | 0 0.00% 99.88% | 2 0.08% 99.96% | 1 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.latency_hist_seqr::total 2585
system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1
system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9
@@ -550,18 +559,18 @@ system.ruby.IFETCH.hit_latency_hist_seqr::total 2288
system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.miss_latency_hist_seqr::samples 297
-system.ruby.IFETCH.miss_latency_hist_seqr::mean 62.306397
-system.ruby.IFETCH.miss_latency_hist_seqr::gmean 56.498895
-system.ruby.IFETCH.miss_latency_hist_seqr::stdev 36.624977
-system.ruby.IFETCH.miss_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.miss_latency_hist_seqr::mean 65.121212
+system.ruby.IFETCH.miss_latency_hist_seqr::gmean 59.083052
+system.ruby.IFETCH.miss_latency_hist_seqr::stdev 34.625488
+system.ruby.IFETCH.miss_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.miss_latency_hist_seqr::total 297
system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64
system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639
system.ruby.Directory.miss_mach_latency_hist_seqr::samples 626
-system.ruby.Directory.miss_mach_latency_hist_seqr::mean 57.023962
-system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 51.467697
-system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 32.986607
-system.ruby.Directory.miss_mach_latency_hist_seqr | 517 82.59% 82.59% | 90 14.38% 96.96% | 14 2.24% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory.miss_mach_latency_hist_seqr::mean 59.996805
+system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 53.641558
+system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 34.472574
+system.ruby.Directory.miss_mach_latency_hist_seqr | 256 40.89% 40.89% | 353 56.39% 97.28% | 12 1.92% 99.20% | 0 0.00% 99.20% | 2 0.32% 99.52% | 3 0.48% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.Directory.miss_mach_latency_hist_seqr::total 626
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1
system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9
@@ -589,29 +598,29 @@ system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00%
system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 245
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 51.032653
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 46.821080
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 22.902478
-system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 203 82.86% 82.86% | 35 14.29% 97.14% | 3 1.22% 98.37% | 3 1.22% 99.59% | 1 0.41% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 55.804082
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.356103
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.580698
+system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 127 51.84% 51.84% | 114 46.53% 98.37% | 2 0.82% 99.18% | 0 0.00% 99.18% | 0 0.00% 99.18% | 2 0.82% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 245
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 84
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 55.821429
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.772534
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 40.751129
-system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 73 86.90% 86.90% | 6 7.14% 94.05% | 4 4.76% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 54.107143
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 48.596564
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 27.751487
+system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 44 52.38% 52.38% | 36 42.86% 95.24% | 1 1.19% 96.43% | 2 2.38% 98.81% | 1 1.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 84
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 297
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 62.306397
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 56.498895
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 36.624977
-system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 241 81.14% 81.14% | 46 15.49% 96.63% | 6 2.02% 98.65% | 0 0.00% 98.65% | 2 0.67% 99.33% | 2 0.67% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 65.121212
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 59.083052
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 34.625488
+system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 85 28.62% 28.62% | 202 68.01% 96.63% | 7 2.36% 98.99% | 0 0.00% 98.99% | 2 0.67% 99.66% | 1 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 297
system.ruby.Directory_Controller.GETX 626 0.00% 0.00%
system.ruby.Directory_Controller.PUTX 622 0.00% 0.00%