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-rw-r--r--tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt588
-rw-r--r--tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt646
2 files changed, 617 insertions, 617 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
index a15c23d57..c9524dba5 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000035 # Number of seconds simulated
-sim_ticks 35024500 # Number of ticks simulated
-final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 35022500 # Number of ticks simulated
+final_tick 35022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72507 # Simulator instruction rate (inst/s)
-host_op_rate 72491 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 396631772 # Simulator tick rate (ticks/s)
-host_mem_usage 236200 # Number of bytes of host memory used
+host_inst_rate 71946 # Simulator instruction rate (inst/s)
+host_op_rate 71929 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 393524726 # Simulator tick rate (ticks/s)
+host_mem_usage 237176 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
sim_insts 6400 # Number of instructions simulated
sim_ops 6400 # Number of ops (including micro ops) simulated
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu
system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory
system.physmem.num_reads::total 533 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 974002427 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 974002427 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 665172389 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 665172389 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 974002427 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 974002427 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 533 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 34926000 # Total gap between requests
+system.physmem.totGap 34924000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By
system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation
-system.physmem.totQLat 3928000 # Total ticks spent queuing
-system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3887500 # Total ticks spent queuing
+system.physmem.totMemAccLat 13881250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 7293.62 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 26043.62 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 974.00 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 974.00 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 7.61 # Data bus utilization in percentage
@@ -216,12 +216,12 @@ system.physmem.readRowHits 435 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 65527.20 # Average gap between requests
+system.physmem.avgGap 65523.45 # Average gap between requests
system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
system.physmem.memoryStateTime::REF 1040000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 30394500 # Time in different power states
+system.physmem.memoryStateTime::ACT 30393500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 257040 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 385560 # Energy for activate commands per rank (pJ)
@@ -234,66 +234,43 @@ system.physmem.writeEnergy::1 0 # En
system.physmem.refreshEnergy::0 2034240 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 2034240 # Energy for refresh commands per rank (pJ)
system.physmem.actBackEnergy::0 21425445 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 20168595 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 20164320 # Energy for active background per rank (pJ)
system.physmem.preBackEnergy::0 67500 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1170000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1173750 # Energy for precharge background per rank (pJ)
system.physmem.totalEnergy::0 26007075 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 25645770 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 25645245 # Total energy per rank (pJ)
system.physmem.averagePower::0 827.295718 # Core power per rank (mW)
-system.physmem.averagePower::1 815.802457 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 460 # Transaction distribution
-system.membus.trans_dist::ReadResp 460 # Transaction distribution
-system.membus.trans_dist::ReadExReq 73 # Transaction distribution
-system.membus.trans_dist::ReadExResp 73 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 533 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 533 # Request fanout histogram
-system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.8 # Layer utilization (%)
-system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 1959 # Number of BP lookups
-system.cpu.branchPred.condPredicted 1201 # Number of conditional branches predicted
+system.physmem.averagePower::1 815.785757 # Core power per rank (mW)
+system.cpu.branchPred.lookups 1972 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 1551 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 381 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 385 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 24.564797 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 1368 # DTB read hits
+system.cpu.dtb.read_hits 1370 # DTB read hits
system.cpu.dtb.read_misses 11 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 1379 # DTB read accesses
+system.cpu.dtb.read_accesses 1381 # DTB read accesses
system.cpu.dtb.write_hits 884 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 887 # DTB write accesses
-system.cpu.dtb.data_hits 2252 # DTB hits
+system.cpu.dtb.data_hits 2254 # DTB hits
system.cpu.dtb.data_misses 14 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 2266 # DTB accesses
-system.cpu.itb.fetch_hits 2630 # ITB hits
+system.cpu.dtb.data_accesses 2268 # DTB accesses
+system.cpu.itb.fetch_hits 2642 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 2647 # ITB accesses
+system.cpu.itb.fetch_accesses 2659 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -307,68 +284,180 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
-system.cpu.numCycles 70049 # number of cpu cycles simulated
+system.cpu.numCycles 70045 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 6400 # Number of instructions committed
system.cpu.committedOps 6400 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 10.945156 # CPI: cycles per instruction
-system.cpu.ipc 0.091365 # IPC: instructions per cycle
-system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 10.944531 # CPI: cycles per instruction
+system.cpu.ipc 0.091370 # IPC: instructions per cycle
+system.cpu.tickCycles 12615 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 57430 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 104.047628 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst 104.047628 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.025402 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.025402 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst 1233 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst 1973 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst 1973 # number of overall hits
+system.cpu.dcache.overall_hits::total 1973 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
+system.cpu.dcache.overall_misses::total 227 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7703250 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8679250 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8679250 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 16382500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 16382500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 16382500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 16382500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst 1335 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst 2200 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst 2200 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076404 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.103182 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.103182 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75522.058824 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69434 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 69434 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 72169.603524 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72169.603524 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 72169.603524 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7131000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5128000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5128000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12259000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12259000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12259000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12259000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.071910 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076818 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74281.250000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70246.575342 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70246.575342 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72538.461538 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 72538.461538 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 176.126032 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -383,62 +472,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365
system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id
@@ -459,14 +520,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 533 #
system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses
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system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses)
@@ -483,14 +544,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998127
system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 # miss rate for overall accesses
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@@ -507,14 +568,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533
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@@ -523,126 +584,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127
system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56415.103189 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56415.103189 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 4559 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 4559 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst 1228 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1228 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst 740 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.inst 1968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst 1968 # number of overall hits
-system.cpu.dcache.overall_hits::total 1968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst 102 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst 125 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.inst 227 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses
-system.cpu.dcache.overall_misses::total 227 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 16424000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst 1330 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1330 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2195 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2195 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.076692 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.076692 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.144509 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 72352.422907 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 52 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 58 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 58 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 96 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 73 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst 169 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 12285000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.072180 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.072180 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 460 # Transaction distribution
+system.membus.trans_dist::ReadResp 460 # Transaction distribution
+system.membus.trans_dist::ReadExReq 73 # Transaction distribution
+system.membus.trans_dist::ReadExResp 73 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 533 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 533 # Request fanout histogram
+system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 4967250 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 14.2 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
index cff801d36..0513960dd 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt
@@ -1,13 +1,13 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 18662000 # Number of ticks simulated
-final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 18733500 # Number of ticks simulated
+final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 40123 # Simulator instruction rate (inst/s)
-host_op_rate 40110 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 289474844 # Simulator tick rate (ticks/s)
-host_mem_usage 234892 # Number of bytes of host memory used
+host_inst_rate 41421 # Simulator instruction rate (inst/s)
+host_op_rate 41407 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 299977624 # Simulator tick rate (ticks/s)
+host_mem_usage 235900 # Number of bytes of host memory used
host_seconds 0.06 # Real time elapsed on the host
sim_insts 2585 # Number of instructions simulated
sim_ops 2585 # Number of ops (including micro ops) simulated
@@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 14272 # Nu
system.physmem.bytes_inst_read::total 14272 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 308 # Number of read requests responded to by this memory
system.physmem.num_reads::total 308 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1056264066 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1056264066 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 764762619 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 764762619 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1056264066 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1056264066 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1052232631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1052232631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 308 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue
@@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 18580000 # Total gap between requests
+system.physmem.totGap 18651500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -182,118 +182,95 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 44 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 411.636364 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 270.438338 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 322.932860 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 11 25.00% 25.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 7 15.91% 40.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 4 9.09% 50.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3 6.82% 56.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 6 13.64% 70.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5 11.36% 81.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation
-system.physmem.totQLat 1719250 # Total ticks spent queuing
-system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation
+system.physmem.totQLat 1958750 # Total ticks spent queuing
+system.physmem.totMemAccLat 7733750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 6359.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 25109.58 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 8.25 # Data bus utilization in percentage
-system.physmem.busUtilRead 8.25 # Data bus utilization in percentage for reads
+system.physmem.busUtil 8.22 # Data bus utilization in percentage
+system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 256 # Number of row buffer hits during reads
+system.physmem.readRowHits 257 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 60324.68 # Average gap between requests
-system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined
+system.physmem.avgGap 60556.82 # Average gap between requests
+system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 15500 # Time in different power states
system.physmem.memoryStateTime::REF 520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15310750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 90720 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::0 83160 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 219240 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 49500 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::0 45375 # Energy for precharge commands per rank (pJ)
system.physmem.preEnergy::1 119625 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 795600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 1302600 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 1294800 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 1017120 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 1017120 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 10733670 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::0 10790100 # Energy for active background per rank (pJ)
system.physmem.actBackEnergy::1 10507095 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 84000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::0 34500 # Energy for precharge background per rank (pJ)
system.physmem.preBackEnergy::1 282750 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 12770610 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 13448430 # Total energy per rank (pJ)
-system.physmem.averagePower::0 806.607295 # Core power per rank (mW)
-system.physmem.averagePower::1 849.419233 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 281 # Transaction distribution
-system.membus.trans_dist::ReadResp 281 # Transaction distribution
-system.membus.trans_dist::ReadExReq 27 # Transaction distribution
-system.membus.trans_dist::ReadExResp 27 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 308 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 308 # Request fanout histogram
-system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 15.4 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 786 # Number of BP lookups
-system.cpu.branchPred.condPredicted 393 # Number of conditional branches predicted
+system.physmem.totalEnergy::0 12765855 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 13440630 # Total energy per rank (pJ)
+system.physmem.averagePower::0 806.306964 # Core power per rank (mW)
+system.physmem.averagePower::1 848.926575 # Core power per rank (mW)
+system.cpu.branchPred.lookups 793 # Number of BP lookups
+system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 558 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups
system.cpu.branchPred.BTBHits 58 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 10.394265 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 508 # DTB read hits
+system.cpu.dtb.read_hits 509 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_accesses 515 # DTB read accesses
+system.cpu.dtb.read_accesses 516 # DTB read accesses
system.cpu.dtb.write_hits 307 # DTB write hits
system.cpu.dtb.write_misses 6 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 313 # DTB write accesses
-system.cpu.dtb.data_hits 815 # DTB hits
+system.cpu.dtb.data_hits 816 # DTB hits
system.cpu.dtb.data_misses 13 # DTB misses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_accesses 828 # DTB accesses
-system.cpu.itb.fetch_hits 962 # ITB hits
+system.cpu.dtb.data_accesses 829 # DTB accesses
+system.cpu.itb.fetch_hits 974 # ITB hits
system.cpu.itb.fetch_misses 13 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 975 # ITB accesses
+system.cpu.itb.fetch_accesses 987 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
@@ -307,68 +284,180 @@ system.cpu.itb.data_misses 0 # DT
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4 # Number of system calls
-system.cpu.numCycles 37324 # number of cpu cycles simulated
+system.cpu.numCycles 37467 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 2585 # Number of instructions committed
system.cpu.committedOps 2585 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 635 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
-system.cpu.cpi 14.438685 # CPI: cycles per instruction
-system.cpu.ipc 0.069258 # IPC: instructions per cycle
-system.cpu.tickCycles 5337 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 31987 # Total number of cycles that the object has spent stopped
+system.cpu.cpi 14.494004 # CPI: cycles per instruction
+system.cpu.ipc 0.068994 # IPC: instructions per cycle
+system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 0 # number of replacements
+system.cpu.dcache.tags.tagsinuse 48.468521 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.inst 48.468521 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.inst 0.011833 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.011833 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.inst 441 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 441 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.inst 251 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 251 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.inst 692 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 692 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.inst 692 # number of overall hits
+system.cpu.dcache.overall_hits::total 692 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.inst 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.inst 43 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.inst 104 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.inst 104 # number of overall misses
+system.cpu.dcache.overall_misses::total 104 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.inst 4636500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4636500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.inst 3517500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3517500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.inst 8154000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 8154000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.inst 8154000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 8154000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.inst 502 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.inst 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.inst 796 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 796 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.inst 796 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 796 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.121514 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.121514 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.146259 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.146259 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.inst 0.130653 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.inst 0.130653 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 76008.196721 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 76008.196721 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 81802.325581 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 81802.325581 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 78403.846154 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.inst 78403.846154 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 78403.846154 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
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+system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
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+system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 58 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
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+system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4302500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4302500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2086500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2086500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6389000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6389000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6389000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6389000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.115538 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.106784 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74181.034483 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74181.034483 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 77277.777778 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77277.777778 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 75164.705882 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 75164.705882 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 0 # number of replacements
-system.cpu.icache.tags.tagsinuse 118.813999 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 739 # Total number of references to valid blocks.
+system.cpu.icache.tags.tagsinuse 118.426247 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3.313901 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 118.813999 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.058015 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.058015 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst 118.426247 # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst 0.057825 # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total 0.057825 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 2147 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 2147 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 739 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 739 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 739 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 739 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 739 # number of overall hits
-system.cpu.icache.overall_hits::total 739 # number of overall hits
+system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 2171 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits
+system.cpu.icache.overall_hits::total 751 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses
system.cpu.icache.overall_misses::total 223 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 15454750 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 15454750 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 15454750 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 15454750 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 15454750 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 15454750 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 962 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 962 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 962 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 962 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 962 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 962 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.231809 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.231809 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.231809 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.231809 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.231809 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.231809 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69303.811659 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 69303.811659 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 69303.811659 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 69303.811659 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 69303.811659 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 69303.811659 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15431500 # number of ReadReq miss cycles
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -383,62 +472,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223
system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
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-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
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system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id
@@ -453,14 +514,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 308 #
system.cpu.l2cache.demand_misses::total 308 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 308 # number of overall misses
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system.cpu.l2cache.ReadReq_accesses::cpu.inst 281 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses::cpu.inst 27 # number of ReadExReq accesses(hits+misses)
@@ -477,14 +538,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1
system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -501,14 +562,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 308
system.cpu.l2cache.demand_mshr_misses::total 308 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 308 # number of overall MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses
@@ -517,126 +578,65 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1
system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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-system.cpu.dcache.demand_miss_rate::total 0.131479 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst 0.131479 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.131479 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75926.229508 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 75926.229508 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69895.348837 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 69895.348837 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 73432.692308 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 73432.692308 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 73432.692308 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 73432.692308 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 16 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 16 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst 19 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst 19 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 19 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 58 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 27 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst 85 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst 85 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4297000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4297000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 1830750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1830750 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 6127750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6127750 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 6127750 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6127750 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.116700 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.116700 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.107459 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.107459 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.107459 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74086.206897 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74086.206897 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 67805.555556 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67805.555556 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72091.176471 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 72091.176471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72091.176471 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 72091.176471 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 27 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 0 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 137000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
+system.membus.trans_dist::ReadReq 281 # Transaction distribution
+system.membus.trans_dist::ReadResp 281 # Transaction distribution
+system.membus.trans_dist::ReadExReq 27 # Transaction distribution
+system.membus.trans_dist::ReadExResp 27 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 308 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 308 # Request fanout histogram
+system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
+system.membus.respLayer1.occupancy 2868500 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 15.3 # Layer utilization (%)
---------- End Simulation Statistics ----------