summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout')
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout16
1 files changed, 9 insertions, 7 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 9a11b77d6..09918a5fe 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,13 +1,15 @@
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2014 12:08:08
-gem5 started Jan 23 2014 17:05:52
-gem5 executing on u200540-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
+gem5 compiled Jun 21 2014 11:22:42
+gem5 started Jun 21 2014 11:25:19
+gem5 executing on phenom
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
- 0: system.cpu.checker.isa: ISA system set to: 0 0x5d826c0
- 0: system.cpu.isa: ISA system set to: 0 0x5d826c0
+ 0: system.cpu.checker.isa: ISA system set to: 0 0x54ee6d0
+ 0: system.cpu.isa: ISA system set to: 0 0x54ee6d0
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 16981000 because target called exit()
+Exiting @ tick 16786000 because target called exit()