diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | 1198 |
1 files changed, 599 insertions, 599 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 17ad77afe..94ce3d081 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17307500 # Number of ticks simulated -final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17398000 # Number of ticks simulated +final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36602 # Simulator instruction rate (inst/s) -host_op_rate 42863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137949898 # Simulator tick rate (ticks/s) -host_mem_usage 239992 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5377 # Number of ops (including micro ops) simulated +host_inst_rate 32773 # Simulator instruction rate (inst/s) +host_op_rate 38377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 124135140 # Simulator tick rate (ticks/s) +host_mem_usage 303432 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +sim_insts 4592 # Number of instructions simulated +sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory +system.physmem.bytes_read::total 25344 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 396 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 90 # Per bank write bursts -system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts system.physmem.perBankRdBursts::4 18 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17240500 # Total gap between requests +system.physmem.totGap 17318000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3336500 # Total ticks spent queuing -system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation +system.physmem.totQLat 3886750 # Total ticks spent queuing +system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.47 # Data bus utilization in percentage -system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.38 # Data bus utilization in percentage +system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43426.95 # Average gap between requests -system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43732.32 # Average gap between requests +system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ) -system.physmem_0.averagePower 909.263856 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.226907 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ) -system.physmem_1.averagePower 806.611620 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states +system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) +system.physmem_1.averagePower 804.955945 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2634 # Number of BP lookups -system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups -system.cpu.branchPred.BTBHits 781 # Number of BTB hits +system.cpu.branchPred.lookups 2567 # Number of BP lookups +system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups +system.cpu.branchPred.BTBHits 778 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,7 +377,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5390 # number of cpu cycles simulated +system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -496,273 +496,273 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34616 # number of cpu cycles simulated +system.cpu.numCycles 34797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2141 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2057 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2103 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2012 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 42 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8345 # Type of FU issued -system.cpu.iq.rate 0.241073 # Inst issue rate -system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15278 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8189 # Type of FU issued +system.cpu.iq.rate 0.235336 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3142 # number of memory reference insts executed -system.cpu.iew.exec_branches 1452 # Number of branches executed -system.cpu.iew.exec_stores 1232 # Number of stores executed -system.cpu.iew.exec_rate 0.232465 # Inst execution rate -system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7583 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3567 # num instructions producing a value -system.cpu.iew.wb_consumers 6985 # num instructions consuming a value +system.cpu.iew.exec_nop 9 # number of nop insts executed +system.cpu.iew.exec_refs 3070 # number of memory reference insts executed +system.cpu.iew.exec_branches 1431 # Number of branches executed +system.cpu.iew.exec_stores 1229 # Number of stores executed +system.cpu.iew.exec_rate 0.225824 # Inst execution rate +system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7454 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3520 # num instructions producing a value +system.cpu.iew.wb_consumers 6887 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back +system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4592 # Number of instructions committed +system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1965 # Number of memory references committed system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1007 # Number of branches committed +system.cpu.commit.branches 1008 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction @@ -771,122 +771,122 @@ system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Cl system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22770 # The number of ROB reads -system.cpu.rob.rob_writes 21679 # The number of ROB writes -system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads -system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7923 # number of integer regfile reads -system.cpu.int_regfile_writes 4408 # number of integer regfile writes +system.cpu.commit.op_class_0::total 5378 # Class of committed instruction +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22302 # The number of ROB reads +system.cpu.rob.rob_writes 21197 # The number of ROB writes +system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4592 # Number of Instructions Simulated +system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7744 # number of integer regfile reads +system.cpu.int_regfile_writes 4257 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28677 # number of cc regfile reads -system.cpu.cc_regfile_writes 3298 # number of cc regfile writes -system.cpu.misc_regfile_reads 3185 # number of misc regfile reads +system.cpu.cc_regfile_reads 28092 # number of cc regfile reads +system.cpu.cc_regfile_writes 3277 # number of cc regfile writes +system.cpu.misc_regfile_reads 3176 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits -system.cpu.dcache.overall_hits::total 2156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits +system.cpu.dcache.overall_hits::total 2137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses -system.cpu.dcache.overall_misses::total 513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses +system.cpu.dcache.overall_misses::total 497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,202 +895,202 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4420 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4420 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1659 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1659 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1659 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1659 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1659 # number of overall hits -system.cpu.icache.overall_hits::total 1659 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 404 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 404 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 404 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 404 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 404 # number of overall misses -system.cpu.icache.overall_misses::total 404 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28289500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28289500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28289500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28289500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28289500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28289500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195831 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195831 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195831 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195831 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195831 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195831 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70023.514851 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70023.514851 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70023.514851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70023.514851 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 361 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4307 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits +system.cpu.icache.overall_hits::total 1613 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses +system.cpu.icache.overall_misses::total 394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 110 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 110 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 110 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 110 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21612000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21612000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21612000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21612000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21612000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21612000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142511 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142511 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142511 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73510.204082 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73510.204082 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22179000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145989 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145989 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145989 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.994376 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.073007 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.852442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.141935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001408 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005707 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.074126 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.998881 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004275 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010803 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3916 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3916 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits system.cpu.l2cache.overall_hits::total 39 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 359 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 401 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21127500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6646750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27774250 # number of ReadReq miss cycles +system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses +system.cpu.l2cache.overall_misses::total 401 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21706000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6539250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28245250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21127500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9993250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31120750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21127500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9993250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31120750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_miss_latency::cpu.inst 21706000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9885750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31591750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21706000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9885750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31591750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 293 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.800000 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.941980 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.790476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.902010 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76548.913043 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79127.976190 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77150.694444 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.850340 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77414.800995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77414.800995 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1106,62 +1106,62 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 79 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 354 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 120 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1170,40 +1170,40 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.trans_dist::ReadReq 354 # Transaction distribution +system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::samples 396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 396 # Request fanout histogram +system.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |