diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 9149a2fa0..e232e499c 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000017 # Nu sim_ticks 17232500 # Number of ticks simulated final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74741 # Simulator instruction rate (inst/s) -host_op_rate 87520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 280399381 # Simulator tick rate (ticks/s) -host_mem_usage 309668 # Number of bytes of host memory used +host_inst_rate 78702 # Simulator instruction rate (inst/s) +host_op_rate 92158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 295258113 # Simulator tick rate (ticks/s) +host_mem_usage 310332 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2837 # Number of BP lookups system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect @@ -264,6 +266,7 @@ system.cpu.branchPred.indirectHits 14 # Nu system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -293,6 +296,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -322,6 +326,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -351,6 +356,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -381,9 +387,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,6 +421,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -442,6 +451,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -471,6 +481,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -500,6 +511,7 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses +system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 34466 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -793,6 +805,7 @@ system.cpu.cc_regfile_reads 27801 # nu system.cpu.cc_regfile_writes 3276 # number of cc regfile writes system.cpu.misc_regfile_reads 2978 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. @@ -808,6 +821,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits @@ -920,6 +934,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. @@ -935,6 +950,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 123 system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses system.cpu.icache.tags.data_accesses 4216 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits @@ -1009,6 +1025,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. @@ -1026,6 +1043,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1166,6 +1184,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1196,6 +1215,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 441000 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution |