diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker')
3 files changed, 522 insertions, 503 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 69978e99c..ff436d924 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -352,7 +352,7 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -756,7 +756,7 @@ pipelined=false [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -888,7 +888,7 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl @@ -1005,6 +1005,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -1016,7 +1017,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -1024,29 +1025,36 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=DRAMCtrl -IDD0=0.075000 +IDD0=0.055000 IDD02=0.000000 -IDD2N=0.050000 +IDD2N=0.032000 IDD2N2=0.000000 IDD2P0=0.000000 IDD2P02=0.000000 -IDD2P1=0.000000 +IDD2P1=0.032000 IDD2P12=0.000000 -IDD3N=0.057000 +IDD3N=0.038000 IDD3N2=0.000000 IDD3P0=0.000000 IDD3P02=0.000000 -IDD3P1=0.000000 +IDD3P1=0.038000 IDD3P12=0.000000 -IDD4R=0.187000 +IDD4R=0.157000 IDD4R2=0.000000 -IDD4W=0.165000 +IDD4W=0.125000 IDD4W2=0.000000 -IDD5=0.220000 +IDD5=0.235000 IDD52=0.000000 -IDD6=0.000000 +IDD6=0.020000 IDD62=0.000000 VDD=1.500000 VDD2=0.000000 @@ -1066,6 +1074,7 @@ devices_per_rank=8 dll=true eventq_index=0 in_addr_map=true +kvm_map=true max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 @@ -1075,7 +1084,7 @@ p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 page_policy=open_adaptive power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 @@ -1097,9 +1106,9 @@ tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 -tXP=0 +tXP=6000 tXPDLL=0 -tXS=0 +tXS=270000 tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 09d4a73db..e9b447feb 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 1 2016 17:10:05 -gem5 started Aug 1 2016 17:27:25 -gem5 executing on e108600-lin, pid 12519 +gem5 compiled Oct 11 2016 00:00:58 +gem5 started Oct 13 2016 20:42:58 +gem5 executing on e108600-lin, pid 17311 command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 17232500 because target called exit() +Exiting @ tick 18422500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 012901358..bf47005a8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17458500 # Number of ticks simulated -final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 18422500 # Number of ticks simulated +final_tick 18422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52261 # Simulator instruction rate (inst/s) -host_op_rate 61197 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 198636102 # Simulator tick rate (ticks/s) -host_mem_usage 269760 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 65137 # Simulator instruction rate (inst/s) +host_op_rate 76274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 261240377 # Simulator tick rate (ticks/s) +host_mem_usage 268360 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 958827521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 420355543 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1379183064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 958827521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 958827521 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 958827521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 420355543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1379183064 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17373000 # Total gap between requests +system.physmem.totGap 18337000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,86 +187,96 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation -system.physmem.totQLat 3455750 # Total ticks spent queuing -system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 407.864407 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 273.934367 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 344.219630 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 16.95% 16.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 28.81% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 13.56% 59.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.86% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.39% 76.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 5.08% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 5.08% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation +system.physmem.totQLat 5196750 # Total ticks spent queuing +system.physmem.totMemAccLat 12640500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13090.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31840.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1379.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1379.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.37 # Data bus utilization in percentage -system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.77 # Data bus utilization in percentage +system.physmem.busUtilRead 10.77 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.90 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43760.71 # Average gap between requests +system.physmem.avgGap 46188.92 # Average gap between requests system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) -system.physmem_0.averagePower 906.309806 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3077430 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 36000 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5255970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 20640 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 12170160 # Total energy per rank (pJ) +system.physmem_0.averagePower 660.613923 # Core power per rank (mW) +system.physmem_0.totalIdleTime 11420000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 0 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 53500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6303750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 11521750 # Time in different power states +system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 749700 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.416167 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states +system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1466040 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 65760 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6124080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 616800 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 10487985 # Total energy per rank (pJ) +system.physmem_1.averagePower 569.303026 # Core power per rank (mW) +system.physmem_1.totalIdleTime 14986000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2836 # Number of BP lookups -system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted +system.physmem_1.memoryStateTime::SREF 0 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1605250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2751250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 13430000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2844 # Number of BP lookups +system.cpu.branchPred.condPredicted 1749 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2408 # Number of BTB lookups +system.cpu.branchPred.BTBHits 867 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 36.004983 # BTB Hit Percentage system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. +system.cpu.branchPred.indirectLookups 266 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 253 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +306,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +336,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +366,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,11 +397,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,7 +431,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,7 +461,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,7 +491,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,237 +521,237 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 34918 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 18422500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 36846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7661 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12314 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2844 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1194 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5108 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.CacheLines 1962 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 13535 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.094422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.458272 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10839 80.08% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 1.95% 82.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 185 1.37% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.51% 84.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 2.09% 87.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 398 2.94% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.03% 90.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.28% 92.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1050 7.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2143 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13535 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077186 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.334202 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6279 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2146 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12150 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 6511 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 826 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2033 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1361 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 178 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1169 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11641 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52345 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12355 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6147 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2200 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. +system.cpu.rename.skidInsts 446 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2197 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1543 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10169 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8096 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4835 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13535 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.598153 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.329974 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10320 76.25% 76.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1163 8.59% 84.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 763 5.64% 90.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 482 3.56% 94.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 344 2.54% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 273 2.02% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 120 0.89% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 60 0.44% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13535 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.12% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.12% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 66 44.90% 51.02% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 72 48.98% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5023 62.04% 62.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1876 23.17% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1187 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8100 # Type of FU issued -system.cpu.iq.rate 0.231972 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8096 # Type of FU issued +system.cpu.iq.rate 0.219725 # Inst issue rate +system.cpu.iq.fu_busy_cnt 147 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018157 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29820 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14935 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7404 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8200 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1173 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1170 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 605 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 31 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 29 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 696 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10222 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 131 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2197 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1543 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 356 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7806 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 290 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2920 # number of memory reference insts executed -system.cpu.iew.exec_branches 1492 # Number of branches executed -system.cpu.iew.exec_stores 1147 # Number of stores executed -system.cpu.iew.exec_rate 0.223581 # Inst execution rate -system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7431 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3502 # num instructions producing a value -system.cpu.iew.wb_consumers 6830 # num instructions consuming a value -system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2921 # number of memory reference insts executed +system.cpu.iew.exec_branches 1491 # Number of branches executed +system.cpu.iew.exec_stores 1153 # Number of stores executed +system.cpu.iew.exec_rate 0.211855 # Inst execution rate +system.cpu.iew.wb_sent 7533 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7436 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3503 # num instructions producing a value +system.cpu.iew.wb_consumers 6835 # num instructions consuming a value +system.cpu.iew.wb_rate 0.201813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512509 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4843 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12682 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.424066 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266213 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10636 83.87% 83.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 879 6.93% 90.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 416 3.28% 94.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 218 1.72% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 111 0.88% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 54 0.43% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12682 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -788,52 +798,52 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22352 # The number of ROB reads -system.cpu.rob.rob_writes 21294 # The number of ROB writes +system.cpu.rob.rob_reads 22637 # The number of ROB reads +system.cpu.rob.rob_writes 21308 # The number of ROB writes system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 23311 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7649 # number of integer regfile reads -system.cpu.int_regfile_writes 4266 # number of integer regfile writes +system.cpu.cpi 8.023955 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.023955 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124627 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124627 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7656 # number of integer regfile reads +system.cpu.int_regfile_writes 4268 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads system.cpu.cc_regfile_reads 27780 # number of cc regfile reads system.cpu.cc_regfile_writes 3273 # number of cc regfile writes -system.cpu.misc_regfile_reads 2976 # number of misc regfile reads +system.cpu.misc_regfile_reads 2974 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.014551 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2093 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.238095 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.014551 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021488 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021488 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5335 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5335 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits -system.cpu.dcache.overall_hits::total 2075 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2072 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2072 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2072 # number of overall hits +system.cpu.dcache.overall_hits::total 2072 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses @@ -844,53 +854,53 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11345000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11345000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24463500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24463500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35808500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35808500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35808500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35808500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1658 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1658 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2571 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2571 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2571 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2571 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110374 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110374 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.194088 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.194088 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.194088 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.194088 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61994.535519 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61994.535519 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77416.139241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77416.139241 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 78000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 78000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71760.521042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71760.521042 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits @@ -910,140 +920,140 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7355500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3668000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3668000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11023500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11023500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11023500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11023500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063329 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063329 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057176 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057176 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057176 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70052.380952 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74989.795918 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74989.795918 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.507349 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.507349 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073002 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073002 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4214 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits -system.cpu.icache.overall_hits::total 1576 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses -system.cpu.icache.overall_misses::total 384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4218 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4218 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 385 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 385 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 385 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 385 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 385 # number of overall misses +system.cpu.icache.overall_misses::total 385 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28997500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28997500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28997500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28997500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28997500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28997500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1962 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1962 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1962 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1962 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1962 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196228 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196228 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196228 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196228 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196228 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196228 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75318.181818 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75318.181818 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75318.181818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75318.181818 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75318.181818 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 493 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 98.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 90 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 90 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 90 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 90 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 90 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 91 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 91 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 91 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 91 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 91 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 91 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23482000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23482000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23482000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23482000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149847 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149847 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149847 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149847 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79870.748299 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79870.748299 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79870.748299 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79870.748299 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 214.408451 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.281348 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 74.127103 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004281 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002262 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1068,18 +1078,18 @@ system.cpu.l2cache.demand_misses::total 403 # nu system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3603000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3603000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22833000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22833000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22833000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10564000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33397000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22833000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10564000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33397000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) @@ -1106,18 +1116,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.913832 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82728.260870 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82728.260870 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81894.117647 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81894.117647 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82870.967742 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82728.260870 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83181.102362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82870.967742 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1142,18 +1152,18 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20073000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20073000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5729500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5729500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8912500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28985500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20073000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8912500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28985500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses @@ -1166,25 +1176,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72728.260870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72728.260870 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72525.316456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72525.316456 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72728.260870 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73657.024793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73011.335013 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1211,18 +1221,18 @@ system.cpu.toL2Bus.snoop_fanout::min_value 0 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 18422500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1243,9 +1253,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.0 # Layer utilization (%) +system.membus.reqLayer0.occupancy 486500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2098750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |