diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker')
3 files changed, 72 insertions, 21 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 34353ab5e..d0f59b4b6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -551,9 +551,8 @@ cpu_side=system.cpu.toL2Bus.master[0] mem_side=system.membus.slave[1] [system.cpu.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false @@ -584,9 +583,8 @@ system=system uid=100 [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=1000 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index a7713ed58..9fb63a7a7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:17:37 -gem5 started May 8 2012 16:20:46 -gem5 executing on piton +gem5 compiled Jun 4 2012 12:14:06 +gem5 started Jun 4 2012 17:23:41 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 7aa4a6157..ea50665b2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000010 # Nu sim_ticks 10303500 # Number of ticks simulated final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20985 # Simulator instruction rate (inst/s) -host_op_rate 26178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46991642 # Simulator tick rate (ticks/s) -host_mem_usage 229632 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 43907 # Simulator instruction rate (inst/s) +host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 98312554 # Simulator tick rate (ticks/s) +host_mem_usage 230064 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25664 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 401 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory +system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 401 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -410,11 +417,17 @@ system.cpu.icache.demand_accesses::total 2031 # nu system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,11 +455,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 9833500 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use @@ -502,15 +521,25 @@ system.cpu.dcache.demand_accesses::total 2879 # nu system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,13 +575,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 4693500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use @@ -609,18 +646,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -659,18 +704,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |