diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 678 |
1 files changed, 339 insertions, 339 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 307f14079..bc5d2d1fc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 20302000 # Number of ticks simulated final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10367 # Simulator instruction rate (inst/s) -host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45828431 # Simulator tick rate (ticks/s) -host_mem_usage 248616 # Number of bytes of host memory used -host_seconds 0.44 # Real time elapsed on the host +host_inst_rate 93691 # Simulator instruction rate (inst/s) +host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 414022055 # Simulator tick rate (ticks/s) +host_mem_usage 265936 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -205,12 +205,12 @@ system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # By system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6124000 # Total ticks spent queuing -system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6135000 # Total ticks spent queuing +system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s @@ -232,28 +232,28 @@ system.physmem_0.preEnergy 170775 # En system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank +system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::SREF 0 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) +system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) +system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) @@ -267,12 +267,12 @@ system.physmem_1.memoryStateTime::ACT 2792000 # Ti system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups +system.cpu.branchPred.BTBHits 446 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -405,80 +405,80 @@ system.cpu.pwrStateResidencyTicks::ON 20302000 # Cu system.cpu.numCycles 40605 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle +system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5174 # Number of cycles decode is running +system.cpu.decode.RunCycles 5171 # Number of cycles decode is running system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4185 # Number of cycles rename is running +system.cpu.rename.RunCycles 4182 # Number of cycles rename is running system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename +system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made +system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle @@ -487,147 +487,147 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7222 # Type of FU issued -system.cpu.iq.rate 0.177860 # Inst issue rate +system.cpu.iq.FU_type_0::total 7227 # Type of FU issued +system.cpu.iq.rate 0.177983 # Inst issue rate system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads +system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2442 # number of memory reference insts executed -system.cpu.iew.exec_branches 1297 # Number of branches executed +system.cpu.iew.exec_refs 2443 # number of memory reference insts executed +system.cpu.iew.exec_branches 1299 # Number of branches executed system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.167836 # Inst execution rate -system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6631 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5426 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back +system.cpu.iew.exec_rate 0.168033 # Inst execution rate +system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6639 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2983 # num instructions producing a value +system.cpu.iew.wb_consumers 5430 # num instructions consuming a value +system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle @@ -635,7 +635,7 @@ system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,33 +686,33 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23226 # The number of ROB reads -system.cpu.rob.rob_writes 16730 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23224 # The number of ROB reads +system.cpu.rob.rob_writes 16731 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6765 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.int_regfile_reads 6850 # number of integer regfile reads +system.cpu.int_regfile_writes 3795 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24202 # number of cc regfile reads -system.cpu.cc_regfile_writes 2924 # number of cc regfile writes -system.cpu.misc_regfile_reads 2558 # number of misc regfile reads +system.cpu.cc_regfile_reads 24229 # number of cc regfile reads +system.cpu.cc_regfile_writes 2927 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id @@ -720,38 +720,38 @@ system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits -system.cpu.dcache.overall_hits::total 1906 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits +system.cpu.dcache.overall_hits::total 1903 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses +system.cpu.dcache.overall_misses::total 361 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -764,26 +764,26 @@ system.cpu.dcache.demand_accesses::cpu.data 2264 # system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,16 +792,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -810,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses @@ -826,67 +826,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses +system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8095 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits -system.cpu.icache.overall_hits::total 3536 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses -system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits +system.cpu.icache.overall_hits::total 3532 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses +system.cpu.icache.overall_misses::total 366 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked @@ -895,36 +895,36 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -934,16 +934,16 @@ system.cpu.l2cache.prefetcher.pfRemovedFull 0 # system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -981,16 +981,16 @@ system.cpu.l2cache.overall_misses::cpu.data 133 # system.cpu.l2cache.overall_misses::total 424 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) @@ -1019,16 +1019,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1064,17 +1064,17 @@ system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766 system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses @@ -1094,17 +1094,17 @@ system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338 system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. @@ -1173,7 +1173,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 445 # Request fanout histogram system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 11.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |