diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/o3-timing')
4 files changed, 0 insertions, 2158 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini deleted file mode 100644 index 72771fa1e..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ /dev/null @@ -1,962 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=DerivO3CPU -children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload -LFSTSize=1024 -LQEntries=16 -LSQCheckLoads=true -LSQDepCheckShift=0 -SQEntries=16 -SSITSize=1024 -activity=0 -backComSize=5 -branchPred=system.cpu.branchPred -cacheStorePorts=200 -checker=Null -clk_domain=system.cpu_clk_domain -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=2 -decodeWidth=3 -default_p_state=UNDEFINED -dispatchWidth=6 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fetchBufferSize=16 -fetchQueueSize=32 -fetchToDecodeDelay=3 -fetchTrapLatency=1 -fetchWidth=3 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -issueToExecuteDelay=1 -issueWidth=8 -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -needsTSO=false -numIQEntries=32 -numPhysCCRegs=640 -numPhysFloatRegs=192 -numPhysIntRegs=128 -numROBEntries=40 -numRobs=1 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=1 -renameToROBDelay=1 -renameWidth=3 -simpoint_start_insts= -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -socket_id=0 -squashWidth=8 -store_set_clear_period=250000 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbWidth=8 -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BiModeBP -BTBEntries=2048 -BTBTagSize=18 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -indirectHashGHR=true -indirectHashTargets=true -indirectPathLength=3 -indirectSets=256 -indirectTagSize=16 -indirectWays=2 -instShiftAmt=2 -numThreads=1 -useIndirect=true - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=6 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=8 -write_buffers=16 -writeback_clean=true -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=2 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 -eventq_index=0 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -eventq_index=0 -opClass=IntAlu -opLat=1 -pipelined=true - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 opList2 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -eventq_index=0 -opClass=IntMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -eventq_index=0 -opClass=IntDiv -opLat=12 -pipelined=false - -[system.cpu.fuPool.FUList1.opList2] -type=OpDesc -eventq_index=0 -opClass=IprAccess -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -eventq_index=0 -opClass=MemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemRead -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 -count=1 -eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -opClass=MemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -opClass=FloatMemWrite -opLat=2 -pipelined=true - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 -count=2 -eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 - -[system.cpu.fuPool.FUList4.opList00] -type=OpDesc -eventq_index=0 -opClass=SimdAdd -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList01] -type=OpDesc -eventq_index=0 -opClass=SimdAddAcc -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList02] -type=OpDesc -eventq_index=0 -opClass=SimdAlu -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList03] -type=OpDesc -eventq_index=0 -opClass=SimdCmp -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList04] -type=OpDesc -eventq_index=0 -opClass=SimdCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList05] -type=OpDesc -eventq_index=0 -opClass=SimdMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList06] -type=OpDesc -eventq_index=0 -opClass=SimdMult -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList07] -type=OpDesc -eventq_index=0 -opClass=SimdMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList08] -type=OpDesc -eventq_index=0 -opClass=SimdShift -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList09] -type=OpDesc -eventq_index=0 -opClass=SimdShiftAcc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList10] -type=OpDesc -eventq_index=0 -opClass=SimdSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList11] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList12] -type=OpDesc -eventq_index=0 -opClass=SimdFloatAlu -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList13] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCmp -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList14] -type=OpDesc -eventq_index=0 -opClass=SimdFloatCvt -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList15] -type=OpDesc -eventq_index=0 -opClass=SimdFloatDiv -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList16] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMisc -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList17] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMult -opLat=3 -pipelined=true - -[system.cpu.fuPool.FUList4.opList18] -type=OpDesc -eventq_index=0 -opClass=SimdFloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList19] -type=OpDesc -eventq_index=0 -opClass=SimdFloatSqrt -opLat=9 -pipelined=true - -[system.cpu.fuPool.FUList4.opList20] -type=OpDesc -eventq_index=0 -opClass=FloatAdd -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList21] -type=OpDesc -eventq_index=0 -opClass=FloatCmp -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList22] -type=OpDesc -eventq_index=0 -opClass=FloatCvt -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList23] -type=OpDesc -eventq_index=0 -opClass=FloatDiv -opLat=9 -pipelined=false - -[system.cpu.fuPool.FUList4.opList24] -type=OpDesc -eventq_index=0 -opClass=FloatSqrt -opLat=33 -pipelined=false - -[system.cpu.fuPool.FUList4.opList25] -type=OpDesc -eventq_index=0 -opClass=FloatMult -opLat=4 -pipelined=true - -[system.cpu.fuPool.FUList4.opList26] -type=OpDesc -eventq_index=0 -opClass=FloatMultAcc -opLat=5 -pipelined=true - -[system.cpu.fuPool.FUList4.opList27] -type=OpDesc -eventq_index=0 -opClass=FloatMisc -opLat=3 -pipelined=true - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=1 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=1 -sequential_access=false -size=32768 -system=system -tag_latency=1 -tags=system.cpu.icache.tags -tgts_per_mshr=8 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=1 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 -tag_latency=1 - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=prefetcher tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=16 -clk_domain=system.cpu_clk_domain -clusivity=mostly_excl -data_latency=12 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=true -prefetcher=system.cpu.l2cache.prefetcher -response_latency=12 -sequential_access=false -size=1048576 -system=system -tag_latency=12 -tags=system.cpu.l2cache.tags -tgts_per_mshr=8 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.prefetcher] -type=StridePrefetcher -cache_snoop=false -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -degree=8 -eventq_index=0 -latency=1 -max_conf=7 -min_conf=0 -on_data=true -on_inst=true -on_miss=false -on_read=true -on_write=true -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -queue_filter=true -queue_size=32 -queue_squash=true -start_conf=4 -sys=system -table_assoc=4 -table_sets=16 -tag_prefetch=true -thresh_conf=4 -use_master_id=true - -[system.cpu.l2cache.tags] -type=RandomRepl -assoc=16 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=12 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=1048576 -tag_latency=12 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=DRAMCtrl -IDD0=0.055000 -IDD02=0.000000 -IDD2N=0.032000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.032000 -IDD2P12=0.000000 -IDD3N=0.038000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.038000 -IDD3P12=0.000000 -IDD4R=0.157000 -IDD4R2=0.000000 -IDD4W=0.125000 -IDD4W2=0.000000 -IDD5=0.235000 -IDD52=0.000000 -IDD6=0.020000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaCoCh -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -device_bus_width=8 -device_rowbuffer_size=1024 -device_size=536870912 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -kvm_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -page_policy=open_adaptive -power_model=Null -range=0:134217727:0:0:0:0 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=6000 -tXPDLL=0 -tXS=270000 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr deleted file mode 100755 index 707fed98b..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout deleted file mode 100755 index 9ae67891c..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ /dev/null @@ -1,13 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 18:08:17 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55753 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing - -Global frequency set at 1000000000000 ticks per second -Hello world! -Exiting @ tick 20302000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt deleted file mode 100644 index f88830f40..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ /dev/null @@ -1,1179 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 -sim_ticks 20302000 -final_tick 20302000 -sim_freq 1000000000000 -host_inst_rate 45535 -host_op_rate 53318 -host_tick_rate 201173118 -host_mem_usage 277864 -host_seconds 0.10 -sim_insts 4592 -sim_ops 5378 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 -system.physmem.bytes_read::cpu.inst 18560 -system.physmem.bytes_read::cpu.data 8128 -system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 -system.physmem.bytes_read::total 28416 -system.physmem.bytes_inst_read::cpu.inst 18560 -system.physmem.bytes_inst_read::total 18560 -system.physmem.num_reads::cpu.inst 290 -system.physmem.num_reads::cpu.data 127 -system.physmem.num_reads::cpu.l2cache.prefetcher 27 -system.physmem.num_reads::total 444 -system.physmem.bw_read::cpu.inst 914195646 -system.physmem.bw_read::cpu.data 400354645 -system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 -system.physmem.bw_read::total 1399665058 -system.physmem.bw_inst_read::cpu.inst 914195646 -system.physmem.bw_inst_read::total 914195646 -system.physmem.bw_total::cpu.inst 914195646 -system.physmem.bw_total::cpu.data 400354645 -system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 -system.physmem.bw_total::total 1399665058 -system.physmem.readReqs 445 -system.physmem.writeReqs 0 -system.physmem.readBursts 445 -system.physmem.writeBursts 0 -system.physmem.bytesReadDRAM 28480 -system.physmem.bytesReadWrQ 0 -system.physmem.bytesWritten 0 -system.physmem.bytesReadSys 28480 -system.physmem.bytesWrittenSys 0 -system.physmem.servicedByWrQ 0 -system.physmem.mergedWrBursts 0 -system.physmem.neitherReadNorWriteReqs 0 -system.physmem.perBankRdBursts::0 103 -system.physmem.perBankRdBursts::1 48 -system.physmem.perBankRdBursts::2 19 -system.physmem.perBankRdBursts::3 45 -system.physmem.perBankRdBursts::4 19 -system.physmem.perBankRdBursts::5 37 -system.physmem.perBankRdBursts::6 46 -system.physmem.perBankRdBursts::7 10 -system.physmem.perBankRdBursts::8 4 -system.physmem.perBankRdBursts::9 8 -system.physmem.perBankRdBursts::10 27 -system.physmem.perBankRdBursts::11 47 -system.physmem.perBankRdBursts::12 17 -system.physmem.perBankRdBursts::13 8 -system.physmem.perBankRdBursts::14 0 -system.physmem.perBankRdBursts::15 7 -system.physmem.perBankWrBursts::0 0 -system.physmem.perBankWrBursts::1 0 -system.physmem.perBankWrBursts::2 0 -system.physmem.perBankWrBursts::3 0 -system.physmem.perBankWrBursts::4 0 -system.physmem.perBankWrBursts::5 0 -system.physmem.perBankWrBursts::6 0 -system.physmem.perBankWrBursts::7 0 -system.physmem.perBankWrBursts::8 0 -system.physmem.perBankWrBursts::9 0 -system.physmem.perBankWrBursts::10 0 -system.physmem.perBankWrBursts::11 0 -system.physmem.perBankWrBursts::12 0 -system.physmem.perBankWrBursts::13 0 -system.physmem.perBankWrBursts::14 0 -system.physmem.perBankWrBursts::15 0 -system.physmem.numRdRetry 0 -system.physmem.numWrRetry 0 -system.physmem.totGap 20260500 -system.physmem.readPktSize::0 0 -system.physmem.readPktSize::1 0 -system.physmem.readPktSize::2 0 -system.physmem.readPktSize::3 0 -system.physmem.readPktSize::4 0 -system.physmem.readPktSize::5 0 -system.physmem.readPktSize::6 445 -system.physmem.writePktSize::0 0 -system.physmem.writePktSize::1 0 -system.physmem.writePktSize::2 0 -system.physmem.writePktSize::3 0 -system.physmem.writePktSize::4 0 -system.physmem.writePktSize::5 0 -system.physmem.writePktSize::6 0 -system.physmem.rdQLenPdf::0 241 -system.physmem.rdQLenPdf::1 136 -system.physmem.rdQLenPdf::2 36 -system.physmem.rdQLenPdf::3 17 -system.physmem.rdQLenPdf::4 5 -system.physmem.rdQLenPdf::5 2 -system.physmem.rdQLenPdf::6 2 -system.physmem.rdQLenPdf::7 2 -system.physmem.rdQLenPdf::8 2 -system.physmem.rdQLenPdf::9 2 -system.physmem.rdQLenPdf::10 0 -system.physmem.rdQLenPdf::11 0 -system.physmem.rdQLenPdf::12 0 -system.physmem.rdQLenPdf::13 0 -system.physmem.rdQLenPdf::14 0 -system.physmem.rdQLenPdf::15 0 -system.physmem.rdQLenPdf::16 0 -system.physmem.rdQLenPdf::17 0 -system.physmem.rdQLenPdf::18 0 -system.physmem.rdQLenPdf::19 0 -system.physmem.rdQLenPdf::20 0 -system.physmem.rdQLenPdf::21 0 -system.physmem.rdQLenPdf::22 0 -system.physmem.rdQLenPdf::23 0 -system.physmem.rdQLenPdf::24 0 -system.physmem.rdQLenPdf::25 0 -system.physmem.rdQLenPdf::26 0 -system.physmem.rdQLenPdf::27 0 -system.physmem.rdQLenPdf::28 0 -system.physmem.rdQLenPdf::29 0 -system.physmem.rdQLenPdf::30 0 -system.physmem.rdQLenPdf::31 0 -system.physmem.wrQLenPdf::0 0 -system.physmem.wrQLenPdf::1 0 -system.physmem.wrQLenPdf::2 0 -system.physmem.wrQLenPdf::3 0 -system.physmem.wrQLenPdf::4 0 -system.physmem.wrQLenPdf::5 0 -system.physmem.wrQLenPdf::6 0 -system.physmem.wrQLenPdf::7 0 -system.physmem.wrQLenPdf::8 0 -system.physmem.wrQLenPdf::9 0 -system.physmem.wrQLenPdf::10 0 -system.physmem.wrQLenPdf::11 0 -system.physmem.wrQLenPdf::12 0 -system.physmem.wrQLenPdf::13 0 -system.physmem.wrQLenPdf::14 0 -system.physmem.wrQLenPdf::15 0 -system.physmem.wrQLenPdf::16 0 -system.physmem.wrQLenPdf::17 0 -system.physmem.wrQLenPdf::18 0 -system.physmem.wrQLenPdf::19 0 -system.physmem.wrQLenPdf::20 0 -system.physmem.wrQLenPdf::21 0 -system.physmem.wrQLenPdf::22 0 -system.physmem.wrQLenPdf::23 0 -system.physmem.wrQLenPdf::24 0 -system.physmem.wrQLenPdf::25 0 -system.physmem.wrQLenPdf::26 0 -system.physmem.wrQLenPdf::27 0 -system.physmem.wrQLenPdf::28 0 -system.physmem.wrQLenPdf::29 0 -system.physmem.wrQLenPdf::30 0 -system.physmem.wrQLenPdf::31 0 -system.physmem.wrQLenPdf::32 0 -system.physmem.wrQLenPdf::33 0 -system.physmem.wrQLenPdf::34 0 -system.physmem.wrQLenPdf::35 0 -system.physmem.wrQLenPdf::36 0 -system.physmem.wrQLenPdf::37 0 -system.physmem.wrQLenPdf::38 0 -system.physmem.wrQLenPdf::39 0 -system.physmem.wrQLenPdf::40 0 -system.physmem.wrQLenPdf::41 0 -system.physmem.wrQLenPdf::42 0 -system.physmem.wrQLenPdf::43 0 -system.physmem.wrQLenPdf::44 0 -system.physmem.wrQLenPdf::45 0 -system.physmem.wrQLenPdf::46 0 -system.physmem.wrQLenPdf::47 0 -system.physmem.wrQLenPdf::48 0 -system.physmem.wrQLenPdf::49 0 -system.physmem.wrQLenPdf::50 0 -system.physmem.wrQLenPdf::51 0 -system.physmem.wrQLenPdf::52 0 -system.physmem.wrQLenPdf::53 0 -system.physmem.wrQLenPdf::54 0 -system.physmem.wrQLenPdf::55 0 -system.physmem.wrQLenPdf::56 0 -system.physmem.wrQLenPdf::57 0 -system.physmem.wrQLenPdf::58 0 -system.physmem.wrQLenPdf::59 0 -system.physmem.wrQLenPdf::60 0 -system.physmem.wrQLenPdf::61 0 -system.physmem.wrQLenPdf::62 0 -system.physmem.wrQLenPdf::63 0 -system.physmem.bytesPerActivate::samples 62 -system.physmem.bytesPerActivate::mean 435.612903 -system.physmem.bytesPerActivate::gmean 295.844737 -system.physmem.bytesPerActivate::stdev 352.802892 -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% -system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% -system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% -system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% -system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% -system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% -system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% -system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% -system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% -system.physmem.bytesPerActivate::total 62 -system.physmem.totQLat 6135000 -system.physmem.totMemAccLat 14478750 -system.physmem.totBusLat 2225000 -system.physmem.avgQLat 13786.52 -system.physmem.avgBusLat 5000.00 -system.physmem.avgMemAccLat 32536.52 -system.physmem.avgRdBW 1402.82 -system.physmem.avgWrBW 0.00 -system.physmem.avgRdBWSys 1402.82 -system.physmem.avgWrBWSys 0.00 -system.physmem.peakBW 12800.00 -system.physmem.busUtil 10.96 -system.physmem.busUtilRead 10.96 -system.physmem.busUtilWrite 0.00 -system.physmem.avgRdQLen 1.85 -system.physmem.avgWrQLen 0.00 -system.physmem.readRowHits 373 -system.physmem.writeRowHits 0 -system.physmem.readRowHitRate 83.82 -system.physmem.writeRowHitRate nan -system.physmem.avgGap 45529.21 -system.physmem.pageHitRate 83.82 -system.physmem_0.actEnergy 349860 -system.physmem_0.preEnergy 170775 -system.physmem_0.readEnergy 2334780 -system.physmem_0.writeEnergy 0 -system.physmem_0.refreshEnergy 1229280.000000 -system.physmem_0.actBackEnergy 3562500 -system.physmem_0.preBackEnergy 28800 -system.physmem_0.actPowerDownEnergy 5660100 -system.physmem_0.prePowerDownEnergy 960 -system.physmem_0.selfRefreshEnergy 0 -system.physmem_0.totalEnergy 13337055 -system.physmem_0.averagePower 656.916882 -system.physmem_0.totalIdleTime 12261000 -system.physmem_0.memoryStateTime::IDLE 19000 -system.physmem_0.memoryStateTime::REF 520000 -system.physmem_0.memoryStateTime::SREF 0 -system.physmem_0.memoryStateTime::PRE_PDN 2500 -system.physmem_0.memoryStateTime::ACT 7351250 -system.physmem_0.memoryStateTime::ACT_PDN 12409250 -system.physmem_1.actEnergy 164220 -system.physmem_1.preEnergy 64515 -system.physmem_1.readEnergy 842520 -system.physmem_1.writeEnergy 0 -system.physmem_1.refreshEnergy 1229280.000000 -system.physmem_1.actBackEnergy 1478010 -system.physmem_1.preBackEnergy 68640 -system.physmem_1.actPowerDownEnergy 7415130 -system.physmem_1.prePowerDownEnergy 238560 -system.physmem_1.selfRefreshEnergy 0 -system.physmem_1.totalEnergy 11500875 -system.physmem_1.averagePower 566.475803 -system.physmem_1.totalIdleTime 16880000 -system.physmem_1.memoryStateTime::IDLE 110000 -system.physmem_1.memoryStateTime::REF 520000 -system.physmem_1.memoryStateTime::SREF 0 -system.physmem_1.memoryStateTime::PRE_PDN 620500 -system.physmem_1.memoryStateTime::ACT 2792000 -system.physmem_1.memoryStateTime::ACT_PDN 16259500 -system.pwrStateResidencyTicks::UNDEFINED 20302000 -system.cpu.branchPred.lookups 2438 -system.cpu.branchPred.condPredicted 1441 -system.cpu.branchPred.condIncorrect 523 -system.cpu.branchPred.BTBLookups 913 -system.cpu.branchPred.BTBHits 446 -system.cpu.branchPred.BTBCorrect 0 -system.cpu.branchPred.BTBHitPct 48.849945 -system.cpu.branchPred.usedRAS 286 -system.cpu.branchPred.RASInCorrect 57 -system.cpu.branchPred.indirectLookups 163 -system.cpu.branchPred.indirectHits 13 -system.cpu.branchPred.indirectMisses 150 -system.cpu.branchPredindirectMispredicted 59 -system.cpu_clk_domain.clock 500 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 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1.08% 98.72% -system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% -system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% -system.cpu.commit.committed_per_cycle::min_value 0 -system.cpu.commit.committed_per_cycle::max_value 8 -system.cpu.commit.committed_per_cycle::total 15346 -system.cpu.commit.committedInsts 4592 -system.cpu.commit.committedOps 5378 -system.cpu.commit.swp_count 0 -system.cpu.commit.refs 1965 -system.cpu.commit.loads 1027 -system.cpu.commit.membars 12 -system.cpu.commit.branches 1008 -system.cpu.commit.fp_insts 16 -system.cpu.commit.int_insts 4624 -system.cpu.commit.function_calls 82 -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% 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-system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 -system.cpu.toL2Bus.pkt_count::total 930 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 -system.cpu.toL2Bus.pkt_size::total 31168 -system.cpu.toL2Bus.snoops 69 -system.cpu.toL2Bus.snoopTraffic 0 -system.cpu.toL2Bus.snoop_fanout::samples 512 -system.cpu.toL2Bus.snoop_fanout::mean 0.134766 -system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% -system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% -system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 2 -system.cpu.toL2Bus.snoop_fanout::total 512 -system.cpu.toL2Bus.reqLayer0.occupancy 289000 -system.cpu.toL2Bus.reqLayer0.utilization 1.4 -system.cpu.toL2Bus.respLayer0.occupancy 448999 -system.cpu.toL2Bus.respLayer0.utilization 2.2 -system.cpu.toL2Bus.respLayer1.occupancy 216995 -system.cpu.toL2Bus.respLayer1.utilization 1.1 -system.membus.snoop_filter.tot_requests 445 -system.membus.snoop_filter.hit_single_requests 35 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 -system.membus.trans_dist::ReadResp 414 -system.membus.trans_dist::ReadExReq 30 -system.membus.trans_dist::ReadExResp 30 -system.membus.trans_dist::ReadSharedReq 415 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 -system.membus.pkt_count::total 889 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 -system.membus.pkt_size::total 28416 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 445 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 445 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 445 -system.membus.reqLayer0.occupancy 554444 -system.membus.reqLayer0.utilization 2.7 -system.membus.respLayer1.occupancy 2338250 -system.membus.respLayer1.utilization 11.5 - ----------- End Simulation Statistics ---------- |