summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt21
1 files changed, 17 insertions, 4 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 12cffc971..c4cb1f552 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 555825 # Simulator instruction rate (inst/s)
-host_op_rate 650110 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 325439975 # Simulator tick rate (ticks/s)
-host_mem_usage 298640 # Number of bytes of host memory used
+host_inst_rate 569364 # Simulator instruction rate (inst/s)
+host_op_rate 666035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 333433301 # Simulator tick rate (ticks/s)
+host_mem_usage 299296 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
system.physmem.bytes_read::total 22911 # Number of bytes read from this memory
@@ -35,7 +36,9 @@ system.physmem.bw_write::total 1353617811 # Wr
system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -65,6 +68,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -94,6 +98,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT
system.cpu.checker.dtb.hits 0 # DTB hits
system.cpu.checker.dtb.misses 0 # DTB misses
system.cpu.checker.dtb.accesses 0 # DTB accesses
+system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -123,6 +128,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.itb.walker.walks 0 # Table walker walks requested
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -153,9 +159,11 @@ system.cpu.checker.itb.hits 0 # DT
system.cpu.checker.itb.misses 0 # DTB misses
system.cpu.checker.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
+system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states
system.cpu.checker.numCycles 0 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -185,6 +193,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks 0 # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -214,6 +223,7 @@ system.cpu.dtb.inst_accesses 0 # IT
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -243,6 +253,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks 0 # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
@@ -272,6 +283,7 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states
system.cpu.numCycles 5391 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
@@ -332,6 +344,7 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 5391 # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 5597 # Transaction distribution
system.membus.trans_dist::ReadResp 5608 # Transaction distribution
system.membus.trans_dist::WriteReq 913 # Transaction distribution