diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker')
4 files changed, 404 insertions, 400 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index be532b0c0..3b9285ab6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -131,6 +132,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=false @@ -200,8 +202,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -212,8 +212,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -340,8 +338,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -352,8 +348,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -414,7 +408,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -423,14 +417,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -454,6 +449,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -465,7 +461,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -473,6 +469,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -481,6 +484,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -488,7 +492,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr index 2b0e974b5..d46032821 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a4f08df89..6f0847911 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:49:47 -gem5 executing on e108600-lin, pid 23301 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54232 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index cf15c6ad1..d2c8b968b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,384 +1,384 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 707147 # Simulator instruction rate (inst/s) -host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 413753949 # Simulator tick rate (ticks/s) -host_mem_usage 259056 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 0 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 413531 +host_op_rate 483368 +host_tick_rate 241807981 +host_mem_usage 270560 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 +system.physmem.bytes_inst_read::total 18420 +system.physmem.bytes_written::cpu.data 3648 +system.physmem.bytes_written::total 3648 +system.physmem.num_reads::cpu.inst 4605 +system.physmem.num_reads::cpu.data 1003 +system.physmem.num_reads::total 5608 +system.physmem.num_writes::cpu.data 924 +system.physmem.num_writes::total 924 +system.physmem.bw_read::cpu.inst 6834879406 +system.physmem.bw_read::cpu.data 1666419295 +system.physmem.bw_read::total 8501298701 +system.physmem.bw_inst_read::cpu.inst 6834879406 +system.physmem.bw_inst_read::total 6834879406 +system.physmem.bw_write::cpu.data 1353617811 +system.physmem.bw_write::total 1353617811 +system.physmem.bw_total::cpu.inst 6834879406 +system.physmem.bw_total::cpu.data 3020037106 +system.physmem.bw_total::total 9854916512 +system.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu_clk_domain.clock 500 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.checker.dtb.walker.walks 0 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+system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4592 +system.cpu.committedOps 5378 +system.cpu.num_int_alu_accesses 4624 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 203 +system.cpu.num_conditional_control_insts 722 +system.cpu.num_int_insts 4624 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 7572 +system.cpu.num_int_register_writes 2728 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 16175 +system.cpu.num_cc_register_writes 2432 +system.cpu.num_mem_refs 1965 +system.cpu.num_load_insts 1027 +system.cpu.num_store_insts 938 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5391 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1008 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3419 63.42% 63.42% +system.cpu.op_class::IntMult 4 0.07% 63.49% +system.cpu.op_class::IntDiv 0 0.00% 63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- |