diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker')
4 files changed, 0 insertions, 903 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini deleted file mode 100644 index 3b9285ab6..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ /dev/null @@ -1,502 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=checker dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload -branchPred=Null -checker=system.cpu.checker -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.dstage2_mmu -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -istage2_mmu=system.cpu.istage2_mmu -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.checker] -type=DummyChecker -children=dstage2_mmu dtb isa istage2_mmu itb tracer -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=-1 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dstage2_mmu=system.cpu.checker.dstage2_mmu -dtb=system.cpu.checker.dtb -eventq_index=0 -exitOnError=false -function_trace=false -function_trace_start=0 -interrupts= -isa=system.cpu.checker.isa -istage2_mmu=system.cpu.checker.istage2_mmu -itb=system.cpu.checker.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.checker.tracer -updateOnError=false -warnOnlyOnLoadError=true -workload=system.cpu.workload - -[system.cpu.checker.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.checker.dtb - -[system.cpu.checker.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.checker.dstage2_mmu.stage2_tlb.walker - -[system.cpu.checker.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.checker.dtb.walker - -[system.cpu.checker.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.checker.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.checker.itb - -[system.cpu.checker.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.checker.istage2_mmu.stage2_tlb.walker - -[system.cpu.checker.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.checker.itb.walker - -[system.cpu.checker.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.checker.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.dstage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.dtb - -[system.cpu.dstage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.dstage2_mmu.stage2_tlb.walker - -[system.cpu.dstage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.dtb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=ArmInterrupts -eventq_index=0 - -[system.cpu.isa] -type=ArmISA -decoderFlavour=Generic -eventq_index=0 -fpsid=1090793632 -id_aa64afr0_el1=0 -id_aa64afr1_el1=0 -id_aa64dfr0_el1=1052678 -id_aa64dfr1_el1=0 -id_aa64isar0_el1=0 -id_aa64isar1_el1=0 -id_aa64mmfr0_el1=15728642 -id_aa64mmfr1_el1=0 -id_isar0=34607377 -id_isar1=34677009 -id_isar2=555950401 -id_isar3=17899825 -id_isar4=268501314 -id_isar5=0 -id_mmfr0=270536963 -id_mmfr1=0 -id_mmfr2=19070976 -id_mmfr3=34611729 -midr=1091551472 -pmu=Null -system=system - -[system.cpu.istage2_mmu] -type=ArmStage2MMU -children=stage2_tlb -eventq_index=0 -stage2_tlb=system.cpu.istage2_mmu.stage2_tlb -sys=system -tlb=system.cpu.itb - -[system.cpu.istage2_mmu.stage2_tlb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=true -size=32 -walker=system.cpu.istage2_mmu.stage2_tlb.walker - -[system.cpu.istage2_mmu.stage2_tlb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=true -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system - -[system.cpu.itb] -type=ArmTLB -children=walker -eventq_index=0 -is_stage2=false -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=ArmTableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -is_stage2=false -num_squash_per_cycle=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sys=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr deleted file mode 100755 index d46032821..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ /dev/null @@ -1,4 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout deleted file mode 100755 index 6f0847911..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ /dev/null @@ -1,13 +0,0 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 17:55:48 -gem5 started Apr 3 2017 17:56:13 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54232 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker - -Global frequency set at 1000000000000 ticks per second -Hello world! -Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt deleted file mode 100644 index d2c8b968b..000000000 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ /dev/null @@ -1,384 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 -sim_ticks 2695000 -final_tick 2695000 -sim_freq 1000000000000 -host_inst_rate 413531 -host_op_rate 483368 -host_tick_rate 241807981 -host_mem_usage 270560 -host_seconds 0.01 -sim_insts 4592 -sim_ops 5378 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 -system.physmem.bytes_read::cpu.inst 18420 -system.physmem.bytes_read::cpu.data 4491 -system.physmem.bytes_read::total 22911 -system.physmem.bytes_inst_read::cpu.inst 18420 -system.physmem.bytes_inst_read::total 18420 -system.physmem.bytes_written::cpu.data 3648 -system.physmem.bytes_written::total 3648 -system.physmem.num_reads::cpu.inst 4605 -system.physmem.num_reads::cpu.data 1003 -system.physmem.num_reads::total 5608 -system.physmem.num_writes::cpu.data 924 -system.physmem.num_writes::total 924 -system.physmem.bw_read::cpu.inst 6834879406 -system.physmem.bw_read::cpu.data 1666419295 -system.physmem.bw_read::total 8501298701 -system.physmem.bw_inst_read::cpu.inst 6834879406 -system.physmem.bw_inst_read::total 6834879406 -system.physmem.bw_write::cpu.data 1353617811 -system.physmem.bw_write::total 1353617811 -system.physmem.bw_total::cpu.inst 6834879406 -system.physmem.bw_total::cpu.data 3020037106 -system.physmem.bw_total::total 9854916512 -system.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu_clk_domain.clock 500 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.checker.dtb.walker.walks 0 -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 -system.cpu.checker.dtb.inst_hits 0 -system.cpu.checker.dtb.inst_misses 0 -system.cpu.checker.dtb.read_hits 0 -system.cpu.checker.dtb.read_misses 0 -system.cpu.checker.dtb.write_hits 0 -system.cpu.checker.dtb.write_misses 0 -system.cpu.checker.dtb.flush_tlb 0 -system.cpu.checker.dtb.flush_tlb_mva 0 -system.cpu.checker.dtb.flush_tlb_mva_asid 0 -system.cpu.checker.dtb.flush_tlb_asid 0 -system.cpu.checker.dtb.flush_entries 0 -system.cpu.checker.dtb.align_faults 0 -system.cpu.checker.dtb.prefetch_faults 0 -system.cpu.checker.dtb.domain_faults 0 -system.cpu.checker.dtb.perms_faults 0 -system.cpu.checker.dtb.read_accesses 0 -system.cpu.checker.dtb.write_accesses 0 -system.cpu.checker.dtb.inst_accesses 0 -system.cpu.checker.dtb.hits 0 -system.cpu.checker.dtb.misses 0 -system.cpu.checker.dtb.accesses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.checker.itb.walker.walks 0 -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 -system.cpu.checker.itb.inst_hits 0 -system.cpu.checker.itb.inst_misses 0 -system.cpu.checker.itb.read_hits 0 -system.cpu.checker.itb.read_misses 0 -system.cpu.checker.itb.write_hits 0 -system.cpu.checker.itb.write_misses 0 -system.cpu.checker.itb.flush_tlb 0 -system.cpu.checker.itb.flush_tlb_mva 0 -system.cpu.checker.itb.flush_tlb_mva_asid 0 -system.cpu.checker.itb.flush_tlb_asid 0 -system.cpu.checker.itb.flush_entries 0 -system.cpu.checker.itb.align_faults 0 -system.cpu.checker.itb.prefetch_faults 0 -system.cpu.checker.itb.domain_faults 0 -system.cpu.checker.itb.perms_faults 0 -system.cpu.checker.itb.read_accesses 0 -system.cpu.checker.itb.write_accesses 0 -system.cpu.checker.itb.inst_accesses 0 -system.cpu.checker.itb.hits 0 -system.cpu.checker.itb.misses 0 -system.cpu.checker.itb.accesses 0 -system.cpu.workload.numSyscalls 13 -system.cpu.checker.pwrStateResidencyTicks::ON 2695000 -system.cpu.checker.numCycles 0 -system.cpu.checker.numWorkItemsStarted 0 -system.cpu.checker.numWorkItemsCompleted 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.dstage2_mmu.stage2_tlb.hits 0 -system.cpu.dstage2_mmu.stage2_tlb.misses 0 -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.dtb.walker.walks 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.dtb.walker.walkRequestOrigin::total 0 -system.cpu.dtb.inst_hits 0 -system.cpu.dtb.inst_misses 0 -system.cpu.dtb.read_hits 0 -system.cpu.dtb.read_misses 0 -system.cpu.dtb.write_hits 0 -system.cpu.dtb.write_misses 0 -system.cpu.dtb.flush_tlb 0 -system.cpu.dtb.flush_tlb_mva 0 -system.cpu.dtb.flush_tlb_mva_asid 0 -system.cpu.dtb.flush_tlb_asid 0 -system.cpu.dtb.flush_entries 0 -system.cpu.dtb.align_faults 0 -system.cpu.dtb.prefetch_faults 0 -system.cpu.dtb.domain_faults 0 -system.cpu.dtb.perms_faults 0 -system.cpu.dtb.read_accesses 0 -system.cpu.dtb.write_accesses 0 -system.cpu.dtb.inst_accesses 0 -system.cpu.dtb.hits 0 -system.cpu.dtb.misses 0 -system.cpu.dtb.accesses 0 -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 -system.cpu.istage2_mmu.stage2_tlb.hits 0 -system.cpu.istage2_mmu.stage2_tlb.misses 0 -system.cpu.istage2_mmu.stage2_tlb.accesses 0 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 -system.cpu.itb.walker.walks 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 -system.cpu.itb.walker.walkRequestOrigin::total 0 -system.cpu.itb.inst_hits 0 -system.cpu.itb.inst_misses 0 -system.cpu.itb.read_hits 0 -system.cpu.itb.read_misses 0 -system.cpu.itb.write_hits 0 -system.cpu.itb.write_misses 0 -system.cpu.itb.flush_tlb 0 -system.cpu.itb.flush_tlb_mva 0 -system.cpu.itb.flush_tlb_mva_asid 0 -system.cpu.itb.flush_tlb_asid 0 -system.cpu.itb.flush_entries 0 -system.cpu.itb.align_faults 0 -system.cpu.itb.prefetch_faults 0 -system.cpu.itb.domain_faults 0 -system.cpu.itb.perms_faults 0 -system.cpu.itb.read_accesses 0 -system.cpu.itb.write_accesses 0 -system.cpu.itb.inst_accesses 0 -system.cpu.itb.hits 0 -system.cpu.itb.misses 0 -system.cpu.itb.accesses 0 -system.cpu.pwrStateResidencyTicks::ON 2695000 -system.cpu.numCycles 5391 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 4592 -system.cpu.committedOps 5378 -system.cpu.num_int_alu_accesses 4624 -system.cpu.num_fp_alu_accesses 16 -system.cpu.num_func_calls 203 -system.cpu.num_conditional_control_insts 722 -system.cpu.num_int_insts 4624 -system.cpu.num_fp_insts 16 -system.cpu.num_int_register_reads 7572 -system.cpu.num_int_register_writes 2728 -system.cpu.num_fp_register_reads 16 -system.cpu.num_fp_register_writes 0 -system.cpu.num_cc_register_reads 16175 -system.cpu.num_cc_register_writes 2432 -system.cpu.num_mem_refs 1965 -system.cpu.num_load_insts 1027 -system.cpu.num_store_insts 938 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 5391 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 1008 -system.cpu.op_class::No_OpClass 0 0.00% 0.00% -system.cpu.op_class::IntAlu 3419 63.42% 63.42% -system.cpu.op_class::IntMult 4 0.07% 63.49% -system.cpu.op_class::IntDiv 0 0.00% 63.49% -system.cpu.op_class::FloatAdd 0 0.00% 63.49% -system.cpu.op_class::FloatCmp 0 0.00% 63.49% -system.cpu.op_class::FloatCvt 0 0.00% 63.49% -system.cpu.op_class::FloatMult 0 0.00% 63.49% -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% -system.cpu.op_class::FloatDiv 0 0.00% 63.49% -system.cpu.op_class::FloatMisc 0 0.00% 63.49% -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% -system.cpu.op_class::SimdAdd 0 0.00% 63.49% -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% -system.cpu.op_class::SimdAlu 0 0.00% 63.49% -system.cpu.op_class::SimdCmp 0 0.00% 63.49% -system.cpu.op_class::SimdCvt 0 0.00% 63.49% -system.cpu.op_class::SimdMisc 0 0.00% 63.49% -system.cpu.op_class::SimdMult 0 0.00% 63.49% -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% -system.cpu.op_class::SimdShift 0 0.00% 63.49% -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% -system.cpu.op_class::MemRead 1027 19.05% 82.60% -system.cpu.op_class::MemWrite 922 17.10% 99.70% -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 5391 -system.membus.snoop_filter.tot_requests 0 -system.membus.snoop_filter.hit_single_requests 0 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 -system.membus.trans_dist::ReadReq 5597 -system.membus.trans_dist::ReadResp 5608 -system.membus.trans_dist::WriteReq 913 -system.membus.trans_dist::WriteResp 913 -system.membus.trans_dist::LoadLockedReq 11 -system.membus.trans_dist::StoreCondReq 11 -system.membus.trans_dist::StoreCondResp 11 -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 -system.membus.pkt_count::total 13064 -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 -system.membus.pkt_size::total 26559 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 6532 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 6532 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 6532 - ----------- End Simulation Statistics ---------- |