diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt | 242 |
1 files changed, 120 insertions, 122 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 872a056d2..8573f117d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815000 # Number of ticks simulated -final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25815500 # Number of ticks simulated +final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376930 # Simulator instruction rate (inst/s) -host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2127142386 # Simulator tick rate (ticks/s) -host_mem_usage 307352 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 263675 # Simulator instruction rate (inst/s) +host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1488783160 # Simulator tick rate (ticks/s) +host_mem_usage 306760 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51630 # number of cpu cycles simulated +system.cpu.numCycles 51631 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy @@ -440,17 +440,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,17 +503,17 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses @@ -525,17 +525,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -549,19 +549,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) @@ -588,9 +586,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- |