diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux/simple-timing')
3 files changed, 163 insertions, 156 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index bf0c1dcee..276d0c57a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -10,11 +10,12 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,11 +31,11 @@ system_port=system.membus.slave[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -42,6 +43,7 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -50,6 +52,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -61,23 +64,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=262144 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -91,7 +89,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -101,23 +99,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=131072 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -126,6 +119,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -134,7 +144,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -142,25 +152,20 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 +response_latency=20 size=2097152 -subblock_size=0 system=system -tgts_per_mshr=5 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -169,10 +174,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -187,7 +192,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=tests/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -211,7 +216,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 92bf5cdb0..58b706eaf 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,13 @@ +Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout +Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:07 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 19:43:25 +gem5 started Jan 23 2013 19:44:20 +gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 27316000 because target called exit() +Exiting @ tick 25969000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 059498d9f..2bce78814 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25969000 # Number of ticks simulated final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 147661 # Simulator instruction rate (inst/s) -host_op_rate 183366 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 839095918 # Simulator tick rate (ticks/s) -host_mem_usage 231680 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 66941 # Simulator instruction rate (inst/s) +host_op_rate 83151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380602116 # Simulator tick rate (ticks/s) +host_mem_usage 284140 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -170,112 +170,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use -system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits -system.cpu.dcache.overall_hits::total 1918 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. @@ -404,5 +298,111 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use +system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits +system.cpu.dcache.overall_hits::total 1918 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |