diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm/linux')
6 files changed, 1414 insertions, 1379 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index ebafeb85e..9ca1ab172 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30083500 # Number of ticks simulated -final_tick 30083500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30404500 # Number of ticks simulated +final_tick 30404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80042 # Simulator instruction rate (inst/s) -host_op_rate 93682 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 522670316 # Simulator tick rate (ticks/s) -host_mem_usage 264608 # Number of bytes of host memory used +host_inst_rate 82707 # Simulator instruction rate (inst/s) +host_op_rate 96800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 545818868 # Simulator tick rate (ticks/s) +host_mem_usage 269760 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory system.physmem.bytes_read::total 26944 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 648860671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 246779796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895640467 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 648860671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 648860671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 648860671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 246779796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895640467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 642010229 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 244174382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 886184611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 642010229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 642010229 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 642010229 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 244174382 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 886184611 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 29992500 # Total gap between requests +system.physmem.totGap 30312500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,71 +187,71 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 408.774194 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 287.809352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.256468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 27.42% 40.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 19.35% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.68% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.84% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 79.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.84% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.61% 85.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 2221000 # Total ticks spent queuing -system.physmem.totMemAccLat 10114750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 286.546821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.800854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.17% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 4.76% 79.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation +system.physmem.totQLat 2201250 # Total ticks spent queuing +system.physmem.totMemAccLat 10095000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5275.53 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5228.62 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24025.53 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 895.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23978.62 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 886.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 895.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 886.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.00 # Data bus utilization in percentage -system.physmem.busUtilRead 7.00 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 349 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71241.09 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined +system.physmem.avgGap 72001.19 # Average gap between requests +system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1965600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16103925 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20064615 # Total energy per rank (pJ) -system.physmem_0.averagePower 849.295873 # Core power per rank (mW) +system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.348875 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22845750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15554160 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 527250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18499935 # Total energy per rank (pJ) -system.physmem_1.averagePower 783.273247 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2015750 # Time in different power states +system.physmem_1.actBackEnergy 15442155 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 625500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18486180 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.690871 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2431750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22043250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21880250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 1968 # Number of BP lookups system.cpu.branchPred.condPredicted 1178 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 351 # Number of conditional branches incorrect @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 8 # Nu system.cpu.branchPred.indirectMisses 127 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 62 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,16 +387,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30083500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 60167 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 30404500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 60809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed system.cpu.discardedOps 1193 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.065581 # CPI: cycles per instruction -system.cpu.ipc 0.076537 # IPC: instructions per cycle +system.cpu.cpi 13.204995 # CPI: cycles per instruction +system.cpu.ipc 0.075729 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction @@ -432,25 +432,25 @@ system.cpu.op_class_0::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10719 # Number of cycles that the object actually ticked -system.cpu.idleCycles 49448 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 10721 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50088 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.478936 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.589882 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.478936 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021113 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021113 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.589882 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021140 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021140 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits @@ -471,14 +471,14 @@ system.cpu.dcache.demand_misses::cpu.data 176 # n system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6690500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6690500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5002500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5002500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11693000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11693000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11693000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11693000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6774500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6774500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5069500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5069500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 11844000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11844000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 11844000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11844000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -499,14 +499,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61380.733945 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61380.733945 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74664.179104 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74664.179104 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66437.500000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.500000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66437.500000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62151.376147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62151.376147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75664.179104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75664.179104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67295.454545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67295.454545 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67295.454545 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,14 +529,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6338000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3188000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3188000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9526000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9526000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9526000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9526000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3231000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3231000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9650000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9650000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9650000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -545,31 +545,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61533.980583 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61533.980583 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74139.534884 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65246.575342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65246.575342 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62320.388350 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75139.534884 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66095.890411 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66095.890411 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 161.834516 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 162.072741 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1963 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.096273 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.834516 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079021 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079021 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.072741 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079137 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079137 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4892 # Number of tag accesses system.cpu.icache.tags.data_accesses 4892 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1963 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1963 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1963 # number of demand (read+write) hits @@ -582,12 +582,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23678000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23678000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23678000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23678000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23678000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23678000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23964000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23964000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23964000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23964000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23964000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23964000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2285 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2285 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2285 # number of demand (read+write) accesses @@ -600,12 +600,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.140919 system.cpu.icache.demand_miss_rate::total 0.140919 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.140919 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.140919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73534.161491 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73534.161491 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73534.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73534.161491 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73534.161491 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74422.360248 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74422.360248 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74422.360248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74422.360248 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74422.360248 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -620,43 +620,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23356000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23356000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23356000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23356000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23642000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23642000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23642000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23642000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140919 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.140919 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140919 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.140919 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72534.161491 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72534.161491 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72534.161491 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72534.161491 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73422.360248 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73422.360248 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73422.360248 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73422.360248 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.879475 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 223.657376 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.111111 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.099762 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.746810 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.132665 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004722 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005978 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.975765 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 68.681611 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4189 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4189 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits @@ -681,18 +681,18 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3123500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22677500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22677500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5924000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 5924000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22677500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9047500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22677500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9047500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31725000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3166500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3166500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22963500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 22963500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6005000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6005000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22963500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9171500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32135000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22963500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9171500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32135000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) @@ -719,18 +719,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72639.534884 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74352.459016 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74352.459016 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 73135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 73135.802469 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73951.048951 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74352.459016 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72963.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73951.048951 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73639.534884 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75290.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75290.163934 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 74135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 74135.802469 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74906.759907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75290.163934 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73963.709677 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74906.759907 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -755,18 +755,18 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2693500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2693500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19627500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19627500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4648000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4648000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7341500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26969000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19627500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7341500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26969000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2736500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2736500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19913500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19913500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4721000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4721000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19913500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7457500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27371000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19913500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7457500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27371000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadCleanReq accesses @@ -779,25 +779,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62639.534884 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64352.459016 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64352.459016 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 63671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 63671.232877 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64352.459016 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63288.793103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64059.382423 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63639.534884 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65290.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65290.163934 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 64671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 64671.232877 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65290.163934 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64288.793103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65014.251781 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 472 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -829,7 +829,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 483000 # La system.cpu.toL2Bus.respLayer0.utilization 1.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30083500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 421 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 30404500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 378 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -852,7 +858,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 421 # Request fanout histogram system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2237750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 117199ea9..012901358 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17232500 # Number of ticks simulated -final_tick 17232500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17458500 # Number of ticks simulated +final_tick 17458500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74373 # Simulator instruction rate (inst/s) -host_op_rate 87086 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 279001739 # Simulator tick rate (ticks/s) -host_mem_usage 265896 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 52261 # Simulator instruction rate (inst/s) +host_op_rate 61197 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 198636102 # Simulator tick rate (ticks/s) +host_mem_usage 269760 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 17664 # Nu system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025039896 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 449383432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1474423328 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025039896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025039896 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025039896 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 449383432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1474423328 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1011770771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 443566171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1455336942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1011770771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1011770771 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1011770771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 443566171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1455336942 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17147000 # Total gap between requests +system.physmem.totGap 17373000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 207 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -187,78 +187,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 391.111111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 256.618090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.397843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 28.57% 49.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.11% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 9.52% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.35% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3287250 # Total ticks spent queuing -system.physmem.totMemAccLat 10731000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 61 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 398.688525 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 264.215339 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.944807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 19.67% 19.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15 24.59% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.75% 59.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.48% 70.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.92% 75.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.28% 78.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.28% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.28% 85.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61 # Bytes accessed per row activation +system.physmem.totQLat 3455750 # Total ticks spent queuing +system.physmem.totMemAccLat 10899500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8280.23 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8704.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27030.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1474.42 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27454.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1455.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1474.42 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1455.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.52 # Data bus utilization in percentage -system.physmem.busUtilRead 11.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.37 # Data bus utilization in percentage +system.physmem.busUtilRead 11.37 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43191.44 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43760.71 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14411520 # Total energy per rank (pJ) -system.physmem_0.averagePower 910.249171 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 69250 # Time in different power states +system.physmem_0.totalEnergy 14349150 # Total energy per rank (pJ) +system.physmem_0.averagePower 906.309806 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16107250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 764400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10407915 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 369750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12792885 # Total energy per rank (pJ) -system.physmem_1.averagePower 808.014211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 741250 # Time in different power states +system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 466500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12753765 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.416167 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 734500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14752750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14593500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2837 # Number of BP lookups +system.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2836 # Number of BP lookups system.cpu.branchPred.condPredicted 1744 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 464 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2401 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 36.026656 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 36.000000 # BTB Hit Percentage system.cpu.branchPred.usedRAS 314 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 265 # Number of indirect predictor lookups. @@ -266,7 +266,7 @@ system.cpu.branchPred.indirectHits 14 # Nu system.cpu.branchPred.indirectMisses 251 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -296,7 +296,7 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -326,7 +326,7 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 0 # DTB hits system.cpu.checker.dtb.misses 0 # DTB misses system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -356,7 +356,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.itb.walker.walks 0 # Table walker walks requested system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -387,11 +387,11 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states +system.cpu.checker.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,7 +421,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -451,7 +451,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,7 +481,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -511,66 +511,66 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 17232500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 34466 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 17458500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 34918 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7588 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12295 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2837 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1193 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4873 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 7601 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12293 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1192 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4902 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 977 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 246 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 248 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.120412 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.482171 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.116542 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.478893 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10520 79.62% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 264 2.00% 81.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 185 1.40% 83.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 203 1.54% 84.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 282 2.13% 86.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 396 3.00% 89.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 139 1.05% 90.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.31% 92.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1051 7.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10565 79.69% 79.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 264 1.99% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 184 1.39% 83.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 203 1.53% 84.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 282 2.13% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 396 2.99% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 139 1.05% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.30% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1051 7.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13213 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.082313 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.356728 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6291 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4311 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2142 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 13257 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.081219 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.352053 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6292 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4354 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2143 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 134 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 334 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 431 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12135 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12137 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 334 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6519 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 770 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2303 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2037 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11429 # Number of instructions processed by rename +system.cpu.rename.IdleCycles 6521 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 773 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2325 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2036 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11426 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 166 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 130 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1074 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11638 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52321 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12347 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 168 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1090 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11634 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52309 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12345 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6144 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6140 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 40 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 441 # count of insts added to the skid buffer @@ -578,109 +578,109 @@ system.cpu.memDep0.insertedLoads 2200 # Nu system.cpu.memDep0.insertedStores 1540 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10167 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10163 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4832 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12329 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8100 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4828 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13213 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.613260 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.341984 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13257 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.610998 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.340069 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9987 75.58% 75.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1172 8.87% 84.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 771 5.84% 90.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 475 3.59% 93.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 273 2.07% 98.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.92% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10033 75.68% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1170 8.83% 84.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 770 5.81% 90.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 479 3.61% 93.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 341 2.57% 96.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.07% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.91% 99.48% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 59 0.45% 99.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13213 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13257 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 6.21% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 44.83% 51.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 48.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 6.16% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 44.52% 50.68% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 72 49.32% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5027 62.04% 62.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.13% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.16% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1882 23.23% 85.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1184 14.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5026 62.05% 62.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.09% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1881 23.22% 85.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1183 14.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8103 # Type of FU issued -system.cpu.iq.rate 0.235101 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.017895 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29511 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14929 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7407 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8100 # Type of FU issued +system.cpu.iq.rate 0.231972 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018025 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29552 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14921 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7399 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 91 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8205 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8203 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 23 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -694,10 +694,10 @@ system.cpu.iew.lsq.thread0.rescheduledLoads 31 # system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 334 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 683 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 684 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10219 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 10215 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2200 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1540 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions @@ -707,41 +707,41 @@ system.cpu.iew.memOrderViolationEvents 19 # Nu system.cpu.iew.predictedTakenIncorrect 94 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 357 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7814 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1772 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 289 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 7807 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1773 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 293 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 2923 # number of memory reference insts executed +system.cpu.iew.exec_refs 2920 # number of memory reference insts executed system.cpu.iew.exec_branches 1492 # Number of branches executed -system.cpu.iew.exec_stores 1151 # Number of stores executed -system.cpu.iew.exec_rate 0.226716 # Inst execution rate -system.cpu.iew.wb_sent 7536 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7439 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3504 # num instructions producing a value -system.cpu.iew.wb_consumers 6831 # num instructions consuming a value -system.cpu.iew.wb_rate 0.215836 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.512956 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4840 # The number of squashed insts skipped by commit +system.cpu.iew.exec_stores 1147 # Number of stores executed +system.cpu.iew.exec_rate 0.223581 # Inst execution rate +system.cpu.iew.wb_sent 7528 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7431 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3502 # num instructions producing a value +system.cpu.iew.wb_consumers 6830 # num instructions consuming a value +system.cpu.iew.wb_rate 0.212813 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.512738 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4836 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 310 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12359 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.435148 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.280013 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.278209 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10307 83.40% 83.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 885 7.16% 90.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.40% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 217 1.76% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 108 0.87% 96.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 219 1.77% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.45% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.32% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10353 83.47% 83.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 884 7.13% 90.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.39% 93.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 217 1.75% 95.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 107 0.86% 96.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 220 1.77% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.44% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.31% 99.12% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 109 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12359 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -788,52 +788,52 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22311 # The number of ROB reads -system.cpu.rob.rob_writes 21303 # The number of ROB writes +system.cpu.rob.rob_reads 22352 # The number of ROB reads +system.cpu.rob.rob_writes 21294 # The number of ROB writes system.cpu.timesIdled 191 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21253 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 21661 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.505662 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.505662 # CPI: Total CPI of All Threads -system.cpu.ipc 0.133233 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.133233 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7659 # number of integer regfile reads -system.cpu.int_regfile_writes 4270 # number of integer regfile writes +system.cpu.cpi 7.604094 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.604094 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131508 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131508 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7649 # number of integer regfile reads +system.cpu.int_regfile_writes 4266 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 27801 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 2980 # number of misc regfile reads +system.cpu.cc_regfile_reads 27780 # number of cc regfile reads +system.cpu.cc_regfile_writes 3273 # number of cc regfile writes +system.cpu.misc_regfile_reads 2976 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 88.359063 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2095 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 88.222961 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2096 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.251701 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.258503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 88.359063 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021572 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021572 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 88.222961 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021539 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021539 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5339 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5339 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5341 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5341 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 1478 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1478 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2074 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2074 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2074 # number of overall hits -system.cpu.dcache.overall_hits::total 2074 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2075 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2075 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2075 # number of overall hits +system.cpu.dcache.overall_hits::total 2075 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 183 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 183 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses @@ -844,53 +844,53 @@ system.cpu.dcache.demand_misses::cpu.data 499 # n system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses system.cpu.dcache.overall_misses::total 499 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10736000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10736000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22555500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 142000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33291500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33291500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33291500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33291500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1660 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1660 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10847000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10847000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22859500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22859500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33706500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33706500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33706500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33706500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1661 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1661 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2573 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2573 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2573 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2573 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110241 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.110241 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2574 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2574 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2574 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2574 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.110175 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.110175 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.193937 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.193937 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.193937 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.193937 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58666.666667 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58666.666667 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71378.164557 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71378.164557 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 71000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 71000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66716.432866 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66716.432866 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66716.432866 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.193862 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.193862 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.193862 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.193862 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59273.224044 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59273.224044 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72340.189873 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72340.189873 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67548.096192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67548.096192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67548.096192 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 147 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 49 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits @@ -910,88 +910,88 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7020000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7020000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3398000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10418000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10418000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10418000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063253 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063253 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7089000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7089000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3440000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3440000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10529000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10529000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10529000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.063215 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.063215 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057132 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057132 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057132 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66857.142857 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66857.142857 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80904.761905 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057110 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057110 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057110 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67514.285714 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67514.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81904.761905 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71625.850340 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 71625.850340 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 150.405898 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.958367 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1576 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.363946 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.360544 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.405898 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073440 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073440 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.958367 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073222 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073222 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4216 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4216 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits -system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.tags.tag_accesses 4214 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4214 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 384 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 384 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 384 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 384 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 384 # number of overall misses system.cpu.icache.overall_misses::total 384 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26669500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26669500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26669500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26669500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26669500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26669500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195818 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195818 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195818 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195818 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195818 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69451.822917 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69451.822917 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69451.822917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69451.822917 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69451.822917 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 423 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 27225000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 27225000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 27225000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 27225000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 27225000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 27225000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195918 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195918 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195918 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195918 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195918 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195918 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70898.437500 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70898.437500 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70898.437500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70898.437500 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70898.437500 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 84.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 86.600000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 2 # number of writebacks system.cpu.icache.writebacks::total 2 # number of writebacks @@ -1007,43 +1007,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 294 system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21733500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21733500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21733500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21733500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21733500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21733500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149924 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.149924 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149924 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.149924 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73923.469388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73923.469388 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73923.469388 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73923.469388 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22193500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22193500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22193500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22193500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22193500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22193500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.150000 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.150000 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.150000 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.150000 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75488.095238 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75488.095238 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75488.095238 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75488.095238 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 187.999052 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 215.001500 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.098237 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.158865 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.840188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001429 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005737 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.723037 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 74.278463 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004295 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006561 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 200 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3933 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3933 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits @@ -1068,18 +1068,18 @@ system.cpu.l2cache.demand_misses::total 403 # nu system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 403 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3333000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21084500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21084500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6625500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6625500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21084500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9958500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31043000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21084500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9958500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31043000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3375000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3375000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21544500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 21544500 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6694500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 6694500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21544500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10069500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31614000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21544500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10069500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31614000 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) @@ -1106,18 +1106,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.913832 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.913832 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79357.142857 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76393.115942 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76393.115942 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77947.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77947.058824 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77029.776675 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76393.115942 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78413.385827 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77029.776675 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80357.142857 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 78059.782609 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 78059.782609 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78758.823529 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78758.823529 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78446.650124 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78059.782609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79287.401575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78446.650124 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1142,18 +1142,18 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2913000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18324500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18324500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5436000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5436000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18324500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8349000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26673500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18324500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8349000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26673500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2955000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2955000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 18784500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 18784500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5499000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18784500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8454000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27238500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18784500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8454000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27238500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadCleanReq accesses @@ -1166,25 +1166,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66393.115942 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66393.115942 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68810.126582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68810.126582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66393.115942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67187.657431 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68059.782609 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68059.782609 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69607.594937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69607.594937 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68059.782609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69867.768595 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68610.831234 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 443 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -1213,10 +1213,16 @@ system.cpu.toL2Bus.snoop_fanout::total 441 # Re system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 441000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 17232500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 397 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 17458500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution @@ -1239,7 +1245,7 @@ system.membus.snoop_fanout::max_value 0 # Re system.membus.snoop_fanout::total 397 # Request fanout histogram system.membus.reqLayer0.occupancy 488000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2101750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 7324072b2..bfd96912f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18821000 # Number of ticks simulated -final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19046000 # Number of ticks simulated +final_tick 19046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81076 # Simulator instruction rate (inst/s) -host_op_rate 94934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 332169191 # Simulator tick rate (ticks/s) -host_mem_usage 262700 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 51970 # Simulator instruction rate (inst/s) +host_op_rate 60857 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215490046 # Simulator tick rate (ticks/s) +host_mem_usage 266056 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory +system.physmem.bytes_read::total 28480 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443 # Number of read requests accepted +system.physmem.num_reads::total 445 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 974482831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430116560 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 90727712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1495327103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 974482831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 974482831 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 974482831 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430116560 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 90727712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1495327103 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 445 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 101 # Per bank write bursts +system.physmem.perBankRdBursts::0 103 # Per bank write bursts system.physmem.perBankRdBursts::1 48 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts system.physmem.perBankRdBursts::3 45 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18779500 # Total gap between requests +system.physmem.totGap 19004500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443 # Read request sizes (log2) +system.physmem.readPktSize::6 445 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -96,11 +96,11 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see @@ -192,77 +192,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 429.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 289.613657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.341954 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 12.70% 12.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 26.98% 39.68% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 9.52% 66.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.17% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 77.78% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3401243 # Total ticks spent queuing -system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst +system.physmem.totQLat 4296708 # Total ticks spent queuing +system.physmem.totMemAccLat 12640458 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9655.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28405.52 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1495.33 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1495.33 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 371 # Number of row buffer hits during reads +system.physmem.readRowHits 373 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42391.65 # Average gap between requests -system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 42706.74 # Average gap between requests +system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2152800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) -system.physmem_0.averagePower 912.921838 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states +system.physmem_0.actBackEnergy 10689210 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 123000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14426160 # Total energy per rank (pJ) +system.physmem_0.averagePower 911.173851 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 148750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15177500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) -system.physmem_1.averagePower 811.289436 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states +system.physmem_1.actBackEnergy 10733670 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 84000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12844635 # Total energy per rank (pJ) +system.physmem_1.averagePower 811.282804 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1145250 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15228250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted +system.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 2439 # Number of BP lookups +system.cpu.branchPred.condPredicted 1443 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 449 # Number of BTB hits +system.cpu.branchPred.BTBHits 448 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 48.961749 # BTB Hit Percentage system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. @@ -270,7 +270,7 @@ system.cpu.branchPred.indirectHits 13 # Nu system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -300,7 +300,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +330,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +360,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -391,85 +391,85 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37643 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 19046000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 38093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 6117 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2439 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8723 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 274 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 416 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 16246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.839530 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.200509 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9855 60.66% 60.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2507 15.43% 76.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 520 3.20% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3364 20.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 16246 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064028 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.301053 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5842 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4705 # Number of cycles decode is blocked system.cpu.decode.RunCycles 5178 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode +system.cpu.decode.BranchResolved 375 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10177 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1679 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full +system.cpu.rename.IdleCycles 6957 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1136 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2347 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4188 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1232 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9097 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 461 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41121 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1125 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9457 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41127 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3963 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued +system.cpu.iq.iqInstsIssued 7229 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 16246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.444971 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.838160 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11980 73.74% 73.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1997 12.29% 86.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1618 9.96% 95.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 608 3.74% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 43 0.26% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -477,105 +477,105 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16246 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 416 28.89% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 475 32.99% 61.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 549 38.12% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4534 62.72% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1606 22.22% 85.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1081 14.95% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7234 # Type of FU issued -system.cpu.iq.rate 0.192174 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads +system.cpu.iq.FU_type_0::total 7229 # Type of FU issued +system.cpu.iq.rate 0.189772 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1440 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.199198 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32277 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 6614 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8641 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 346 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking +system.cpu.iew.iewBlockCycles 339 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall @@ -583,41 +583,41 @@ system.cpu.iew.memOrderViolationEvents 7 # Nu system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6820 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1423 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2451 # number of memory reference insts executed -system.cpu.iew.exec_branches 1299 # Number of branches executed -system.cpu.iew.exec_stores 1030 # Number of stores executed -system.cpu.iew.exec_rate 0.181282 # Inst execution rate -system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6637 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2986 # num instructions producing a value -system.cpu.iew.wb_consumers 5424 # num instructions consuming a value -system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 2448 # number of memory reference insts executed +system.cpu.iew.exec_branches 1296 # Number of branches executed +system.cpu.iew.exec_stores 1025 # Number of stores executed +system.cpu.iew.exec_rate 0.179036 # Inst execution rate +system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6630 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2985 # num instructions producing a value +system.cpu.iew.wb_consumers 5422 # num instructions consuming a value +system.cpu.iew.wb_rate 0.174048 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.550535 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 2710 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 15677 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.343050 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.979995 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13011 82.99% 82.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1405 8.96% 91.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 598 3.81% 95.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 299 1.91% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 169 1.08% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 80 0.51% 99.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 44 0.28% 99.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 28 0.18% 99.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 43 0.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15677 # Number of insts commited each cycle system.cpu.commit.committedInsts 4592 # Number of instructions committed system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -664,40 +664,40 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23088 # The number of ROB reads -system.cpu.rob.rob_writes 16743 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23565 # The number of ROB reads +system.cpu.rob.rob_writes 16751 # The number of ROB writes +system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21847 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4592 # Number of Instructions Simulated system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads -system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6777 # number of integer regfile reads -system.cpu.int_regfile_writes 3787 # number of integer regfile writes +system.cpu.cpi 8.295514 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.295514 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120547 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120547 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6772 # number of integer regfile reads +system.cpu.int_regfile_writes 3788 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24229 # number of cc regfile reads -system.cpu.cc_regfile_writes 2921 # number of cc regfile writes -system.cpu.misc_regfile_reads 2564 # number of misc regfile reads +system.cpu.cc_regfile_reads 24217 # number of cc regfile reads +system.cpu.cc_regfile_writes 2924 # number of cc regfile writes +system.cpu.misc_regfile_reads 2559 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 84.349867 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.349867 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164746 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164746 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.tag_accesses 4725 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4725 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -710,76 +710,76 @@ system.cpu.dcache.demand_hits::cpu.data 1910 # nu system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits system.cpu.dcache.overall_hits::total 1910 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses -system.cpu.dcache.overall_misses::total 358 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10679500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10679500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7608000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7608000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18287500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18287500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18287500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses +system.cpu.dcache.overall_misses::total 359 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10937500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10937500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9601000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9601000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20538500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20538500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20538500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20538500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1356 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1356 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2269 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2269 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2269 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2269 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123894 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123894 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63949.101796 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39832.460733 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39832.460733 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158219 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158219 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158219 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158219 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57210.306407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57210.306407 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1304 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 72.444444 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 1 # number of writebacks system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -788,189 +788,187 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 144 system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6934000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2433000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2433000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9367000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9367000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7149000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9849500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9849500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9849500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9849500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075959 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075959 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 137.872552 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3542 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 137.872552 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.269282 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.269282 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses -system.cpu.icache.tags.data_accesses 8101 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits -system.cpu.icache.overall_hits::total 3540 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 361 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 361 # number of overall misses -system.cpu.icache.overall_misses::total 361 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22435492 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22435492 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22435492 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22435492 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22435492 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22435492 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092540 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092540 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092540 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092540 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092540 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62148.177285 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62148.177285 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62148.177285 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62148.177285 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8414 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 8107 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8107 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 3542 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3542 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3542 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3542 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3542 # number of overall hits +system.cpu.icache.overall_hits::total 3542 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses +system.cpu.icache.overall_misses::total 362 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22563992 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22563992 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22563992 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22563992 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22563992 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22563992 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3904 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3904 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3904 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3904 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092725 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092725 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092725 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092725 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092725 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092725 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62331.469613 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62331.469613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62331.469613 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8558 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 35 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.084211 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 44 # number of writebacks system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19775992 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19775992 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19775992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19775992 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19775992 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19775992 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19836992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19836992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19836992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076588 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.076588 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.076588 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66344.454849 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.162055 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000498 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.001062 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17622000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17622000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5892000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5892000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17622000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8011000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17622000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8011000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27541926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 3053926 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2154000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17682000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17682000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6104000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6104000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17682000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25940000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17682000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8258000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28993926 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.939052 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.058691 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 36017.471698 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70633.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70633.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60765.517241 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60765.517241 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61375 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71800 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution @@ -1106,49 +1105,55 @@ system.cpu.toL2Bus.pkt_count::total 930 # Pa system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 454 # Total snoops (count) +system.cpu.toL2Bus.snoops 69 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 411 45.82% 95.43% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41 4.57% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 412 # Transaction distribution +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 443 # Request fanout histogram +system.membus.snoop_fanout::samples 445 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 443 # Request fanout histogram -system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 445 # Request fanout histogram +system.membus.reqLayer0.occupancy 562944 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2340257 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 55d542711..83c02dd61 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 427598 # Simulator instruction rate (inst/s) -host_op_rate 499586 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 249859240 # Simulator tick rate (ticks/s) -host_mem_usage 254616 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 207093 # Simulator instruction rate (inst/s) +host_op_rate 242387 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121392563 # Simulator tick rate (ticks/s) +host_mem_usage 259512 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -344,6 +344,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution @@ -361,14 +367,14 @@ system.membus.pkt_size::total 26559 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 43260b12f..b8117da74 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2695000 # Number of ticks simulated final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 433184 # Simulator instruction rate (inst/s) -host_op_rate 506134 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 253162440 # Simulator tick rate (ticks/s) -host_mem_usage 254364 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 213878 # Simulator instruction rate (inst/s) +host_op_rate 250318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 125362190 # Simulator tick rate (ticks/s) +host_mem_usage 258232 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4592 # Number of instructions simulated sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -220,6 +220,12 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 5597 # Transaction distribution system.membus.trans_dist::ReadResp 5608 # Transaction distribution @@ -237,14 +243,14 @@ system.membus.pkt_size::total 26559 # Cu system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram -system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 40170ff2c..6ed816eb8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28298500 # Number of ticks simulated -final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000029 # Number of seconds simulated +sim_ticks 28648500 # Number of ticks simulated +final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 246555 # Simulator instruction rate (inst/s) -host_op_rate 287459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1524533550 # Simulator tick rate (ticks/s) -host_mem_usage 264352 # Number of bytes of host memory used +host_inst_rate 192730 # Simulator instruction rate (inst/s) +host_op_rate 224907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208517164 # Simulator tick rate (ticks/s) +host_mem_usage 267456 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 4566 # Number of instructions simulated sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,8 +153,8 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 56597 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 57297 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4566 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles +system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1008 # Number of branches fetched @@ -214,23 +214,23 @@ system.cpu.op_class::MemWrite 938 17.40% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5391 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -251,14 +251,14 @@ system.cpu.dcache.demand_misses::cpu.data 141 # n system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -279,14 +279,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -301,14 +301,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -317,31 +317,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses system.cpu.icache.tags.data_accesses 9453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits @@ -354,12 +354,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses @@ -372,12 +372,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,43 +392,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits @@ -451,18 +451,18 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) @@ -487,18 +487,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,18 +517,18 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses @@ -541,25 +541,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -591,7 +591,13 @@ system.cpu.toL2Bus.respLayer0.occupancy 361500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states +system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution @@ -613,8 +619,8 @@ system.membus.snoop_fanout::min_value 0 # Re system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.membus.respLayer1.utilization 6.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- |