summaryrefslogtreecommitdiff
path: root/tests/quick/se/00.hello/ref/arm
diff options
context:
space:
mode:
Diffstat (limited to 'tests/quick/se/00.hello/ref/arm')
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini67
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout6
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt1081
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini81
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/o3-timing/simout6
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt1129
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini14
-rwxr-xr-xtests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout4
-rw-r--r--tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt10
9 files changed, 1220 insertions, 1178 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 6e3934424..6a6ed7d49 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -128,7 +128,7 @@ icache_port=system.cpu.icache.cpu_side
type=O3Checker
children=dtb itb tracer
checker=Null
-clock=1
+clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
@@ -161,7 +161,7 @@ walker=system.cpu.checker.dtb.walker
[system.cpu.checker.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[5]
@@ -174,7 +174,7 @@ walker=system.cpu.checker.itb.walker
[system.cpu.checker.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[4]
@@ -187,18 +187,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
@@ -217,7 +217,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -490,18 +490,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
@@ -523,7 +523,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -531,24 +531,24 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -558,10 +558,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
@@ -598,15 +598,28 @@ master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[0]
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index 425371c96..edb619587 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:20:03
+gem5 compiled Nov 1 2012 15:18:10
+gem5 started Nov 1 2012 22:40:56
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 10738000 because target called exit()
+Exiting @ tick 13371000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
index ccb8279d9..0b4c661be 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt
@@ -1,47 +1,47 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13414500 # Number of ticks simulated
-final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13371000 # Number of ticks simulated
+final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59216 # Simulator instruction rate (inst/s)
-host_op_rate 73866 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 172781643 # Simulator tick rate (ticks/s)
-host_mem_usage 231444 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 32660 # Simulator instruction rate (inst/s)
+host_op_rate 40743 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 94998008 # Simulator tick rate (ticks/s)
+host_mem_usage 228356 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 401 # Total number of read requests seen
+system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 25600 # Total number of bytes read from memory
+system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25216 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
@@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13356500 # Total gap between requests
+system.physmem.totGap 13312500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 401 # Categorize read packet sizes
+system.physmem.readPktSize::6 394 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2497399 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests
-system.physmem.totBusLat 1604000 # Total cycles spent in databus access
-system.physmem.totBankLat 6636000 # Total cycles spent in bank access
-system.physmem.avgQLat 6227.93 # Average queueing delay per request
-system.physmem.avgBankLat 16548.63 # Average bank access latency per request
+system.physmem.totQLat 2460894 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests
+system.physmem.totBusLat 1576000 # Total cycles spent in databus access
+system.physmem.totBankLat 6524000 # Total cycles spent in bank access
+system.physmem.avgQLat 6245.92 # Average queueing delay per request
+system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26776.56 # Average memory access latency
-system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26804.30 # Average memory access latency
+system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.93 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.80 # Average read queue length over time
+system.physmem.busUtil 11.79 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 326 # Number of row buffer hits during reads
+system.physmem.readRowHits 319 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33307.98 # Average gap between requests
+system.physmem.avgGap 33788.07 # Average gap between requests
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
@@ -273,245 +273,244 @@ system.cpu.itb.inst_accesses 0 # IT
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.numCycles 26830 # number of cpu cycles simulated
+system.cpu.numCycles 26743 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2508 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect
+system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits
+system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2440 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8896 # Type of FU issued
-system.cpu.iq.rate 0.331569 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
+system.cpu.iq.rate 0.336088 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1 # number of nop insts executed
-system.cpu.iew.exec_refs 3284 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1437 # Number of branches executed
-system.cpu.iew.exec_stores 1174 # Number of stores executed
-system.cpu.iew.exec_rate 0.316996 # Inst execution rate
-system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8071 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3897 # num instructions producing a value
-system.cpu.iew.wb_consumers 7827 # num instructions consuming a value
+system.cpu.iew.exec_nop 0 # number of nop insts executed
+system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1446 # Number of branches executed
+system.cpu.iew.exec_stores 1164 # Number of stores executed
+system.cpu.iew.exec_rate 0.320233 # Inst execution rate
+system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3899 # num instructions producing a value
+system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4596 # Number of instructions committed
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -522,69 +521,69 @@ system.cpu.commit.branches 1008 # Nu
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23385 # The number of ROB reads
-system.cpu.rob.rob_writes 23680 # The number of ROB writes
-system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 22988 # The number of ROB reads
+system.cpu.rob.rob_writes 23599 # The number of ROB writes
+system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39120 # number of integer regfile reads
-system.cpu.int_regfile_writes 7969 # number of integer regfile writes
+system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39369 # number of integer regfile reads
+system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 15172 # number of misc regfile reads
+system.cpu.misc_regfile_reads 15007 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use
-system.cpu.icache.total_refs 1570 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
+system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits
-system.cpu.icache.overall_hits::total 1570 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses
-system.cpu.icache.overall_misses::total 373 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
+system.cpu.icache.overall_hits::total 1601 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
+system.cpu.icache.overall_misses::total 359 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@@ -593,236 +592,236 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits
+system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits
-system.cpu.dcache.overall_hits::total 2324 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
+system.cpu.dcache.overall_hits::total 2371 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses
-system.cpu.dcache.overall_misses::total 518 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
+system.cpu.dcache.overall_misses::total 498 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
-system.cpu.l2cache.overall_hits::total 41 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
+system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
+system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
+system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
-system.cpu.l2cache.overall_misses::total 405 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total 399 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -831,56 +830,56 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index f5b7d940d..c182ad17a 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -30,7 +30,7 @@ system_port=system.membus.slave[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -78,6 +78,7 @@ iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -129,18 +130,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
@@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -432,18 +433,18 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
@@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
@@ -465,7 +483,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -500,10 +518,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
@@ -540,15 +558,28 @@ master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[0]
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index dc9a7546c..116fbeb57 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -1,11 +1,11 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:07
+gem5 compiled Oct 30 2012 11:20:14
+gem5 started Oct 30 2012 18:52:17
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 10738000 because target called exit()
+Exiting @ tick 13371000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
index 62de1d1aa..76131bc35 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
@@ -1,47 +1,47 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000013 # Number of seconds simulated
-sim_ticks 13414500 # Number of ticks simulated
-final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 13371000 # Number of ticks simulated
+final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64991 # Simulator instruction rate (inst/s)
-host_op_rate 81070 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 189628588 # Simulator tick rate (ticks/s)
-host_mem_usage 230428 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 37264 # Simulator instruction rate (inst/s)
+host_op_rate 46486 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 108387516 # Simulator tick rate (ticks/s)
+host_mem_usage 228452 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 4596 # Number of instructions simulated
sim_ops 5734 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory
-system.physmem.bytes_read::total 25600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 25216 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 400 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 401 # Total number of read requests seen
+system.physmem.num_reads::total 394 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 394 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
-system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 25600 # Total number of bytes read from memory
+system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 25216 # Total number of bytes read from memory
system.physmem.bytesWritten 0 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis
@@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr
system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
@@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 13356500 # Total gap between requests
+system.physmem.totGap 13312500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 401 # Categorize read packet sizes
+system.physmem.readPktSize::6 394 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
@@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca
system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
@@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2497399 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests
-system.physmem.totBusLat 1604000 # Total cycles spent in databus access
-system.physmem.totBankLat 6636000 # Total cycles spent in bank access
-system.physmem.avgQLat 6227.93 # Average queueing delay per request
-system.physmem.avgBankLat 16548.63 # Average bank access latency per request
+system.physmem.totQLat 2460894 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests
+system.physmem.totBusLat 1576000 # Total cycles spent in databus access
+system.physmem.totBankLat 6524000 # Total cycles spent in bank access
+system.physmem.avgQLat 6245.92 # Average queueing delay per request
+system.physmem.avgBankLat 16558.38 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26776.56 # Average memory access latency
-system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26804.30 # Average memory access latency
+system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
-system.physmem.busUtil 11.93 # Data bus utilization in percentage
-system.physmem.avgRdQLen 0.80 # Average read queue length over time
+system.physmem.busUtil 11.79 # Data bus utilization in percentage
+system.physmem.avgRdQLen 0.79 # Average read queue length over time
system.physmem.avgWrQLen 0.00 # Average write queue length over time
-system.physmem.readRowHits 326 # Number of row buffer hits during reads
+system.physmem.readRowHits 319 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 33307.98 # Average gap between requests
+system.physmem.avgGap 33788.07 # Average gap between requests
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
@@ -228,245 +228,244 @@ system.cpu.itb.hits 0 # DT
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 13 # Number of system calls
-system.cpu.numCycles 26830 # number of cpu cycles simulated
+system.cpu.numCycles 26743 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2508 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect
+system.cpu.BPredUnit.lookups 2505 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits
+system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 2440 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 2245 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 2446 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 2247 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 49 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 44 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 8896 # Type of FU issued
-system.cpu.iq.rate 0.331569 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 215 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total 8988 # Type of FU issued
+system.cpu.iq.rate 0.336088 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 228 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1 # number of nop insts executed
-system.cpu.iew.exec_refs 3284 # number of memory reference insts executed
-system.cpu.iew.exec_branches 1437 # Number of branches executed
-system.cpu.iew.exec_stores 1174 # Number of stores executed
-system.cpu.iew.exec_rate 0.316996 # Inst execution rate
-system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 8071 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 3897 # num instructions producing a value
-system.cpu.iew.wb_consumers 7827 # num instructions consuming a value
+system.cpu.iew.exec_nop 0 # number of nop insts executed
+system.cpu.iew.exec_refs 3300 # number of memory reference insts executed
+system.cpu.iew.exec_branches 1446 # Number of branches executed
+system.cpu.iew.exec_stores 1164 # Number of stores executed
+system.cpu.iew.exec_rate 0.320233 # Inst execution rate
+system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 8109 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 3899 # num instructions producing a value
+system.cpu.iew.wb_consumers 7837 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle
system.cpu.commit.committedInsts 4596 # Number of instructions committed
system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
@@ -477,69 +476,69 @@ system.cpu.commit.branches 1008 # Nu
system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.int_insts 4980 # Number of committed integer instructions.
system.cpu.commit.function_calls 82 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 23385 # The number of ROB reads
-system.cpu.rob.rob_writes 23680 # The number of ROB writes
-system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.rob.rob_reads 22988 # The number of ROB reads
+system.cpu.rob.rob_writes 23599 # The number of ROB writes
+system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 4596 # Number of Instructions Simulated
system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 4596 # Number of Instructions Simulated
-system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 39120 # number of integer regfile reads
-system.cpu.int_regfile_writes 7969 # number of integer regfile writes
+system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 39369 # number of integer regfile reads
+system.cpu.int_regfile_writes 8027 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.misc_regfile_reads 15172 # number of misc regfile reads
+system.cpu.misc_regfile_reads 15007 # number of misc regfile reads
system.cpu.misc_regfile_writes 26 # number of misc regfile writes
system.cpu.icache.replacements 4 # number of replacements
-system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use
-system.cpu.icache.total_refs 1570 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use
+system.cpu.icache.total_refs 1601 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits
-system.cpu.icache.overall_hits::total 1570 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses
-system.cpu.icache.overall_misses::total 373 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits
+system.cpu.icache.overall_hits::total 1601 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses
+system.cpu.icache.overall_misses::total 359 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@@ -548,294 +547,294 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits
+system.cpu.l2cache.overall_hits::total 40 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
+system.cpu.l2cache.overall_misses::total 399 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits
+system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits
-system.cpu.dcache.overall_hits::total 2324 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits
+system.cpu.dcache.overall_hits::total 2371 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses
-system.cpu.dcache.overall_misses::total 518 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses
+system.cpu.dcache.overall_misses::total 498 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits
-system.cpu.l2cache.overall_hits::total 41 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses
-system.cpu.l2cache.overall_misses::total 405 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 1ce31c334..bda1e98df 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -64,7 +64,7 @@ icache_port=system.membus.slave[1]
type=DummyChecker
children=dtb itb tracer
checker=Null
-clock=1
+clock=500
cpu_id=-1
defer_registration=false
do_checkpoint_insts=true
@@ -94,7 +94,7 @@ walker=system.cpu.checker.dtb.walker
[system.cpu.checker.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
@@ -106,7 +106,7 @@ walker=system.cpu.checker.itb.walker
[system.cpu.checker.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
@@ -121,7 +121,7 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
@@ -137,7 +137,7 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
@@ -177,7 +177,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 21ae26652..57c2a5d84 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -1,8 +1,8 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:07
+gem5 compiled Nov 1 2012 15:18:10
+gem5 started Nov 1 2012 22:41:17
gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
index 592f491b0..147a664f0 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 92985 # Simulator instruction rate (inst/s)
-host_op_rate 115998 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58104040 # Simulator tick rate (ticks/s)
-host_mem_usage 217212 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 135088 # Simulator instruction rate (inst/s)
+host_op_rate 168502 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 84394877 # Simulator tick rate (ticks/s)
+host_mem_usage 218472 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory