diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt | 550 |
1 files changed, 275 insertions, 275 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 888fdd0d2..00c469890 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24405000 # Number of ticks simulated final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38911 # Simulator instruction rate (inst/s) -host_op_rate 38904 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189891987 # Simulator tick rate (ticks/s) -host_mem_usage 234100 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 119579 # Simulator instruction rate (inst/s) +host_op_rate 119550 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 583509526 # Simulator tick rate (ticks/s) +host_mem_usage 251420 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4999 # Number of instructions simulated sim_ops 4999 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -201,12 +201,12 @@ system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # By system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation -system.physmem.totQLat 7577250 # Total ticks spent queuing -system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 7589250 # Total ticks spent queuing +system.physmem.totMemAccLat 16383000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers -system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst +system.physmem.avgQLat 16181.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34931.77 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s @@ -228,9 +228,9 @@ system.physmem_0.preEnergy 98670 # En system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 1603980 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) +system.physmem_0.actPowerDownEnergy 8337960 # Energy for active power-down per rank (pJ) system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) @@ -247,29 +247,29 @@ system.physmem_1.preEnergy 333960 # En system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.actBackEnergy 4208310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 89280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 6602310 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 178560 # Energy for precharge power-down per rank (pJ) system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ) -system.physmem_1.averagePower 675.693915 # Core power per rank (mW) +system.physmem_1.totalEnergy 16490760 # Total energy per rank (pJ) +system.physmem_1.averagePower 675.712354 # Core power per rank (mW) system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 464250 # Time in different power states system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 14474500 # Time in different power states system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2188 # Number of BP lookups -system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups -system.cpu.branchPred.BTBHits 587 # Number of BTB hits +system.cpu.branchPred.lookups 2177 # Number of BP lookups +system.cpu.branchPred.condPredicted 1448 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 422 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups +system.cpu.branchPred.BTBHits 589 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 33.108488 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. @@ -299,91 +299,91 @@ system.cpu.pwrStateResidencyTicks::ON 24405000 # Cu system.cpu.numCycles 48811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 9085 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12947 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2177 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 842 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2046 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 261 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 15162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.853911 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.140587 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11809 77.89% 77.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1506 9.93% 87.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 111 0.73% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 164 1.08% 89.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 279 1.84% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 101 0.67% 92.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 136 0.90% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.04% 94.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 898 5.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2768 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 15162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.044601 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.265248 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8416 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3447 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2766 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 141 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 392 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 589 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11962 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 392 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8568 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 617 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running +system.cpu.rename.RunCycles 2736 # Number of cycles rename is running system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 11523 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 6897 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13509 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13276 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3605 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2464 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8995 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4006 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1995 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15162 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.534758 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264874 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11839 78.08% 78.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1338 8.82% 86.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 727 4.79% 91.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 451 2.97% 94.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 343 2.26% 96.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 1.87% 98.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 110 0.73% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.34% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15162 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available @@ -423,58 +423,58 @@ system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4767 58.79% 58.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2271 28.01% 86.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1063 13.11% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8118 # Type of FU issued -system.cpu.iq.rate 0.166315 # Inst issue rate +system.cpu.iq.FU_type_0::total 8108 # Type of FU issued +system.cpu.iq.rate 0.166110 # Inst issue rate system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.022200 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31574 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 13019 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7329 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8286 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1329 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed @@ -483,45 +483,45 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 392 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 487 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10600 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2464 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 335 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 436 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7776 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2123 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1596 # number of nop insts executed -system.cpu.iew.exec_refs 3178 # number of memory reference insts executed -system.cpu.iew.exec_branches 1363 # Number of branches executed +system.cpu.iew.exec_nop 1594 # number of nop insts executed +system.cpu.iew.exec_refs 3172 # number of memory reference insts executed +system.cpu.iew.exec_branches 1361 # Number of branches executed system.cpu.iew.exec_stores 1049 # Number of stores executed -system.cpu.iew.exec_rate 0.159595 # Inst execution rate -system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7339 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2867 # num instructions producing a value -system.cpu.iew.wb_consumers 4274 # num instructions consuming a value -system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit +system.cpu.iew.exec_rate 0.159308 # Inst execution rate +system.cpu.iew.wb_sent 7424 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7331 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2863 # num instructions producing a value +system.cpu.iew.wb_consumers 4269 # num instructions consuming a value +system.cpu.iew.wb_rate 0.150192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.670649 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 4961 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14286 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.394792 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.199270 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12095 84.66% 84.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 883 6.18% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 3.65% 94.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle @@ -531,7 +531,7 @@ system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14286 # Number of insts commited each cycle system.cpu.commit.committedInsts 5640 # Number of instructions committed system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -582,46 +582,46 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5640 # Class of committed instruction system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 24800 # The number of ROB reads -system.cpu.rob.rob_writes 22133 # The number of ROB writes +system.cpu.rob.rob_reads 24772 # The number of ROB reads +system.cpu.rob.rob_writes 22085 # The number of ROB writes system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 33649 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4999 # Number of Instructions Simulated system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10560 # number of integer regfile reads -system.cpu.int_regfile_writes 5141 # number of integer regfile writes +system.cpu.int_regfile_reads 10585 # number of integer regfile reads +system.cpu.int_regfile_writes 5135 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 161 # number of misc regfile reads system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.124976 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2389 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.064286 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.124976 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022247 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022247 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses +system.cpu.dcache.tags.tag_accesses 5940 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5940 # Number of data accesses system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits -system.cpu.dcache.overall_hits::total 2395 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses @@ -638,22 +638,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 46928999 system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2900 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2900 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2900 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2900 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083542 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.083542 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.176207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.176207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.176207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.176207 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency @@ -692,14 +692,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048276 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048276 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048276 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency @@ -710,57 +710,57 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 160.153151 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1609 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.846386 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 160.153151 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078200 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078200 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses +system.cpu.icache.tags.tag_accesses 4424 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4424 # Number of data accesses system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits -system.cpu.icache.overall_hits::total 1613 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 1609 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1609 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1609 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1609 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1609 # number of overall hits +system.cpu.icache.overall_hits::total 1609 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35547000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35547000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35547000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35547000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35547000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35547000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213587 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.213587 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.213587 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.213587 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.213587 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.213587 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81343.249428 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 81343.249428 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 81343.249428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 81343.249428 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 81343.249428 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,36 +781,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 332 system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 28124000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 28124000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28124000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 28124000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162268 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162268 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162268 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162268 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84710.843373 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84710.843373 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84710.843373 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 84710.843373 # average overall mshr miss latency system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 253.368786 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.183576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 91.185210 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004949 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007732 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id @@ -840,16 +840,16 @@ system.cpu.l2cache.overall_misses::cpu.data 140 # system.cpu.l2cache.overall_misses::total 469 # number of overall misses system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27593000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 27593000 # number of ReadCleanReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27593000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 40389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27593000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40389500 # number of overall miss cycles system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) @@ -878,16 +878,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.data 1 system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83869.300912 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83869.300912 # average ReadCleanReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 86118.336887 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83869.300912 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 86118.336887 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -908,16 +908,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.data 140 system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24303000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24303000 # number of ReadCleanReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24303000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 35699500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24303000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 35699500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses @@ -932,16 +932,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73869.300912 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73869.300912 # average ReadCleanReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73869.300912 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76118.336887 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |