diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby')
| -rw-r--r-- | tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini | 125 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt | 452 |
2 files changed, 427 insertions, 150 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index 03c785312..8604f5de4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000 [system] type=System -children=clk_domain cpu dvfs_handler physmem ruby sys_port_proxy voltage_domain +children=clk_domain cpu dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain @@ -22,7 +22,7 @@ load_addr_mask=1099511627775 load_offset=0 mem_mode=timing mem_ranges=0:268435455 -memories=system.physmem +memories=system.mem_ctrls num_work_ids=16 readfile= symbolfile= @@ -138,17 +138,82 @@ eventq_index=0 sys_clk_domain=system.clk_domain transition_latency=100000 -[system.physmem] -type=SimpleMemory -bandwidth=0.000000 +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 clk_domain=system.clk_domain conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true -latency=30 -latency_var=0 -null=true -range=0:134217727 +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:268435455 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10 +static_frontend_latency=10 +tBURST=5 +tCCD_L=0 +tCK=1 +tCL=14 +tCS=3 +tRAS=35 +tRCD=14 +tREFI=7800 +tRFC=260 +tRP=14 +tRRD=6 +tRRD_L=0 +tRTP=8 +tRTW=3 +tWR=15 +tWTR=8 +tXAW=30 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory [system.ruby] type=RubySystem @@ -158,9 +223,9 @@ block_size_bytes=64 clk_domain=system.ruby.clk_domain eventq_index=0 hot_lines=false -mem_size=268435456 -no_mem_vec=false +memory_size_bits=48 num_of_sequencers=1 +phys_mem=Null random_seed=1234 randomization=false @@ -174,56 +239,32 @@ voltage_domain=system.voltage_domain [system.ruby.dir_cntrl0] type=Directory_Controller -children=directory memBuffer +children=directory buffer_size=0 clk_domain=system.ruby.clk_domain cluster_id=0 directory=system.ruby.dir_cntrl0.directory directory_latency=12 eventq_index=0 -memBuffer=system.ruby.dir_cntrl0.memBuffer number_of_TBEs=256 -peer=Null recycle_latency=10 ruby_system=system.ruby +system=system +to_memory_controller_latency=1 transitions_per_cycle=4 version=0 dmaRequestToDir=system.ruby.network.master[3] dmaResponseFromDir=system.ruby.network.slave[3] forwardFromDir=system.ruby.network.slave[4] +memory=system.mem_ctrls.port requestToDir=system.ruby.network.master[2] responseFromDir=system.ruby.network.slave[2] [system.ruby.dir_cntrl0.directory] type=RubyDirectoryMemory eventq_index=0 -map_levels=4 numa_high_bit=5 size=268435456 -use_map=false -version=0 - -[system.ruby.dir_cntrl0.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -clk_domain=system.ruby.memctrl_clk_domain -dimm_bit_0=12 -dimms_per_channel=2 -eventq_index=0 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -ruby_system=system.ruby -tFaw=0 version=0 [system.ruby.l1_cntrl0] @@ -237,11 +278,11 @@ cluster_id=0 eventq_index=0 issue_latency=2 number_of_TBEs=256 -peer=Null recycle_latency=10 ruby_system=system.ruby send_evictions=false sequencer=system.ruby.l1_cntrl0.sequencer +system=system transitions_per_cycle=4 version=0 forwardToCache=system.ruby.network.master[0] @@ -266,7 +307,7 @@ tagArrayBanks=1 [system.ruby.l1_cntrl0.sequencer] type=RubySequencer -access_phys_mem=false +access_backing_store=false clk_domain=system.cpu.clk_domain dcache=system.ruby.l1_cntrl0.cacheMemory deadlock_threshold=500000 @@ -370,7 +411,7 @@ virt_nets=10 [system.sys_port_proxy] type=RubyPortProxy -access_phys_mem=true +access_backing_store=false clk_domain=system.clk_domain eventq_index=0 ruby_system=system.ruby diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index e8e105f9d..3a696e5a2 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -1,18 +1,268 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000123 # Number of seconds simulated -sim_ticks 122907 # Number of ticks simulated -final_tick 122907 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000116 # Number of seconds simulated +sim_ticks 115508 # Number of ticks simulated +final_tick 115508 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19204 # Simulator instruction rate (inst/s) -host_op_rate 19202 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 419624 # Simulator tick rate (ticks/s) -host_mem_usage 174296 # Number of bytes of host memory used -host_seconds 0.29 # Real time elapsed on the host +host_inst_rate 2198 # Simulator instruction rate (inst/s) +host_op_rate 2198 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45146 # Simulator tick rate (ticks/s) +host_mem_usage 435400 # Number of bytes of host memory used +host_seconds 2.56 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94080 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 94080 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93824 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 93824 # Number of bytes written to this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1470 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1470 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1466 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 1466 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 814489040 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 814489040 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::ruby.dir_cntrl0 812272743 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 812272743 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1626761783 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1626761783 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1470 # Number of read requests accepted +system.mem_ctrls.writeReqs 1466 # Number of write requests accepted +system.mem_ctrls.readBursts 1470 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 1466 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 59264 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 34816 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 60672 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 94080 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 93824 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 544 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 493 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 86 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 65 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 244 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 102 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 43 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 173 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 35 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 76 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 244 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 103 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 43 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 194 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 15 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 115437 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1470 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 1466 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 926 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 12 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 56 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 59 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 64 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 59 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 349 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 341.455587 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 225.575393 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 311.156448 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 80 22.92% 22.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 99 28.37% 51.29% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 59 16.91% 68.19% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 25 7.16% 75.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 22 6.30% 81.66% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 9 2.58% 84.24% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 12 3.44% 87.68% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 1.72% 89.40% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 37 10.60% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 349 # Bytes accessed per row activation +system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::mean 16.070175 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::gmean 15.908868 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::stdev 2.750712 # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::14-15 24 42.11% 45.61% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 89.47% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::18-19 5 8.77% 98.25% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes +system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes +system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::mean 16.631579 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::gmean 16.601010 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::stdev 1.045937 # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::16 39 68.42% 68.42% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::17 5 8.77% 77.19% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::18 9 15.79% 92.98% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads +system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads +system.mem_ctrls.totQLat 12468 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 30062 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 4630 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 13.46 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 32.46 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 513.07 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 525.26 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 814.49 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 812.27 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.11 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 4.01 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 25.51 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 626 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 891 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 67.60 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 91.57 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 39.32 # Average gap between requests +system.mem_ctrls.pageHitRate 79.88 # Row buffer hit rate, read and write combined +system.mem_ctrls.memoryStateTime::IDLE 12 # Time in different power states +system.mem_ctrls.memoryStateTime::REF 3640 # Time in different power states +system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls.memoryStateTime::ACT 105626 # Time in different power states +system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls.actEnergy::0 453600 # Energy for activate commands per rank (pJ) +system.mem_ctrls.actEnergy::1 2033640 # Energy for activate commands per rank (pJ) +system.mem_ctrls.preEnergy::0 252000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.preEnergy::1 1129800 # Energy for precharge commands per rank (pJ) +system.mem_ctrls.readEnergy::0 1547520 # Energy for read commands per rank (pJ) +system.mem_ctrls.readEnergy::1 9409920 # Energy for read commands per rank (pJ) +system.mem_ctrls.writeEnergy::0 1213056 # Energy for write commands per rank (pJ) +system.mem_ctrls.writeEnergy::1 8107776 # Energy for write commands per rank (pJ) +system.mem_ctrls.refreshEnergy::0 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.refreshEnergy::1 7119840 # Energy for refresh commands per rank (pJ) +system.mem_ctrls.actBackEnergy::0 51518196 # Energy for active background per rank (pJ) +system.mem_ctrls.actBackEnergy::1 74359692 # Energy for active background per rank (pJ) +system.mem_ctrls.preBackEnergy::0 20367000 # Energy for precharge background per rank (pJ) +system.mem_ctrls.preBackEnergy::1 330600 # Energy for precharge background per rank (pJ) +system.mem_ctrls.totalEnergy::0 82471212 # Total energy per rank (pJ) +system.mem_ctrls.totalEnergy::1 102491268 # Total energy per rank (pJ) +system.mem_ctrls.averagePower::0 754.788512 # Core power per rank (mW) +system.mem_ctrls.averagePower::1 938.014973 # Core power per rank (mW) system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -26,13 +276,13 @@ system.ruby.outstanding_req_hist::mean 1 system.ruby.outstanding_req_hist::gmean 1 system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 7659 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.outstanding_req_hist::total 7659 -system.ruby.latency_hist::bucket_size 16 -system.ruby.latency_hist::max_bucket 159 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 7658 -system.ruby.latency_hist::mean 15.049491 -system.ruby.latency_hist::gmean 5.422767 -system.ruby.latency_hist::stdev 24.869733 -system.ruby.latency_hist | 6188 80.80% 80.80% | 0 0.00% 80.80% | 0 0.00% 80.80% | 330 4.31% 85.11% | 1061 13.85% 98.97% | 77 1.01% 99.97% | 2 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::mean 14.083312 +system.ruby.latency_hist::gmean 5.240199 +system.ruby.latency_hist::stdev 27.247033 +system.ruby.latency_hist | 7337 95.81% 95.81% | 269 3.51% 99.32% | 34 0.44% 99.76% | 10 0.13% 99.90% | 4 0.05% 99.95% | 3 0.04% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 7658 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 @@ -41,13 +291,13 @@ system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 6188 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.hit_latency_hist::total 6188 -system.ruby.miss_latency_hist::bucket_size 16 -system.ruby.miss_latency_hist::max_bucket 159 +system.ruby.miss_latency_hist::bucket_size 64 +system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1470 -system.ruby.miss_latency_hist::mean 65.772109 -system.ruby.miss_latency_hist::gmean 65.537231 -system.ruby.miss_latency_hist::stdev 6.143987 -system.ruby.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::mean 60.738776 +system.ruby.miss_latency_hist::gmean 54.828482 +system.ruby.miss_latency_hist::stdev 34.263958 +system.ruby.miss_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1470 system.ruby.Directory.incomplete_times 1469 system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks @@ -55,7 +305,7 @@ system.ruby.l1_cntrl0.cacheMemory.demand_hits 6188 system.ruby.l1_cntrl0.cacheMemory.demand_misses 1470 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7658 # Number of cache demand accesses system.cpu.clk_domain.clock 1 # Clock period in ticks -system.ruby.network.routers0.percent_links_utilized 5.971995 +system.ruby.network.routers0.percent_links_utilized 6.354538 system.ruby.network.routers0.msg_count.Control::2 1470 system.ruby.network.routers0.msg_count.Data::2 1466 system.ruby.network.routers0.msg_count.Response_Data::4 1470 @@ -64,21 +314,7 @@ system.ruby.network.routers0.msg_bytes.Control::2 11760 system.ruby.network.routers0.msg_bytes.Data::2 105552 system.ruby.network.routers0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11728 -system.ruby.dir_cntrl0.memBuffer.memReq 2936 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 1470 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 1466 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 854 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 2108 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 2 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 2110 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 0.718665 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 845 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 1147 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 40 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 76 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 232 7.90% 7.90% | 108 3.68% 11.58% | 64 2.18% 13.76% | 51 1.74% 15.50% | 26 0.89% 16.38% | 106 3.61% 19.99% | 20 0.68% 20.67% | 38 1.29% 21.97% | 16 0.54% 22.51% | 52 1.77% 24.28% | 138 4.70% 28.99% | 48 1.63% 30.62% | 16 0.54% 31.16% | 70 2.38% 33.55% | 30 1.02% 34.57% | 220 7.49% 42.06% | 80 2.72% 44.79% | 60 2.04% 46.83% | 80 2.72% 49.56% | 118 4.02% 53.58% | 46 1.57% 55.14% | 52 1.77% 56.91% | 84 2.86% 59.78% | 180 6.13% 65.91% | 108 3.68% 69.58% | 74 2.52% 72.10% | 140 4.77% 76.87% | 112 3.81% 80.69% | 198 6.74% 87.43% | 261 8.89% 96.32% | 40 1.36% 97.68% | 68 2.32% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 2936 # Number of accesses per bank -system.ruby.network.routers1.percent_links_utilized 5.971995 +system.ruby.network.routers1.percent_links_utilized 6.354538 system.ruby.network.routers1.msg_count.Control::2 1470 system.ruby.network.routers1.msg_count.Data::2 1466 system.ruby.network.routers1.msg_count.Response_Data::4 1470 @@ -87,7 +323,7 @@ system.ruby.network.routers1.msg_bytes.Control::2 11760 system.ruby.network.routers1.msg_bytes.Data::2 105552 system.ruby.network.routers1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.percent_links_utilized 5.971995 +system.ruby.network.routers2.percent_links_utilized 6.354538 system.ruby.network.routers2.msg_count.Control::2 1470 system.ruby.network.routers2.msg_count.Data::2 1466 system.ruby.network.routers2.msg_count.Response_Data::4 1470 @@ -123,7 +359,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 122907 # number of cpu cycles simulated +system.cpu.numCycles 115508 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -142,7 +378,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 122907 # Number of busy cycles +system.cpu.num_busy_cycles 115508 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -181,32 +417,32 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction -system.ruby.network.routers0.throttle0.link_utilization 5.978504 +system.ruby.network.routers0.throttle0.link_utilization 6.361464 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers0.throttle1.link_utilization 5.965486 +system.ruby.network.routers0.throttle1.link_utilization 6.347612 system.ruby.network.routers0.throttle1.msg_count.Control::2 1470 system.ruby.network.routers0.throttle1.msg_count.Data::2 1466 system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11760 system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle0.link_utilization 5.965486 +system.ruby.network.routers1.throttle0.link_utilization 6.347612 system.ruby.network.routers1.throttle0.msg_count.Control::2 1470 system.ruby.network.routers1.throttle0.msg_count.Data::2 1466 system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11760 system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105552 -system.ruby.network.routers1.throttle1.link_utilization 5.978504 +system.ruby.network.routers1.throttle1.link_utilization 6.361464 system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1470 system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1466 system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105840 system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle0.link_utilization 5.978504 +system.ruby.network.routers2.throttle0.link_utilization 6.361464 system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1470 system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1466 system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105840 system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11728 -system.ruby.network.routers2.throttle1.link_utilization 5.965486 +system.ruby.network.routers2.throttle1.link_utilization 6.347612 system.ruby.network.routers2.throttle1.msg_count.Control::2 1470 system.ruby.network.routers2.throttle1.msg_count.Data::2 1466 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11760 @@ -221,13 +457,13 @@ system.ruby.delayVCHist.vnet_2::max_bucket 9 # system.ruby.delayVCHist.vnet_2::samples 1466 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2 | 1466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::total 1466 # delay histogram for vnet_2 -system.ruby.LD.latency_hist::bucket_size 16 -system.ruby.LD.latency_hist::max_bucket 159 +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 system.ruby.LD.latency_hist::samples 1132 -system.ruby.LD.latency_hist::mean 39.690813 -system.ruby.LD.latency_hist::gmean 18.392553 -system.ruby.LD.latency_hist::stdev 30.890580 -system.ruby.LD.latency_hist | 465 41.08% 41.08% | 0 0.00% 41.08% | 0 0.00% 41.08% | 147 12.99% 54.06% | 497 43.90% 97.97% | 22 1.94% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::mean 35.522968 +system.ruby.LD.latency_hist::gmean 16.130611 +system.ruby.LD.latency_hist::stdev 37.257775 +system.ruby.LD.latency_hist | 989 87.37% 87.37% | 116 10.25% 97.61% | 20 1.77% 99.38% | 4 0.35% 99.73% | 2 0.18% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.latency_hist::total 1132 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 @@ -236,21 +472,21 @@ system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 465 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.hit_latency_hist::total 465 -system.ruby.LD.miss_latency_hist::bucket_size 16 -system.ruby.LD.miss_latency_hist::max_bucket 159 +system.ruby.LD.miss_latency_hist::bucket_size 64 +system.ruby.LD.miss_latency_hist::max_bucket 639 system.ruby.LD.miss_latency_hist::samples 667 -system.ruby.LD.miss_latency_hist::mean 65.269865 -system.ruby.LD.miss_latency_hist::gmean 65.112332 -system.ruby.LD.miss_latency_hist::stdev 5.027167 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::mean 58.196402 +system.ruby.LD.miss_latency_hist::gmean 52.112336 +system.ruby.LD.miss_latency_hist::stdev 33.226027 +system.ruby.LD.miss_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.miss_latency_hist::total 667 -system.ruby.ST.latency_hist::bucket_size 16 -system.ruby.ST.latency_hist::max_bucket 159 +system.ruby.ST.latency_hist::bucket_size 64 +system.ruby.ST.latency_hist::max_bucket 639 system.ruby.ST.latency_hist::samples 901 -system.ruby.ST.latency_hist::mean 18.103219 -system.ruby.ST.latency_hist::gmean 6.303338 -system.ruby.ST.latency_hist::stdev 27.010521 -system.ruby.ST.latency_hist | 684 75.92% 75.92% | 0 0.00% 75.92% | 0 0.00% 75.92% | 46 5.11% 81.02% | 158 17.54% 98.56% | 13 1.44% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::mean 15.558269 +system.ruby.ST.latency_hist::gmean 5.883337 +system.ruby.ST.latency_hist::stdev 27.738104 +system.ruby.ST.latency_hist | 860 95.45% 95.45% | 33 3.66% 99.11% | 6 0.67% 99.78% | 1 0.11% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.latency_hist::total 901 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 @@ -259,21 +495,21 @@ system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.hit_latency_hist::total 684 -system.ruby.ST.miss_latency_hist::bucket_size 16 -system.ruby.ST.miss_latency_hist::max_bucket 159 +system.ruby.ST.miss_latency_hist::bucket_size 64 +system.ruby.ST.miss_latency_hist::max_bucket 639 system.ruby.ST.miss_latency_hist::samples 217 -system.ruby.ST.miss_latency_hist::mean 65.709677 -system.ruby.ST.miss_latency_hist::gmean 65.456791 -system.ruby.ST.miss_latency_hist::stdev 6.376574 -system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::mean 55.142857 +system.ruby.ST.miss_latency_hist::gmean 49.160125 +system.ruby.ST.miss_latency_hist::stdev 33.648687 +system.ruby.ST.miss_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.miss_latency_hist::total 217 -system.ruby.IFETCH.latency_hist::bucket_size 16 -system.ruby.IFETCH.latency_hist::max_bucket 159 +system.ruby.IFETCH.latency_hist::bucket_size 64 +system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 5625 -system.ruby.IFETCH.latency_hist::mean 9.601422 -system.ruby.IFETCH.latency_hist::gmean 4.140083 -system.ruby.IFETCH.latency_hist::stdev 19.494566 -system.ruby.IFETCH.latency_hist | 5039 89.58% 89.58% | 0 0.00% 89.58% | 0 0.00% 89.58% | 137 2.44% 92.02% | 406 7.22% 99.24% | 42 0.75% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::mean 9.532444 +system.ruby.IFETCH.latency_hist::gmean 4.102291 +system.ruby.IFETCH.latency_hist::stdev 22.246367 +system.ruby.IFETCH.latency_hist | 5488 97.56% 97.56% | 120 2.13% 99.70% | 8 0.14% 99.84% | 5 0.09% 99.93% | 2 0.04% 99.96% | 1 0.02% 99.98% | 0 0.00% 99.98% | 1 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 5625 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 @@ -282,21 +518,21 @@ system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5039 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.hit_latency_hist::total 5039 -system.ruby.IFETCH.miss_latency_hist::bucket_size 16 -system.ruby.IFETCH.miss_latency_hist::max_bucket 159 +system.ruby.IFETCH.miss_latency_hist::bucket_size 64 +system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 586 -system.ruby.IFETCH.miss_latency_hist::mean 66.366894 -system.ruby.IFETCH.miss_latency_hist::gmean 66.054272 -system.ruby.IFETCH.miss_latency_hist::stdev 7.096661 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::mean 65.704778 +system.ruby.IFETCH.miss_latency_hist::gmean 60.488386 +system.ruby.IFETCH.miss_latency_hist::stdev 35.064530 +system.ruby.IFETCH.miss_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 586 -system.ruby.Directory.miss_mach_latency_hist::bucket_size 16 -system.ruby.Directory.miss_mach_latency_hist::max_bucket 159 +system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 +system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1470 -system.ruby.Directory.miss_mach_latency_hist::mean 65.772109 -system.ruby.Directory.miss_mach_latency_hist::gmean 65.537231 -system.ruby.Directory.miss_mach_latency_hist::stdev 6.143987 -system.ruby.Directory.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 330 22.45% 22.45% | 1061 72.18% 94.63% | 77 5.24% 99.86% | 2 0.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_mach_latency_hist::mean 60.738776 +system.ruby.Directory.miss_mach_latency_hist::gmean 54.828482 +system.ruby.Directory.miss_mach_latency_hist::stdev 34.263958 +system.ruby.Directory.miss_mach_latency_hist | 1149 78.16% 78.16% | 269 18.30% 96.46% | 34 2.31% 98.78% | 10 0.68% 99.46% | 4 0.27% 99.73% | 3 0.20% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1470 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::max_bucket 9 @@ -319,34 +555,34 @@ system.ruby.Directory.miss_latency_hist.forward_to_first_response::total system.ruby.Directory.miss_latency_hist.first_response_to_completion::bucket_size 8 system.ruby.Directory.miss_latency_hist.first_response_to_completion::max_bucket 79 system.ruby.Directory.miss_latency_hist.first_response_to_completion::samples 1 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 61 -system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 61.000000 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::mean 75 +system.ruby.Directory.miss_latency_hist.first_response_to_completion::gmean 75.000000 system.ruby.Directory.miss_latency_hist.first_response_to_completion::stdev nan -system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.miss_latency_hist.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% system.ruby.Directory.miss_latency_hist.first_response_to_completion::total 1 -system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 16 -system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 159 +system.ruby.LD.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.LD.Directory.miss_type_mach_latency_hist::samples 667 -system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 65.269865 -system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 65.112332 -system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 5.027167 -system.ruby.LD.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 147 22.04% 22.04% | 497 74.51% 96.55% | 22 3.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.miss_type_mach_latency_hist::mean 58.196402 +system.ruby.LD.Directory.miss_type_mach_latency_hist::gmean 52.112336 +system.ruby.LD.Directory.miss_type_mach_latency_hist::stdev 33.226027 +system.ruby.LD.Directory.miss_type_mach_latency_hist | 524 78.56% 78.56% | 116 17.39% 95.95% | 20 3.00% 98.95% | 4 0.60% 99.55% | 2 0.30% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.LD.Directory.miss_type_mach_latency_hist::total 667 -system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 16 -system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 159 +system.ruby.ST.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.ST.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.ST.Directory.miss_type_mach_latency_hist::samples 217 -system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 65.709677 -system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 65.456791 -system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 6.376574 -system.ruby.ST.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 46 21.20% 21.20% | 158 72.81% 94.01% | 13 5.99% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.miss_type_mach_latency_hist::mean 55.142857 +system.ruby.ST.Directory.miss_type_mach_latency_hist::gmean 49.160125 +system.ruby.ST.Directory.miss_type_mach_latency_hist::stdev 33.648687 +system.ruby.ST.Directory.miss_type_mach_latency_hist | 176 81.11% 81.11% | 33 15.21% 96.31% | 6 2.76% 99.08% | 1 0.46% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.ST.Directory.miss_type_mach_latency_hist::total 217 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 16 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 159 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size 64 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 586 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 66.366894 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 66.054272 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 7.096661 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 137 23.38% 23.38% | 406 69.28% 92.66% | 42 7.17% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 65.704778 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 60.488386 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 35.064530 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 449 76.62% 76.62% | 120 20.48% 97.10% | 8 1.37% 98.46% | 5 0.85% 99.32% | 2 0.34% 99.66% | 1 0.17% 99.83% | 0 0.00% 99.83% | 1 0.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 586 system.ruby.L1Cache_Controller.Load 1132 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 5625 0.00% 0.00% |