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-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini48
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout6
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt385
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini49
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/o3-timing/simout6
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt383
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini15
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout6
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt13
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini16
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout6
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt13
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini48
-rwxr-xr-xtests/quick/se/00.hello/ref/mips/linux/simple-timing/simout6
-rw-r--r--tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt364
15 files changed, 813 insertions, 551 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index 1ccb30b9c..600677fb9 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
@@ -165,20 +164,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 677598e87..9f59be0ce 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:29
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:30
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
index 78172e7b6..6cd55fbff 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000020 # Nu
sim_ticks 19785000 # Number of ticks simulated
final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71616 # Simulator instruction rate (inst/s)
-host_tick_rate 243111037 # Simulator tick rate (ticks/s)
-host_mem_usage 208328 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 101976 # Simulator instruction rate (inst/s)
+host_op_rate 101944 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 346042004 # Simulator tick rate (ticks/s)
+host_mem_usage 210372 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 29120 # Number of bytes read from this memory
system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -54,9 +56,10 @@ system.cpu.comNops 657 # Nu
system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed
system.cpu.comInts 2155 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
-system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total)
system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads
@@ -110,26 +113,39 @@ system.cpu.icache.total_refs 443 # To
system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits
-system.cpu.icache.demand_hits 443 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 443 # number of overall hits
-system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses
-system.cpu.icache.demand_misses 341 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 341 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits
+system.cpu.icache.overall_hits::total 443 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses
+system.cpu.icache.overall_misses::total 341 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -138,27 +154,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use
@@ -166,32 +185,49 @@ system.cpu.dcache.total_refs 1838 # To
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits
-system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 1838 # number of overall hits
-system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses
-system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 251 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 763 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1838 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1838 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1838 # number of overall hits
+system.cpu.dcache.overall_hits::total 1838 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 162 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 162 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses
+system.cpu.dcache.overall_misses::total 251 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -200,32 +236,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 7448500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 111 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 111 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2746000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2746000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7448500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use
@@ -233,31 +275,64 @@ system.cpu.l2cache.total_refs 2 # To
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 455 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.l2cache.overall_misses::total 455 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 319 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 319 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -266,30 +341,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 404 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 455 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 508c3cad4..00305a8e7 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
@@ -460,20 +460,13 @@ is_top_level=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index eb1e6f70f..afa267678 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:41
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:39
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
index e49d82dd9..9ff42644b 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu
sim_ticks 12272500 # Number of ticks simulated
final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 65845 # Simulator instruction rate (inst/s)
-host_tick_rate 156294886 # Simulator tick rate (ticks/s)
-host_mem_usage 208908 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 97350 # Simulator instruction rate (inst/s)
+host_op_rate 97317 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 230983195 # Simulator tick rate (ticks/s)
+host_mem_usage 211060 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5169 # Number of instructions simulated
+sim_ops 5169 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30400 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -255,6 +257,7 @@ system.cpu.iew.wb_rate 0.289986 # in
system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted
@@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle
-system.cpu.commit.count 5826 # Number of instructions committed
+system.cpu.commit.committedInsts 5826 # Number of instructions committed
+system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2089 # Number of memory references committed
system.cpu.commit.loads 1164 # Number of loads committed
@@ -291,6 +295,7 @@ system.cpu.rob.rob_writes 20794 # Th
system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5169 # Number of Instructions Simulated
+system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads
@@ -307,26 +312,39 @@ system.cpu.icache.total_refs 1363 # To
system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits
-system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1363 # number of overall hits
-system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses
-system.cpu.icache.demand_misses 418 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 418 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits
+system.cpu.icache.overall_hits::total 1363 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses
+system.cpu.icache.overall_misses::total 418 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -335,27 +353,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 82 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 82 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 82 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.188658 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.188658 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.188658 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use
@@ -363,32 +384,49 @@ system.cpu.dcache.total_refs 2380 # To
system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 92.121984 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1802 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits
-system.cpu.dcache.demand_hits 2380 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 2380 # number of overall hits
-system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses
-system.cpu.dcache.demand_misses 480 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 480 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 4767500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 11508000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 16275500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 16275500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 1935 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 2860 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 2860 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.068734 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.167832 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.167832 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33907.291667 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33907.291667 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits
+system.cpu.dcache.overall_hits::total 2380 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses
+system.cpu.dcache.overall_misses::total 480 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -397,32 +435,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 1836000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 5108000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 5108000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.047028 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.049650 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.049650 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use
@@ -430,31 +474,64 @@ system.cpu.l2cache.total_refs 3 # To
system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 221.521956 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 3 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 424 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 475 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 475 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 14561000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 1760500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 16321500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 16321500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 427 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 478 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 478 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.992974 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.993724 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.993724 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34519.607843 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34361.052632 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34361.052632 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 163.434563 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 58.087393 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004988 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006760 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
+system.cpu.l2cache.overall_hits::total 3 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 333 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 424 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 333 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 475 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 333 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
+system.cpu.l2cache.overall_misses::total 475 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11418500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 14561000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1760500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1760500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 11418500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4903000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 16321500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 11418500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4903000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 16321500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 336 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 427 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 336 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -463,30 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index 8bad8df13..9563d85bf 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
type=MipsTLB
size=64
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index 4b9270f18..7716b33a4 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:47
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:41
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
index 397c3f1f6..9ae16c4c6 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu
sim_ticks 2913500 # Number of ticks simulated
final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 231601 # Simulator instruction rate (inst/s)
-host_tick_rate 115720913 # Simulator tick rate (ticks/s)
-host_mem_usage 199128 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 1078442 # Simulator instruction rate (inst/s)
+host_op_rate 1075012 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 535874927 # Simulator tick rate (ticks/s)
+host_mem_usage 200784 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27687 # Number of bytes read from this memory
system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3658 # Number of bytes written to this memory
@@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 8 # Nu
system.cpu.numCycles 5828 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.committedInsts 5827 # Number of instructions committed
+system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index e5b4b16c8..da3c93787 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
type=MipsTLB
size=64
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
@@ -131,6 +144,7 @@ issue_latency=2
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index f6eaf03f7..ac3ff100c 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:56
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:52
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 65d0aed82..8087912dc 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000293 # Nu
sim_ticks 292960 # Number of ticks simulated
final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 55801 # Simulator instruction rate (inst/s)
-host_tick_rate 2804966 # Simulator tick rate (ticks/s)
-host_mem_usage 220172 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 71598 # Simulator instruction rate (inst/s)
+host_op_rate 71583 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3598224 # Simulator tick rate (ticks/s)
+host_mem_usage 221836 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27687 # Number of bytes read from this memory
system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3658 # Number of bytes written to this memory
@@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 8 # Nu
system.cpu.numCycles 292960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.committedInsts 5827 # Number of instructions committed
+system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 36444e22d..3cd70d03a 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -1,6 +1,7 @@
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
@@ -130,20 +129,13 @@ is_top_level=false
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index 7525d1ad5..29b03eaff 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:52
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:50
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
index 566ce19a4..5a0520753 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
@@ -4,11 +4,13 @@ sim_seconds 0.000032 # Nu
sim_ticks 32088000 # Number of ticks simulated
final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 263412 # Simulator instruction rate (inst/s)
-host_tick_rate 1449372115 # Simulator tick rate (ticks/s)
-host_mem_usage 207940 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 603210 # Simulator instruction rate (inst/s)
+host_op_rate 602100 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3309896144 # Simulator tick rate (ticks/s)
+host_mem_usage 209992 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 28096 # Number of bytes read from this memory
system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
@@ -40,7 +42,8 @@ system.cpu.workload.num_syscalls 8 # Nu
system.cpu.numCycles 64176 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.committedInsts 5827 # Number of instructions committed
+system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
@@ -64,26 +67,39 @@ system.cpu.icache.total_refs 5526 # To
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
-system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 5526 # number of overall hits
-system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 303 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits
+system.cpu.icache.overall_hits::total 5526 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses
+system.cpu.icache.overall_misses::total 303 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -92,26 +108,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
@@ -119,32 +133,49 @@ system.cpu.dcache.total_refs 1951 # To
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -153,30 +184,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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@@ -184,31 +215,64 @@ system.cpu.l2cache.total_refs 2 # To
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system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
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@@ -217,30 +281,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
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+system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------