diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/mips')
4 files changed, 847 insertions, 703 deletions
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 54d30dc78..4cccc3a14 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19339000 # Number of ticks simulated -final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 24539000 # Number of ticks simulated +final_tick 24539000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 26477 # Simulator instruction rate (inst/s) -host_op_rate 26474 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88053451 # Simulator tick rate (ticks/s) -host_mem_usage 270344 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host +host_inst_rate 40560 # Simulator instruction rate (inst/s) +host_op_rate 40552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 171130571 # Simulator tick rate (ticks/s) +host_mem_usage 226208 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1049071824 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 456693728 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1505765551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1049071824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1049071824 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1049071824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 456693728 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1505765551 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 826765557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 359916867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1186682424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 826765557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 826765557 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 826765557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 359916867 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1186682424 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 29120 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 89 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 33 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 10 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 37 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 59 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 36 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 7 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19292000 # Total gap between requests +system.physmem.totGap 24472000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see @@ -149,34 +149,69 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2650000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 94 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 251.234043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.011055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.928179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 34 36.17% 36.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 16 17.02% 53.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 9 9.57% 62.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 9 9.57% 72.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4 4.26% 76.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 9 9.57% 86.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 1 1.06% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2 2.13% 89.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 2 2.13% 91.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 2 2.13% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 2 2.13% 95.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1 1.06% 96.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 1.06% 97.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 1 1.06% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 1 1.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 94 # Bytes accessed per row activation +system.physmem.totQLat 2632000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13115750 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access -system.physmem.totBankLat 9033750 # Total cycles spent in bank access -system.physmem.avgQLat 5824.18 # Average queueing delay per request -system.physmem.avgBankLat 19854.40 # Average bank access latency per request +system.physmem.totBankLat 8208750 # Total cycles spent in bank access +system.physmem.avgQLat 5784.62 # Average queueing delay per request +system.physmem.avgBankLat 18041.21 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30678.57 # Average memory access latency -system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28825.82 # Average memory access latency +system.physmem.avgRdBW 1186.68 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1186.68 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.76 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.72 # Average read queue length over time +system.physmem.busUtil 9.27 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.53 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 334 # Number of row buffer hits during reads +system.physmem.readRowHits 361 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.41 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42400.00 # Average gap between requests -system.cpu.branchPred.lookups 1154 # Number of BP lookups -system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted +system.physmem.avgGap 53784.62 # Average gap between requests +system.membus.throughput 1186682424 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 404 # Transaction distribution +system.membus.trans_dist::ReadResp 404 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 910 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 29120 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 551000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 4265750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 17.4 # Layer utilization (%) +system.cpu.branchPred.lookups 1157 # Number of BP lookups +system.cpu.branchPred.condPredicted 861 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 336 # Number of BTB hits +system.cpu.branchPred.BTBLookups 880 # Number of BTB lookups +system.cpu.branchPred.BTBHits 339 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 38.522727 # BTB Hit Percentage system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -198,34 +233,34 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 38679 # number of cpu cycles simulated +system.cpu.numCycles 49079 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedTaken 432 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5089 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8485 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1328 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2229 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3135 # Number of Instructions Executed. +system.cpu.execution_unit.executions 3133 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9463 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9516 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33303 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5376 # Number of cycles cpu stages are processed. -system.cpu.activity 13.899015 # Percentage of cycles cpu is active +system.cpu.timesIdled 488 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 43696 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. +system.cpu.activity 10.968031 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -237,72 +272,72 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.652735 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 8.441520 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.652735 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150314 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 8.441520 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118462 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150314 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35030 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.434060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35863 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.280436 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 35914 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.118462 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 45429 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3650 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.436989 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 46265 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2814 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.733613 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 46314 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.148582 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37453 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.169679 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35777 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.utilization 5.633774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 47841 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.522464 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46189 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2890 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.888466 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use -system.cpu.icache.total_refs 429 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 150.599216 # Cycle average of tags in use +system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits -system.cpu.icache.overall_hits::total 429 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses -system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18937500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18937500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18937500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54732.658960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54732.658960 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.599216 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073535 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 428 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18696000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5647250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24343250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3006000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3006000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18696000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8653250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27349250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18696000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8653250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27349250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -455,51 +509,51 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58977.917981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64910.919540 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60255.569307 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58941.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58941.176471 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58977.917981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62704.710145 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60108.241758 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use -system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 90.129103 # Cycle average of tags in use +system.cpu.dcache.total_refs 1637 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.862319 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.917113 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021952 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021952 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits -system.cpu.dcache.overall_hits::total 1644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses -system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5626500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5626500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14767500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14767500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20394000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20394000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20394000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20394000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 90.129103 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022004 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022004 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1065 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1065 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1637 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1637 # number of overall hits +system.cpu.dcache.overall_hits::total 1637 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 451 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 451 # number of overall misses +system.cpu.dcache.overall_misses::total 451 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7478500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7478500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21383500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21383500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28862000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28862000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28862000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28862000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -508,38 +562,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42072.649573 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42072.649573 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45932.432432 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45932.432432 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45932.432432 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084265 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.215996 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.215996 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.215996 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.215996 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76311.224490 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76311.224490 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60576.487252 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60576.487252 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63995.565410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63995.565410 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63995.565410 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 253 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.461538 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 313 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 313 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -548,14 +602,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5255500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5255500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2614500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2614500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7870000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7870000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7870000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6809500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3694500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3694500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10504000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10504000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10504000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -564,14 +618,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60408.045977 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60408.045977 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51264.705882 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51264.705882 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57028.985507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57028.985507 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78270.114943 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78270.114943 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72441.176471 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72441.176471 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76115.942029 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76115.942029 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index c79016c7b..37ca97b46 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17026500 # Number of ticks simulated -final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21759500 # Number of ticks simulated +final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 19281 # Simulator instruction rate (inst/s) -host_op_rate 19280 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63663526 # Simulator tick rate (ticks/s) -host_mem_usage 270344 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 43168 # Simulator instruction rate (inst/s) +host_op_rate 43158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182102261 # Simulator tick rate (ticks/s) +host_mem_usage 228268 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory system.physmem.num_reads::total 478 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 478 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady @@ -36,22 +36,22 @@ system.physmem.bytesConsumedRd 30592 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16967000 # Total gap between requests +system.physmem.totGap 21680500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,11 +85,11 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -149,36 +149,70 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2843000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests +system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation +system.physmem.totQLat 2435500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access -system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5947.70 # Average queueing delay per request -system.physmem.avgBankLat 19589.44 # Average bank access latency per request +system.physmem.totBankLat 8676250 # Total cycles spent in bank access +system.physmem.avgQLat 5095.19 # Average queueing delay per request +system.physmem.avgBankLat 18151.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30537.13 # Average memory access latency -system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28246.34 # Average memory access latency +system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.86 # Average read queue length over time +system.physmem.busUtil 10.98 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 351 # Number of row buffer hits during reads +system.physmem.readRowHits 375 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 35495.82 # Average gap between requests -system.cpu.branchPred.lookups 2218 # Number of BP lookups -system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups -system.cpu.branchPred.BTBHits 508 # Number of BTB hits +system.physmem.avgGap 45356.69 # Average gap between requests +system.membus.throughput 1405914658 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 427 # Transaction distribution +system.membus.trans_dist::ReadResp 427 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 956 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 30592 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.6 # Layer utilization (%) +system.cpu.branchPred.lookups 2196 # Number of BP lookups +system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups +system.cpu.branchPred.BTBHits 505 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -198,94 +232,94 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 34054 # number of cpu cycles simulated +system.cpu.numCycles 43520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3093 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3054 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2958 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2924 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available @@ -321,113 +355,113 @@ system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8318 # Type of FU issued -system.cpu.iq.rate 0.244259 # Inst issue rate +system.cpu.iq.FU_type_0::total 8313 # Type of FU issued +system.cpu.iq.rate 0.191016 # Inst issue rate system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1546 # number of nop insts executed -system.cpu.iew.exec_refs 3202 # number of memory reference insts executed -system.cpu.iew.exec_branches 1355 # Number of branches executed -system.cpu.iew.exec_stores 1077 # Number of stores executed -system.cpu.iew.exec_rate 0.232924 # Inst execution rate -system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7467 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2949 # num instructions producing a value -system.cpu.iew.wb_consumers 4258 # num instructions consuming a value +system.cpu.iew.exec_nop 1529 # number of nop insts executed +system.cpu.iew.exec_refs 3196 # number of memory reference insts executed +system.cpu.iew.exec_branches 1356 # Number of branches executed +system.cpu.iew.exec_stores 1078 # Number of stores executed +system.cpu.iew.exec_rate 0.182353 # Inst execution rate +system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7469 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2922 # num instructions producing a value +system.cpu.iew.wb_consumers 4200 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back +system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,119 +472,138 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23961 # The number of ROB reads -system.cpu.rob.rob_writes 22589 # The number of ROB writes -system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24277 # The number of ROB reads +system.cpu.rob.rob_writes 22442 # The number of ROB writes +system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads -system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10750 # number of integer regfile reads -system.cpu.int_regfile_writes 5236 # number of integer regfile writes +system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads +system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10757 # number of integer regfile reads +system.cpu.int_regfile_writes 5239 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 148 # number of misc regfile reads +system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 678 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 962 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 30784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 30784 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 508500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 213000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 161.130962 # Cycle average of tags in use +system.cpu.icache.total_refs 1541 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.545723 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses -system.cpu.icache.overall_misses::total 446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22343000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22343000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22343000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22343000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22343000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22343000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2012 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2012 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2012 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2012 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2012 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221670 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.221670 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.221670 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.221670 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.221670 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.221670 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50096.412556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50096.412556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50096.412556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50096.412556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 161.130962 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078677 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078677 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1541 # number of overall hits +system.cpu.icache.overall_hits::total 1541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses +system.cpu.icache.overall_misses::total 453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30806000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30806000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30806000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30806000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30806000 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19402750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9177500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28580250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19402750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9177500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28580250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -653,91 +706,91 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39461.389881 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52728.494505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42288.805621 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57746.279762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65483.516484 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59395.199063 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63107.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63107.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use -system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.370944 # Cycle average of tags in use +system.cpu.dcache.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.901408 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.619831 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits -system.cpu.dcache.overall_hits::total 2424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses -system.cpu.dcache.overall_misses::total 501 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8995500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8995500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24094499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24094499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24094499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 91.370944 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022307 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022307 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits +system.cpu.dcache.overall_hits::total 2400 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses +system.cpu.dcache.overall_misses::total 511 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10242000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22669999 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22669999 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32911999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32911999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32911999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32911999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1986 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2911 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2911 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2911 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2911 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075025 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.175541 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.175541 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.175541 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.175541 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68738.255034 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68738.255034 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62624.306630 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62624.306630 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64407.043053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -746,30 +799,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 773dc4053..e850cb6a0 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85249 # Simulator instruction rate (inst/s) -host_op_rate 85225 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42601271 # Simulator tick rate (ticks/s) -host_mem_usage 261900 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 727521 # Simulator instruction rate (inst/s) +host_op_rate 725084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 361375060 # Simulator tick rate (ticks/s) +host_mem_usage 216568 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory @@ -33,6 +33,9 @@ system.physmem.bw_write::total 1258341933 # Wr system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 10764361885 # Throughput (bytes/s) +system.membus.data_through_bus 31292 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 45395bf9c..0d57ed336 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3112 # Simulator instruction rate (inst/s) -host_op_rate 3112 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16931146 # Simulator tick rate (ticks/s) -host_mem_usage 270356 # Number of bytes of host memory used -host_seconds 1.87 # Real time elapsed on the host +host_inst_rate 482351 # Simulator instruction rate (inst/s) +host_op_rate 481309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2613274672 # Simulator tick rate (ticks/s) +host_mem_usage 225064 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -27,6 +27,21 @@ system.physmem.bw_inst_read::total 608984289 # In system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 888186388 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 388 # Transaction distribution +system.membus.trans_dist::ReadResp 388 # Transaction distribution +system.membus.trans_dist::ReadExReq 51 # Transaction distribution +system.membus.trans_dist::ReadExResp 51 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 878 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28096 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.5 # Layer utilization (%) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -369,5 +384,24 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 882 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- |