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diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
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+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.000003 # Number of seconds simulated
+sim_ticks 2900000 # Number of ticks simulated
+final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_inst_rate 305071 # Simulator instruction rate (inst/s)
+host_tick_rate 152367478 # Simulator tick rate (ticks/s)
+host_mem_usage 196296 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 5801 # Number of instructions simulated
+system.physmem.bytes_read 26925 # Number of bytes read from this memory
+system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory
+system.physmem.bytes_written 4209 # Number of bytes written to this memory
+system.physmem.num_reads 6763 # Number of read requests responded to by this memory
+system.physmem.num_writes 1046 # Number of write requests responded to by this memory
+system.physmem.num_other 0 # Number of other requests responded to by this memory
+system.physmem.bw_read 9284482759 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 8001379310 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 1451379310 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 10735862069 # Total bandwidth to/from this memory (bytes/s)
+system.cpu.dtb.read_hits 0 # DTB read hits
+system.cpu.dtb.read_misses 0 # DTB read misses
+system.cpu.dtb.read_accesses 0 # DTB read accesses
+system.cpu.dtb.write_hits 0 # DTB write hits
+system.cpu.dtb.write_misses 0 # DTB write misses
+system.cpu.dtb.write_accesses 0 # DTB write accesses
+system.cpu.dtb.hits 0 # DTB hits
+system.cpu.dtb.misses 0 # DTB misses
+system.cpu.dtb.accesses 0 # DTB accesses
+system.cpu.itb.read_hits 0 # DTB read hits
+system.cpu.itb.read_misses 0 # DTB read misses
+system.cpu.itb.read_accesses 0 # DTB read accesses
+system.cpu.itb.write_hits 0 # DTB write hits
+system.cpu.itb.write_misses 0 # DTB write misses
+system.cpu.itb.write_accesses 0 # DTB write accesses
+system.cpu.itb.hits 0 # DTB hits
+system.cpu.itb.misses 0 # DTB misses
+system.cpu.itb.accesses 0 # DTB accesses
+system.cpu.workload.num_syscalls 9 # Number of system calls
+system.cpu.numCycles 5801 # number of cpu cycles simulated
+system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
+system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.num_insts 5801 # Number of instructions executed
+system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses
+system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
+system.cpu.num_func_calls 200 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 896 # number of instructions that are conditional controls
+system.cpu.num_int_insts 5706 # number of integer instructions
+system.cpu.num_fp_insts 22 # number of float instructions
+system.cpu.num_int_register_reads 9541 # number of times the integer registers were read
+system.cpu.num_int_register_writes 5005 # number of times the integer registers were written
+system.cpu.num_fp_register_reads 20 # number of times the floating registers were read
+system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
+system.cpu.num_mem_refs 2008 # number of memory refs
+system.cpu.num_load_insts 962 # Number of load instructions
+system.cpu.num_store_insts 1046 # Number of store instructions
+system.cpu.num_idle_cycles 0 # Number of idle cycles
+system.cpu.num_busy_cycles 5801 # Number of busy cycles
+system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0 # Percentage of idle cycles
+
+---------- End Simulation Statistics ----------