diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/power')
| -rw-r--r-- | tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | 21 | ||||
| -rw-r--r-- | tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt | 12 |
2 files changed, 24 insertions, 9 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 9c7cb3cdb..c26ae805a 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000020 # Nu sim_ticks 19908000 # Number of ticks simulated final_tick 19908000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120043 # Simulator instruction rate (inst/s) -host_op_rate 120013 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 412413617 # Simulator tick rate (ticks/s) -host_mem_usage 245176 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 67828 # Simulator instruction rate (inst/s) +host_op_rate 67820 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 233087583 # Simulator tick rate (ticks/s) +host_mem_usage 290888 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory system.physmem.bytes_read::total 28352 # Number of bytes read from this memory @@ -250,6 +251,7 @@ system.physmem_1.memoryStateTime::REF 520000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 10721750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.branchPred.lookups 2407 # Number of BP lookups system.cpu.branchPred.condPredicted 1979 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect @@ -283,6 +285,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 19908000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 39817 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -572,6 +575,7 @@ system.cpu.int_regfile_reads 13370 # nu system.cpu.int_regfile_writes 7150 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 64.466372 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2199 # Total number of references to valid blocks. @@ -587,6 +591,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5374 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5374 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 1477 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1477 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits @@ -681,6 +686,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81139.403846 system.cpu.dcache.demand_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81139.403846 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 81139.403846 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 169.073673 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1420 # Total number of references to valid blocks. @@ -696,6 +702,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 163 system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4061 # Number of tag accesses system.cpu.icache.tags.data_accesses 4061 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 1420 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1420 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1420 # number of demand (read+write) hits @@ -768,6 +775,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75925.714286 system.cpu.icache.demand_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75925.714286 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 75925.714286 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 199.665471 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8 # Total number of references to valid blocks. @@ -785,6 +793,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::1 197 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4075 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4075 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 6 # number of ReadCleanReq hits system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits @@ -915,6 +924,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution @@ -944,6 +954,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 523500 # La system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 153000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 19908000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 396 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 5dd437e9a..7771c9798 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 887311 # Simulator instruction rate (inst/s) -host_op_rate 885785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 442112700 # Simulator tick rate (ticks/s) -host_mem_usage 234416 # Number of bytes of host memory used +host_inst_rate 806520 # Simulator instruction rate (inst/s) +host_op_rate 805428 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 402167874 # Simulator tick rate (ticks/s) +host_mem_usage 277804 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory system.physmem.bytes_read::total 26892 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 1453383978 # Wr system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -55,6 +57,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 2896000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 5793 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -113,6 +116,7 @@ system.cpu.op_class::MemWrite 1046 18.06% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5793 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 6754 # Transaction distribution system.membus.trans_dist::ReadResp 6754 # Transaction distribution system.membus.trans_dist::WriteReq 1046 # Transaction distribution |