diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/power')
| -rw-r--r-- | tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | 1107 |
1 files changed, 555 insertions, 552 deletions
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ca8bce664..895c59829 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,57 +1,57 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19030500 # Number of ticks simulated -final_tick 19030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18857500 # Number of ticks simulated +final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 17395 # Simulator instruction rate (inst/s) -host_op_rate 17394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57147442 # Simulator tick rate (ticks/s) -host_mem_usage 218304 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 41326 # Simulator instruction rate (inst/s) +host_op_rate 41320 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134509153 # Simulator tick rate (ticks/s) +host_mem_usage 232584 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28544 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28416 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1160242768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 339665274 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1499908042 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1160242768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1160242768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1160242768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 339665274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1499908042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 446 # Number of read requests accepted +system.physmem.num_reads::total 444 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28544 # Total read bytes from the system interface side +system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 70 # Per bank write bursts +system.physmem.perBankRdBursts::0 71 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 54 # Per bank write bursts -system.physmem.perBankRdBursts::3 59 # Per bank write bursts +system.physmem.perBankRdBursts::2 55 # Per bank write bursts +system.physmem.perBankRdBursts::3 58 # Per bank write bursts system.physmem.perBankRdBursts::4 53 # Per bank write bursts system.physmem.perBankRdBursts::5 61 # Per bank write bursts system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 13 # Per bank write bursts -system.physmem.perBankRdBursts::8 8 # Per bank write bursts +system.physmem.perBankRdBursts::7 10 # Per bank write bursts +system.physmem.perBankRdBursts::8 9 # Per bank write bursts system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 2 # Per bank write bursts +system.physmem.perBankRdBursts::10 1 # Per bank write bursts system.physmem.perBankRdBursts::11 0 # Per bank write bursts system.physmem.perBankRdBursts::12 0 # Per bank write bursts system.physmem.perBankRdBursts::13 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18902000 # Total gap between requests +system.physmem.totGap 18724000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 446 # Read request sizes (log2) +system.physmem.readPktSize::6 444 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 245 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,71 +186,72 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 77 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 342.441558 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 199.719469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 351.121005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27 35.06% 35.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18 23.38% 58.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6 7.79% 66.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 5 6.49% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5 6.49% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.60% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.90% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 14.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 77 # Bytes accessed per row activation -system.physmem.totQLat 3354000 # Total ticks spent queuing -system.physmem.totMemAccLat 11716500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7520.18 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation +system.physmem.totQLat 3609000 # Total ticks spent queuing +system.physmem.totMemAccLat 11934000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8128.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26270.18 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1499.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26878.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1499.91 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.72 # Data bus utilization in percentage -system.physmem.busUtilRead 11.72 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.77 # Data bus utilization in percentage +system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads +system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42381.17 # Average gap between requests -system.physmem.pageHitRate 80.27 # Row buffer hit rate, read and write combined +system.physmem.avgGap 42171.17 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1499908042 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 399 # Transaction distribution -system.membus.trans_dist::ReadResp 399 # Transaction distribution +system.membus.throughput 1506880552 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 397 # Transaction distribution +system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28544 # Total data (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 28416 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4177750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 22.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2252 # Number of BP lookups -system.cpu.branchPred.condPredicted 1816 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1865 # Number of BTB lookups -system.cpu.branchPred.BTBHits 610 # Number of BTB hits +system.cpu.branchPred.lookups 2332 # Number of BP lookups +system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups +system.cpu.branchPred.BTBHits 661 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.707775 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -270,235 +271,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 38062 # number of cpu cycles simulated +system.cpu.numCycles 37716 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7462 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13226 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2252 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 809 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2276 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1296 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 871 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1823 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.152492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.564431 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9200 80.17% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 1.55% 81.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 178 1.55% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 145 1.26% 84.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 228 1.99% 86.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 133 1.16% 87.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 261 2.27% 89.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 110 0.96% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1043 9.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11476 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.059167 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.347486 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7479 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1089 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2174 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 714 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 154 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11804 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 436 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 714 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7660 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 212 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 446 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2016 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 428 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11368 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 165 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 241 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9753 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18286 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18260 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1951 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1916 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4755 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 259 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2025 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1841 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 53 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10356 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8929 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 241 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4296 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3542 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.778059 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.545863 # Number of insts issued each cycle +system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8265 72.02% 72.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1011 8.81% 80.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 683 5.95% 86.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 469 4.09% 90.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 473 4.12% 94.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 313 2.73% 97.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 182 1.59% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.38% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11476 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 6.21% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 75 42.37% 48.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91 51.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5495 61.54% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1798 20.14% 81.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1634 18.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8929 # Type of FU issued -system.cpu.iq.rate 0.234591 # Inst issue rate -system.cpu.iq.fu_busy_cnt 177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019823 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29690 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14680 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9108 # Type of FU issued +system.cpu.iq.rate 0.241489 # Inst issue rate +system.cpu.iq.fu_busy_cnt 251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9072 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1064 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 795 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 714 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 160 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 48 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10413 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2025 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1841 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 262 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 328 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8526 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1682 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3211 # number of memory reference insts executed -system.cpu.iew.exec_branches 1353 # Number of branches executed -system.cpu.iew.exec_stores 1529 # Number of stores executed -system.cpu.iew.exec_rate 0.224003 # Inst execution rate -system.cpu.iew.wb_sent 8294 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8178 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4388 # num instructions producing a value -system.cpu.iew.wb_consumers 6958 # num instructions consuming a value +system.cpu.iew.exec_refs 3329 # number of memory reference insts executed +system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_stores 1554 # Number of stores executed +system.cpu.iew.exec_rate 0.230724 # Inst execution rate +system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8300 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4483 # num instructions producing a value +system.cpu.iew.wb_consumers 7102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.214860 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.630641 # average fanout of values written-back +system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4620 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.538190 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.389247 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8538 79.33% 79.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 887 8.24% 87.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 552 5.13% 92.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 240 2.23% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.64% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.89% 97.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 1.10% 98.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 47 0.44% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -544,148 +547,148 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21067 # The number of ROB reads -system.cpu.rob.rob_writes 21539 # The number of ROB writes -system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26586 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21861 # The number of ROB reads +system.cpu.rob.rob_writes 21469 # The number of ROB writes +system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.571478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.571478 # CPI: Total CPI of All Threads -system.cpu.ipc 0.152173 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.152173 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13502 # number of integer regfile reads -system.cpu.int_regfile_writes 7065 # number of integer regfile writes +system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads +system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13743 # number of integer regfile reads +system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1523449200 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution +system.cpu.toL2Bus.throughput 1530637677 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 906 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22464 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28992 # Total data (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 28864 # Total data (bytes) system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 226500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 588250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 169.076059 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1380 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.931624 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 169.076059 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082557 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082557 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 351 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.171387 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 3997 # Number of tag accesses -system.cpu.icache.tags.data_accesses 3997 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1380 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1380 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1380 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1380 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1380 # number of overall hits -system.cpu.icache.overall_hits::total 1380 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 443 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 443 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 443 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 443 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 443 # number of overall misses -system.cpu.icache.overall_misses::total 443 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29586250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29586250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29586250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29586250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29586250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29586250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1823 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1823 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1823 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1823 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1823 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.243006 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.243006 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.243006 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.243006 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.243006 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.243006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66786.117381 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66786.117381 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66786.117381 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66786.117381 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66786.117381 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 460 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4007 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits +system.cpu.icache.overall_hits::total 1391 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses +system.cpu.icache.overall_misses::total 438 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 76.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 92 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 92 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24098750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24098750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24098750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24098750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24098750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24098750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.192540 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.192540 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.192540 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.192540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68657.407407 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68657.407407 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68657.407407 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68657.407407 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # 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average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56057.246377 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63980.198020 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57851.457399 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 63.722947 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2180 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.372549 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 63.722947 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015557 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015557 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5332 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5332 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1465 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1465 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2180 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2180 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2180 # number of overall hits -system.cpu.dcache.overall_hits::total 2180 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses -system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7380250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7380250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21128996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21128996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28509246 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28509246 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28509246 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28509246 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits +system.cpu.dcache.overall_hits::total 2261 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses +system.cpu.dcache.overall_misses::total 452 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066284 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066284 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166348 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166348 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166348 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166348 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70963.942308 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70963.942308 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63833.824773 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63833.824773 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65538.496552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65538.496552 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65538.496552 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 492 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 98.400000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -890,30 +893,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4139250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4139250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3677248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3677248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7816498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7816498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7816498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7816498 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.035054 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.035054 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.039006 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.039006 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.039006 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75259.090909 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75259.090909 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78239.319149 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78239.319149 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76632.333333 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76632.333333 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |