diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt | 236 |
1 files changed, 118 insertions, 118 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index d53327dbb..91942b523 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16783500 # Number of ticks simulated final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48421 # Simulator instruction rate (inst/s) -host_op_rate 48416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152524495 # Simulator tick rate (ticks/s) -host_mem_usage 230316 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 18770 # Simulator instruction rate (inst/s) +host_op_rate 18768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59128079 # Simulator tick rate (ticks/s) +host_mem_usage 276316 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2672750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests +system.physmem.totQLat 2671750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6318.56 # Average queueing delay per request +system.physmem.avgQLat 6316.19 # Average queueing delay per request system.physmem.avgBankLat 19406.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30724.59 # Average memory access latency +system.physmem.avgMemAccLat 30722.22 # Average memory access latency system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s @@ -202,7 +202,7 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed @@ -225,12 +225,12 @@ system.cpu.cpi_total 6.301483 # CP system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). @@ -241,50 +241,50 @@ system.cpu.stage4.idleCycles 30411 # Nu system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use -system.cpu.icache.total_refs 895 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use +system.cpu.icache.total_refs 896 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits -system.cpu.icache.overall_hits::total 895 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits +system.cpu.icache.overall_hits::total 896 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18997500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18997500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18997500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18997500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18997500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18997500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52479.281768 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52479.281768 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52479.281768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52479.281768 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,32 +305,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15424000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15424000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53003.436426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53003.436426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.396977 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 140.660763 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy @@ -355,16 +355,16 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15105500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3319000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8029000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15105500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8029000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) @@ -388,16 +388,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52268.166090 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62622.641509 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -419,16 +419,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2664291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14191519 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6384078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17911306 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6384078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17911306 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -441,16 +441,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50269.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41495.669591 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use @@ -477,14 +477,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3817500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25629500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25629500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25629500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25629500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -501,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62581.967213 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62581.967213 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54070.675105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54070.675105 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked @@ -533,14 +533,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3385500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3385500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8179000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8179000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |