diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/sparc/linux/simple-timing')
4 files changed, 0 insertions, 894 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini deleted file mode 100644 index 48a2ce7b0..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ /dev/null @@ -1,382 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=hello -cwd= -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr deleted file mode 100755 index c0b55d123..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr +++ /dev/null @@ -1,3 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout deleted file mode 100755 index 55314358f..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 18:41:19 -gem5 started Apr 3 2017 18:41:41 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64913 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing - -Global frequency set at 1000000000000 ticks per second -Hello World!Exiting @ tick 30915500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt deleted file mode 100644 index 058393673..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ /dev/null @@ -1,497 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 -sim_ticks 30915500 -final_tick 30915500 -sim_freq 1000000000000 -host_inst_rate 330902 -host_op_rate 330442 -host_tick_rate 1915496347 -host_mem_usage 261572 -host_seconds 0.02 -sim_insts 5327 -sim_ops 5327 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 -system.physmem.bytes_read::cpu.inst 16320 -system.physmem.bytes_read::cpu.data 8576 -system.physmem.bytes_read::total 24896 -system.physmem.bytes_inst_read::cpu.inst 16320 -system.physmem.bytes_inst_read::total 16320 -system.physmem.num_reads::cpu.inst 255 -system.physmem.num_reads::cpu.data 134 -system.physmem.num_reads::total 389 -system.physmem.bw_read::cpu.inst 527890540 -system.physmem.bw_read::cpu.data 277401304 -system.physmem.bw_read::total 805291844 -system.physmem.bw_inst_read::cpu.inst 527890540 -system.physmem.bw_inst_read::total 527890540 -system.physmem.bw_total::cpu.inst 527890540 -system.physmem.bw_total::cpu.data 277401304 -system.physmem.bw_total::total 805291844 -system.pwrStateResidencyTicks::UNDEFINED 30915500 -system.cpu_clk_domain.clock 500 -system.cpu.workload.numSyscalls 11 -system.cpu.pwrStateResidencyTicks::ON 30915500 -system.cpu.numCycles 61831 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 5327 -system.cpu.committedOps 5327 -system.cpu.num_int_alu_accesses 4505 -system.cpu.num_fp_alu_accesses 0 -system.cpu.num_func_calls 146 -system.cpu.num_conditional_control_insts 773 -system.cpu.num_int_insts 4505 -system.cpu.num_fp_insts 0 -system.cpu.num_int_register_reads 10598 -system.cpu.num_int_register_writes 4845 -system.cpu.num_fp_register_reads 0 -system.cpu.num_fp_register_writes 0 -system.cpu.num_mem_refs 1401 -system.cpu.num_load_insts 723 -system.cpu.num_store_insts 678 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 61831 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 1121 -system.cpu.op_class::No_OpClass 173 3.22% 3.22% -system.cpu.op_class::IntAlu 3796 70.69% 73.91% -system.cpu.op_class::IntMult 0 0.00% 73.91% -system.cpu.op_class::IntDiv 0 0.00% 73.91% -system.cpu.op_class::FloatAdd 0 0.00% 73.91% -system.cpu.op_class::FloatCmp 0 0.00% 73.91% -system.cpu.op_class::FloatCvt 0 0.00% 73.91% -system.cpu.op_class::FloatMult 0 0.00% 73.91% -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% -system.cpu.op_class::FloatDiv 0 0.00% 73.91% -system.cpu.op_class::FloatMisc 0 0.00% 73.91% -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% -system.cpu.op_class::SimdAdd 0 0.00% 73.91% -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% -system.cpu.op_class::SimdAlu 0 0.00% 73.91% -system.cpu.op_class::SimdCmp 0 0.00% 73.91% -system.cpu.op_class::SimdCvt 0 0.00% 73.91% -system.cpu.op_class::SimdMisc 0 0.00% 73.91% -system.cpu.op_class::SimdMult 0 0.00% 73.91% -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% -system.cpu.op_class::SimdShift 0 0.00% 73.91% -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% -system.cpu.op_class::MemRead 723 13.46% 87.37% -system.cpu.op_class::MemWrite 678 12.63% 100.00% -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 5370 -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 -system.cpu.dcache.tags.replacements 0 -system.cpu.dcache.tags.tagsinuse 81.942328 -system.cpu.dcache.tags.total_refs 1253 -system.cpu.dcache.tags.sampled_refs 135 -system.cpu.dcache.tags.avg_refs 9.281481 -system.cpu.dcache.tags.warmup_cycle 0 -system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 -system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 -system.cpu.dcache.tags.occ_percent::total 0.020005 -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 -system.cpu.dcache.tags.tag_accesses 2911 -system.cpu.dcache.tags.data_accesses 2911 -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 -system.cpu.dcache.ReadReq_hits::cpu.data 661 -system.cpu.dcache.ReadReq_hits::total 661 -system.cpu.dcache.WriteReq_hits::cpu.data 592 -system.cpu.dcache.WriteReq_hits::total 592 -system.cpu.dcache.demand_hits::cpu.data 1253 -system.cpu.dcache.demand_hits::total 1253 -system.cpu.dcache.overall_hits::cpu.data 1253 -system.cpu.dcache.overall_hits::total 1253 -system.cpu.dcache.ReadReq_misses::cpu.data 54 -system.cpu.dcache.ReadReq_misses::total 54 -system.cpu.dcache.WriteReq_misses::cpu.data 81 -system.cpu.dcache.WriteReq_misses::total 81 -system.cpu.dcache.demand_misses::cpu.data 135 -system.cpu.dcache.demand_misses::total 135 -system.cpu.dcache.overall_misses::cpu.data 135 -system.cpu.dcache.overall_misses::total 135 -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 -system.cpu.dcache.ReadReq_miss_latency::total 3353000 -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 -system.cpu.dcache.WriteReq_miss_latency::total 5103000 -system.cpu.dcache.demand_miss_latency::cpu.data 8456000 -system.cpu.dcache.demand_miss_latency::total 8456000 -system.cpu.dcache.overall_miss_latency::cpu.data 8456000 -system.cpu.dcache.overall_miss_latency::total 8456000 -system.cpu.dcache.ReadReq_accesses::cpu.data 715 -system.cpu.dcache.ReadReq_accesses::total 715 -system.cpu.dcache.WriteReq_accesses::cpu.data 673 -system.cpu.dcache.WriteReq_accesses::total 673 -system.cpu.dcache.demand_accesses::cpu.data 1388 -system.cpu.dcache.demand_accesses::total 1388 -system.cpu.dcache.overall_accesses::cpu.data 1388 -system.cpu.dcache.overall_accesses::total 1388 -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 -system.cpu.dcache.demand_miss_rate::total 0.097262 -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 -system.cpu.dcache.overall_miss_rate::total 0.097262 -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 -system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 -system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 -system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 -system.cpu.dcache.blocked_cycles::no_mshrs 0 -system.cpu.dcache.blocked_cycles::no_targets 0 -system.cpu.dcache.blocked::no_mshrs 0 -system.cpu.dcache.blocked::no_targets 0 -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan -system.cpu.dcache.avg_blocked_cycles::no_targets nan -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 -system.cpu.dcache.ReadReq_mshr_misses::total 54 -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 -system.cpu.dcache.WriteReq_mshr_misses::total 81 -system.cpu.dcache.demand_mshr_misses::cpu.data 135 -system.cpu.dcache.demand_mshr_misses::total 135 -system.cpu.dcache.overall_mshr_misses::cpu.data 135 -system.cpu.dcache.overall_mshr_misses::total 135 -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 -system.cpu.dcache.demand_mshr_miss_latency::total 8321000 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