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-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini63
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt370
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini6
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini4
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr4
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini42
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt10
13 files changed, 282 insertions, 267 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index 2fea3a81f..505121624 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -92,22 +92,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -123,22 +123,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -155,24 +155,24 @@ size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=10000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -182,10 +182,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -200,7 +200,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -222,15 +222,28 @@ master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[0]
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index c486c847c..ff91b8c31 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:12:48
-gem5 executing on zizzer
+gem5 compiled Nov 2 2012 11:45:16
+gem5 started Nov 2 2012 11:45:52
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 18878500 because target called exit()
+Hello World!Exiting @ tick 16286500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index 0f666ffe1..f975c5003 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,14 +1,14 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000016 # Number of seconds simulated
-sim_ticks 16282500 # Number of ticks simulated
-final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 16286500 # Number of ticks simulated
+final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46082 # Simulator instruction rate (inst/s)
-host_op_rate 46072 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 140796560 # Simulator tick rate (ticks/s)
-host_mem_usage 222960 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
+host_inst_rate 32524 # Simulator instruction rate (inst/s)
+host_op_rate 32520 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 99417983 # Simulator tick rate (ticks/s)
+host_mem_usage 221588 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 423 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady
@@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr
system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 16231000 # Total gap between requests
+system.physmem.totGap 16235000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
@@ -164,17 +164,17 @@ system.physmem.wrQLenPdf::29 0 # Wh
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2301921 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests
+system.physmem.totQLat 2302422 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests
system.physmem.totBusLat 1692000 # Total cycles spent in databus access
system.physmem.totBankLat 7308000 # Total cycles spent in bank access
-system.physmem.avgQLat 5441.89 # Average queueing delay per request
+system.physmem.avgQLat 5443.08 # Average queueing delay per request
system.physmem.avgBankLat 17276.60 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26718.49 # Average memory access latency
-system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 26719.67 # Average memory access latency
+system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 10.39 # Data bus utilization in percentage
@@ -184,44 +184,44 @@ system.physmem.readRowHits 336 # Nu
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 38371.16 # Average gap between requests
+system.physmem.avgGap 38380.61 # Average gap between requests
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 32566 # number of cpu cycles simulated
+system.cpu.numCycles 32574 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1630 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits
+system.cpu.branch_predictor.lookups 1636 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 1090 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 897 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 1343 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 584 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File
+system.cpu.branch_predictor.BTBHitPct 43.484736 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 1483 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 838 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 277 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 75.156951 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 3966 # Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 1472 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 3957 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 6202 # Number of cycles cpu stages are processed.
-system.cpu.activity 19.044402 # Percentage of cycles cpu is active
+system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 6247 # Number of cycles cpu stages are processed.
+system.cpu.activity 19.177872 # Percentage of cycles cpu is active
system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
system.cpu.comBranches 1115 # Number of Branches instructions committed
@@ -233,72 +233,72 @@ system.cpu.committedInsts 5327 # Nu
system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
-system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use
-system.cpu.icache.total_refs 814 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use
+system.cpu.icache.total_refs 896 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits
-system.cpu.icache.overall_hits::total 814 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses
-system.cpu.icache.overall_misses::total 364 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -307,12 +307,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
@@ -325,12 +325,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
@@ -339,14 +339,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
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system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
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@@ -363,14 +363,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n
system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
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system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
@@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499
system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
@@ -421,12 +421,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 135
system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
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@@ -437,22 +437,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262
system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
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system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
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@@ -478,14 +478,14 @@ system.cpu.l2cache.overall_misses::total 423 # nu
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles
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@@ -511,14 +511,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.992958 #
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@@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
@@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index a6a41648e..5620e85e4 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -82,7 +82,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -106,7 +106,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 3e672ef03..3359de27e 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:12:59
-gem5 executing on zizzer
+gem5 compiled Nov 2 2012 11:45:16
+gem5 started Nov 2 2012 11:46:02
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index 9a9c3bf56..a4c6ca2b7 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 126208 # Simulator instruction rate (inst/s)
-host_op_rate 126157 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63788253 # Simulator tick rate (ticks/s)
-host_mem_usage 221040 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
+host_inst_rate 63026 # Simulator instruction rate (inst/s)
+host_op_rate 63015 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 31868954 # Simulator tick rate (ticks/s)
+host_mem_usage 212680 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 61c642df2..ab18e451d 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -106,7 +106,7 @@ version=0
[system.dir_cntrl0.directory]
type=RubyDirectoryMemory
map_levels=4
-numa_high_bit=6
+numa_high_bit=5
size=134217728
use_map=false
version=0
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index e45cd058f..5da3f0737 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -1,2 +1,6 @@
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index d65bb97a2..18fb5a397 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
-Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 9 2012 13:47:14
-gem5 started Sep 9 2012 13:47:33
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Nov 2 2012 11:45:16
+gem5 started Nov 2 2012 11:45:52
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 59ceed6d6..0ee67c488 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 10153 # Simulator instruction rate (inst/s)
-host_op_rate 10153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 205737 # Simulator tick rate (ticks/s)
-host_mem_usage 240612 # Number of bytes of host memory used
-host_seconds 0.52 # Real time elapsed on the host
+host_inst_rate 33106 # Simulator instruction rate (inst/s)
+host_op_rate 33103 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 670773 # Simulator tick rate (ticks/s)
+host_mem_usage 232832 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 135ea172c..bf88dfd5e 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
@@ -61,22 +61,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=262144
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -92,22 +92,22 @@ type=BaseCache
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=1000
+response_latency=2
size=131072
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
@@ -124,24 +124,24 @@ size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
prioritizeRequests=false
repl=Null
-response_latency=10000
+response_latency=20
size=2097152
subblock_size=0
system=system
-tgts_per_mshr=5
+tgts_per_mshr=12
trace_addr=0
two_queue=false
write_buffers=8
@@ -151,10 +151,10 @@ mem_side=system.membus.slave[1]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
@@ -169,7 +169,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
@@ -193,7 +193,7 @@ slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 2fc16fb0f..ff092cd6d 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:13:07
-gem5 executing on zizzer
+gem5 compiled Nov 2 2012 11:45:16
+gem5 started Nov 2 2012 11:46:02
+gem5 executing on u200540-lin
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 29527000 because target called exit()
+Hello World!Exiting @ tick 27800000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index 37ab13bca..df9fd5f9b 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 251441 # Simulator instruction rate (inst/s)
-host_op_rate 251244 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1310200039 # Simulator tick rate (ticks/s)
-host_mem_usage 220428 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 85623 # Simulator instruction rate (inst/s)
+host_op_rate 85602 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 446634768 # Simulator tick rate (ticks/s)
+host_mem_usage 221096 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory