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-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini61
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt289
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini12
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini1
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats20
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt10
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini29
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt206
13 files changed, 336 insertions, 334 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index 505121624..a9336e1ed 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,18 +31,13 @@ system_port=system.membus.slave[0]
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
@@ -57,16 +53,9 @@ dtb=system.cpu.dtb
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
@@ -75,11 +64,11 @@ memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
@@ -87,6 +76,24 @@ workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
@@ -94,21 +101,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -125,21 +127,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -148,6 +145,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -159,21 +159,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -200,7 +195,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index ff91b8c31..7978eda39 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:02
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index f975c5003..0a19f6727 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000016 # Nu
sim_ticks 16286500 # Number of ticks simulated
final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32524 # Simulator instruction rate (inst/s)
-host_op_rate 32520 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 99417983 # Simulator tick rate (ticks/s)
-host_mem_usage 221588 # Number of bytes of host memory used
+host_inst_rate 32843 # Simulator instruction rate (inst/s)
+host_op_rate 32839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100387600 # Simulator tick rate (ticks/s)
+host_mem_usage 278524 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
@@ -185,18 +185,19 @@ system.physmem.writeRowHits 0 # Nu
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 38380.61 # Average gap between requests
+system.cpu.branchPred.lookups 1636 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 584 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 32574 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1636 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1090 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 897 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1343 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 584 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 43.484736 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
@@ -256,19 +257,19 @@ system.cpu.stage4.runCycles 3157 # Nu
system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use
-system.cpu.icache.total_refs 896 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 895 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits
-system.cpu.icache.overall_hits::total 896 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits
+system.cpu.icache.overall_hits::total 895 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
@@ -281,18 +282,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18347500
system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency
@@ -325,12 +326,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
@@ -338,112 +339,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
-system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
-system.cpu.dcache.overall_hits::total 914 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
-system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
@@ -572,5 +467,111 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
+system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
+system.cpu.dcache.overall_hits::total 914 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses
+system.cpu.dcache.overall_misses::total 474 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 5620e85e4..d5e3e4b20 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -15,6 +15,7 @@ init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -43,6 +44,7 @@ fastmem=false
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -53,6 +55,7 @@ profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
@@ -67,6 +70,9 @@ size=64
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -82,7 +88,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 3359de27e..805340a73 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:14
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index a4c6ca2b7..bd3dfe2fe 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63026 # Simulator instruction rate (inst/s)
-host_op_rate 63015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31868954 # Simulator tick rate (ticks/s)
-host_mem_usage 212680 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 73566 # Simulator instruction rate (inst/s)
+host_op_rate 73547 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37192728 # Simulator tick rate (ticks/s)
+host_mem_usage 269044 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index f73262840..d14b371f2 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -32,6 +32,7 @@ system_port=system.sys_port_proxy.slave[0]
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index c5c22fe69..1fd961fd8 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Jan/14/2013 08:36:36
+Real time: Jan/23/2013 16:01:36
Profiler Stats
--------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.57
-Virtual_time_in_minutes: 0.0095
-Virtual_time_in_hours: 0.000158333
-Virtual_time_in_days: 6.59722e-06
+Virtual_time_in_seconds: 0.47
+Virtual_time_in_minutes: 0.00783333
+Virtual_time_in_hours: 0.000130556
+Virtual_time_in_days: 5.43981e-06
Ruby_current_time: 107952
Ruby_start_time: 0
Ruby_cycles: 107952
-mbytes_resident: 55.6602
-mbytes_total: 282.727
-resident_ratio: 0.196911
+mbytes_resident: 57.3125
+mbytes_total: 282.734
+resident_ratio: 0.202749
ruby_cycles_executed: [ 107953 ]
@@ -86,11 +86,11 @@ Resource Usage
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11405
+page_reclaims: 10848
page_faults: 0
swaps: 0
block_inputs: 0
-block_outputs: 88
+block_outputs: 96
Network Stats
-------------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index 18fb5a397..34599be55 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 78e09ef17..ce6a7813a 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 20687 # Simulator instruction rate (inst/s)
-host_op_rate 20685 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 419155 # Simulator tick rate (ticks/s)
-host_mem_usage 289516 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
+host_inst_rate 30407 # Simulator instruction rate (inst/s)
+host_op_rate 30404 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 616066 # Simulator tick rate (ticks/s)
+host_mem_usage 289524 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index bf88dfd5e..3ba498627 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -14,7 +14,8 @@ clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
@@ -30,11 +31,11 @@ system_port=system.membus.slave[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -42,6 +43,7 @@ dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
@@ -50,6 +52,7 @@ max_loads_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -63,21 +66,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
@@ -94,21 +92,16 @@ assoc=2
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
@@ -117,6 +110,9 @@ mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
@@ -128,21 +124,16 @@ assoc=8
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
@@ -169,7 +160,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index ff092cd6d..411439c6e 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,9 +1,11 @@
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index df9fd5f9b..4cc5c5030 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85623 # Simulator instruction rate (inst/s)
-host_op_rate 85602 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 446634768 # Simulator tick rate (ticks/s)
-host_mem_usage 221096 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 116604 # Simulator instruction rate (inst/s)
+host_op_rate 116555 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 608021957 # Simulator tick rate (ticks/s)
+host_mem_usage 277492 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
@@ -128,104 +128,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
-system.cpu.dcache.overall_hits::total 1253 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
-system.cpu.dcache.overall_misses::total 135 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 142.183999 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
@@ -354,5 +256,103 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020048 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
+system.cpu.dcache.overall_hits::total 1253 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses
+system.cpu.dcache.overall_misses::total 135 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------