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-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt460
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini4
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout6
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt76
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout6
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt64
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini2
-rwxr-xr-xtests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt186
12 files changed, 412 insertions, 412 deletions
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index dd53d4220..9d387b483 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -214,7 +214,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index a234b881d..c486c847c 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:54:18
-gem5 started Jul 2 2012 11:30:03
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:12:48
gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 18885500 because target called exit()
+Hello World!Exiting @ tick 18878500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
index fa8b51b5a..00104c1c9 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000019 # Number of seconds simulated
-sim_ticks 18885500 # Number of ticks simulated
-final_tick 18885500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 18878500 # Number of ticks simulated
+final_tick 18878500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 37135 # Simulator instruction rate (inst/s)
-host_op_rate 37131 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 131302803 # Simulator tick rate (ticks/s)
-host_mem_usage 220012 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
-sim_insts 5340 # Number of instructions simulated
-sim_ops 5340 # Number of ops (including micro ops) simulated
+host_inst_rate 36734 # Simulator instruction rate (inst/s)
+host_op_rate 36730 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 130153209 # Simulator tick rate (ticks/s)
+host_mem_usage 229488 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
+sim_insts 5327 # Number of instructions simulated
+sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 27072 # Number of bytes read from this memory
@@ -19,134 +19,134 @@ system.physmem.bytes_inst_read::total 18496 # Nu
system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 423 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 979375712 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 454105001 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1433480713 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 979375712 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 979375712 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 979375712 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 454105001 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1433480713 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 979738856 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 454273380 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1434012236 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 979738856 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 979738856 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 979738856 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 454273380 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1434012236 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 37772 # number of cpu cycles simulated
+system.cpu.numCycles 37758 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1615 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1170 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits
+system.cpu.branch_predictor.lookups 1630 # Number of BP lookups
+system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits
system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 37.179487 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken 1113 # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.branch_predictor.BTBHitPct 37.596567 # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken 1125 # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads 5623 # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses 9611 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards 1686 # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens 1487 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 319 # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect 517 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions 3979 # Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards 1685 # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens 1483 # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted 838 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 277 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 75.156951 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions 3966 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 10178 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 10163 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 31527 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 6245 # Number of cycles cpu stages are processed.
-system.cpu.activity 16.533411 # Percentage of cycles cpu is active
-system.cpu.comLoads 716 # Number of Load instructions committed
+system.cpu.timesIdled 500 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 31528 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 6230 # Number of cycles cpu stages are processed.
+system.cpu.activity 16.499815 # Percentage of cycles cpu is active
+system.cpu.comLoads 715 # Number of Load instructions committed
system.cpu.comStores 673 # Number of Store instructions committed
-system.cpu.comBranches 1116 # Number of Branches instructions committed
+system.cpu.comBranches 1115 # Number of Branches instructions committed
system.cpu.comNops 173 # Number of Nop instructions committed
system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
-system.cpu.comInts 2537 # Number of Integer instructions committed
+system.cpu.comInts 2526 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
-system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread)
+system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total)
-system.cpu.cpi 7.073408 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total)
+system.cpu.cpi 7.088042 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
-system.cpu.cpi_total 7.073408 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.141375 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total 7.088042 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.141083 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
-system.cpu.ipc_total 0.141375 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 33203 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 4569 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 12.096262 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 34575 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 8.463942 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 34722 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 8.074764 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles 36789 # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization 2.602457 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 34600 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 3172 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 8.397755 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total 0.141083 # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles 33195 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 4563 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 12.084856 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 34564 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 8.459134 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 34714 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 8.061868 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles 36776 # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization 2.600773 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 34592 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 3166 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 8.384978 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 136.494329 # Cycle average of tags in use
-system.cpu.icache.total_refs 825 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 136.498326 # Cycle average of tags in use
+system.cpu.icache.total_refs 829 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 2.835052 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 136.494329 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.066648 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.066648 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 825 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 825 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 825 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 825 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 825 # number of overall hits
-system.cpu.icache.overall_hits::total 825 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 136.498326 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.066650 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.066650 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits
+system.cpu.icache.overall_hits::total 829 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
system.cpu.icache.overall_misses::total 350 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 19647000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 19647000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 19647000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 19647000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 19647000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 19647000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1175 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1175 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1175 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1175 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1175 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1175 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297872 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.297872 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.297872 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.297872 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.297872 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.297872 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56134.285714 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56134.285714 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56134.285714 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56134.285714 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 19654500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 19654500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 19654500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 19654500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 19654500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 19654500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1179 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1179 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1179 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1179 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1179 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1179 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.296862 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.296862 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.296862 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.296862 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.296862 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.296862 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56155.714286 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56155.714286 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56155.714286 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56155.714286 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56155.714286 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets 109000 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits
@@ -161,42 +161,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291
system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54500 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54734.567901 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54734.567901 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54544.917258 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54166.089965 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55361.940299 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54544.917258 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14483000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14482000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5798000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 17937500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5798000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 17937500 # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5797500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17936500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5797500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17936500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses
@@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42005.190311 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44216.981132 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42347.953216 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42003.460208 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44207.547170 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42345.029240 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42003.460208 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43264.925373 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42403.073286 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index 9462bf460..69d80e31f 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -99,8 +99,8 @@ block_size=64
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index a096c2705..3e672ef03 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 12:01:47
-gem5 started Jun 4 2012 14:44:41
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:12:59
gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 2701000 because target called exit()
+Hello World!Exiting @ tick 2694500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
index c78599e75..9a9c3bf56 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
@@ -1,59 +1,59 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000003 # Number of seconds simulated
-sim_ticks 2701000 # Number of ticks simulated
-final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2694500 # Number of ticks simulated
+final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 947128 # Simulator instruction rate (inst/s)
-host_op_rate 944143 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 476131381 # Simulator tick rate (ticks/s)
-host_mem_usage 212364 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-sim_insts 5340 # Number of instructions simulated
-sim_ops 5340 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21532 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 4603 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26135 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21532 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21532 # Number of instructions bytes read from this memory
+host_inst_rate 126208 # Simulator instruction rate (inst/s)
+host_op_rate 126157 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63788253 # Simulator tick rate (ticks/s)
+host_mem_usage 221040 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
+sim_insts 5327 # Number of instructions simulated
+sim_ops 5327 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26082 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21480 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21480 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory
system.physmem.bytes_written::total 5065 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5383 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 716 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6099 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 5370 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 715 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6085 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory
system.physmem.num_writes::total 673 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7971862273 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1704183636 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9676045909 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7971862273 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7971862273 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1875231396 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1875231396 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7971862273 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3579415031 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11551277305 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 7971794396 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1707923548 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 9679717944 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 7971794396 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 7971794396 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1879755057 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1879755057 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 5403 # number of cpu cycles simulated
+system.cpu.numCycles 5390 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5340 # Number of instructions committed
-system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
+system.cpu.committedInsts 5327 # Number of instructions committed
+system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4517 # number of integer instructions
+system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4505 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4859 # number of times the integer registers were written
+system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4846 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1402 # number of memory refs
-system.cpu.num_load_insts 724 # Number of load instructions
+system.cpu.num_mem_refs 1401 # number of memory refs
+system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 5403 # Number of busy cycles
+system.cpu.num_busy_cycles 5390 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index 671f90296..631d050da 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -78,7 +78,7 @@ egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index f8d1a8b44..b90476d27 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -1,9 +1,9 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 10 2012 17:56:55
-gem5 started Jul 10 2012 17:57:35
-gem5 executing on sc2b0605
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:09
+gem5 executing on zizzer
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 4bb30bdf1..4125da946 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,35 +4,35 @@ sim_seconds 0.000253 # Nu
sim_ticks 253364 # Number of ticks simulated
final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 42932 # Simulator instruction rate (inst/s)
-host_op_rate 42926 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2036393 # Simulator tick rate (ticks/s)
-host_mem_usage 243564 # Number of bytes of host memory used
-host_seconds 0.12 # Real time elapsed on the host
-sim_insts 5340 # Number of instructions simulated
-sim_ops 5340 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst 21532 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 4603 # Number of bytes read from this memory
-system.physmem.bytes_read::total 26135 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 21532 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 21532 # Number of instructions bytes read from this memory
+host_inst_rate 38246 # Simulator instruction rate (inst/s)
+host_op_rate 38242 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1818652 # Simulator tick rate (ticks/s)
+host_mem_usage 240496 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+sim_insts 5327 # Number of instructions simulated
+sim_ops 5327 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory
+system.physmem.bytes_read::total 26082 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 21480 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 21480 # Number of instructions bytes read from this memory
system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory
system.physmem.bytes_written::total 5065 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 5383 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 716 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6099 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 5370 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 715 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 6085 # Number of read requests responded to by this memory
system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory
system.physmem.num_writes::total 673 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 84984449 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 18167538 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 103151987 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 84984449 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 84984449 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 84779211 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 18163591 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 102942802 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 84779211 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 84779211 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 19991001 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 19991001 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 84984449 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 38158539 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 123142988 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 84779211 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 38154592 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 122933803 # Total bandwidth to/from this memory (bytes/s)
system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads
@@ -43,20 +43,20 @@ system.cpu.workload.num_syscalls 11 # Nu
system.cpu.numCycles 253364 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5340 # Number of instructions committed
-system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
+system.cpu.committedInsts 5327 # Number of instructions committed
+system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4517 # number of integer instructions
+system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4505 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
+system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1402 # number of memory refs
-system.cpu.num_load_insts 724 # Number of load instructions
+system.cpu.num_mem_refs 1401 # number of memory refs
+system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 253364 # Number of busy cycles
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 53f402a63..62c147fd5 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -181,7 +181,7 @@ clock=1000
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 81bff15c4..2fc16fb0f 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:54:18
-gem5 started Jul 2 2012 11:30:26
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:07
gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 29541000 because target called exit()
+Hello World!Exiting @ tick 29527000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
index d0e2c9d97..3eb56a69e 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29541000 # Number of ticks simulated
-final_tick 29541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 29527000 # Number of ticks simulated
+final_tick 29527000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 73924 # Simulator instruction rate (inst/s)
-host_op_rate 73907 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 408761366 # Simulator tick rate (ticks/s)
-host_mem_usage 220016 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-sim_insts 5340 # Number of instructions simulated
-sim_ops 5340 # Number of ops (including micro ops) simulated
+host_inst_rate 69145 # Simulator instruction rate (inst/s)
+host_op_rate 69130 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 383102769 # Simulator tick rate (ticks/s)
+host_mem_usage 229488 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
+sim_insts 5327 # Number of instructions simulated
+sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory
system.physmem.bytes_read::total 24896 # Number of bytes read from this memory
@@ -19,52 +19,52 @@ system.physmem.bytes_inst_read::total 16320 # Nu
system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory
system.physmem.num_reads::total 389 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 552452524 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 290308385 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 842760909 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 552452524 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 552452524 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 552452524 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 290308385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 842760909 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 552714465 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 290446032 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 843160497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 552714465 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 552714465 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 552714465 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 290446032 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 843160497 # Total bandwidth to/from this memory (bytes/s)
system.cpu.workload.num_syscalls 11 # Number of system calls
-system.cpu.numCycles 59082 # number of cpu cycles simulated
+system.cpu.numCycles 59054 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 5340 # Number of instructions committed
-system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
+system.cpu.committedInsts 5327 # Number of instructions committed
+system.cpu.committedOps 5327 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4517 # number of integer instructions
+system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls
+system.cpu.num_int_insts 4505 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 10620 # number of times the integer registers were read
-system.cpu.num_int_register_writes 4858 # number of times the integer registers were written
+system.cpu.num_int_register_reads 10598 # number of times the integer registers were read
+system.cpu.num_int_register_writes 4845 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 1402 # number of memory refs
-system.cpu.num_load_insts 724 # Number of load instructions
+system.cpu.num_mem_refs 1401 # number of memory refs
+system.cpu.num_load_insts 723 # Number of load instructions
system.cpu.num_store_insts 678 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_busy_cycles 59082 # Number of busy cycles
+system.cpu.num_busy_cycles 59054 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 117.079183 # Cycle average of tags in use
-system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 117.127109 # Cycle average of tags in use
+system.cpu.icache.total_refs 5114 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 19.898833 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 117.079183 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.057168 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.057168 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits
-system.cpu.icache.overall_hits::total 5127 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 117.127109 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.057191 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.057191 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits
+system.cpu.icache.overall_hits::total 5114 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
@@ -77,18 +77,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 14308000
system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.047734 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.047734 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.047734 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.047850 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
@@ -115,12 +115,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000
system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047734 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.047734 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.047734 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
@@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 82.107175 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 82.138993 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 9.281481 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 82.107175 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020046 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020046 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 82.138993 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020053 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020053 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits
-system.cpu.dcache.overall_hits::total 1254 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits
+system.cpu.dcache.overall_hits::total 1253 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses
@@ -161,22 +161,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7518000
system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.075419 # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.097192 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.097192 # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000
system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889
system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 142.223187 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 142.279716 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 116.548564 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 25.674623 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.003557 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst 116.596239 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 25.683477 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.003558 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.004340 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.004342 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits