diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt | 942 |
1 files changed, 471 insertions, 471 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b16a10afa..d0e4f2a16 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,272 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12198000 # Number of ticks simulated -final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12803000 # Number of ticks simulated +final_tick 12803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39950 # Simulator instruction rate (inst/s) -host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89952499 # Simulator tick rate (ticks/s) -host_mem_usage 224288 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 24032 # Simulator instruction rate (inst/s) +host_op_rate 43521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56800152 # Simulator tick rate (ticks/s) +host_mem_usage 227452 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory -system.physmem.bytes_read::total 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1504647348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 724830118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229477466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1504647348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1504647348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1504647348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 724830118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229477466 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24397 # number of cpu cycles simulated +system.cpu.numCycles 25607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3206 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits +system.cpu.BPredUnit.lookups 3125 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3125 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2605 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 830 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched +system.cpu.fetch.icacheStallCycles 8034 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3125 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 830 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4070 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2483 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3408 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 244 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1957 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 17679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.502687 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.975668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13710 77.55% 77.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 177 1.00% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.93% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 211 1.19% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 170 0.96% 81.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 182 1.03% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 260 1.47% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 162 0.92% 85.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2643 14.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3749 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3522 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 17679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.585035 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8588 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1882 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25327 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1882 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8910 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 505 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3461 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23802 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 747 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 70488 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 70472 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 34224 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 68607 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 68591 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 19517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 35 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1875 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1775 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10865 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19620 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.994513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.826049 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12114 68.52% 68.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1582 8.95% 77.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1012 5.72% 83.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 689 3.90% 87.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 696 3.94% 91.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 692 3.91% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 627 3.55% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 233 1.32% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17679 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133 73.08% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 29 15.93% 89.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14185 80.68% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1924 10.94% 91.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1469 8.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17854 # Type of FU issued -system.cpu.iq.rate 0.731811 # Inst issue rate -system.cpu.iq.fu_busy_cnt 191 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17582 # Type of FU issued +system.cpu.iq.rate 0.686609 # Inst issue rate +system.cpu.iq.fu_busy_cnt 182 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53109 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32144 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16183 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17756 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 148 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1250 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 841 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1882 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1425 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21272 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2306 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 36 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 640 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16602 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3203 # number of memory reference insts executed -system.cpu.iew.exec_branches 1645 # Number of branches executed -system.cpu.iew.exec_stores 1359 # Number of stores executed -system.cpu.iew.exec_rate 0.689593 # Inst execution rate -system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16406 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10679 # num instructions producing a value -system.cpu.iew.wb_consumers 24448 # num instructions consuming a value +system.cpu.iew.exec_refs 3144 # number of memory reference insts executed +system.cpu.iew.exec_branches 1642 # Number of branches executed +system.cpu.iew.exec_stores 1350 # Number of stores executed +system.cpu.iew.exec_rate 0.648338 # Inst execution rate +system.cpu.iew.wb_sent 16384 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16187 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10480 # num instructions producing a value +system.cpu.iew.wb_consumers 24095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.632132 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.434945 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 589 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15797 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.620941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.463366 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12065 76.38% 76.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1534 9.71% 86.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 576 3.65% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 731 4.63% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 367 2.32% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.82% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 134 0.85% 98.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 75 0.47% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 186 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15797 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,68 +277,68 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 186 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36362 # The number of ROB reads -system.cpu.rob.rob_writes 45397 # The number of ROB writes -system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36882 # The number of ROB reads +system.cpu.rob.rob_writes 44457 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 35460 # number of integer regfile reads -system.cpu.int_regfile_writes 22063 # number of integer regfile writes +system.cpu.cpi 4.728028 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.728028 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211505 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211505 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 35136 # number of integer regfile reads +system.cpu.int_regfile_writes 21832 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7402 # number of misc regfile reads +system.cpu.misc_regfile_reads 7303 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use -system.cpu.icache.total_refs 1561 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 144.987593 # Cycle average of tags in use +system.cpu.icache.total_refs 1569 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 302 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.195364 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1561 # number of overall hits -system.cpu.icache.overall_hits::total 1561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 390 # number of overall misses -system.cpu.icache.overall_misses::total 390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 144.987593 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070795 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070795 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1569 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1569 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1569 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1569 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1569 # number of overall hits +system.cpu.icache.overall_hits::total 1569 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 388 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 388 # 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mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |