diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt | 229 |
1 files changed, 117 insertions, 112 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index f27f9e229..6ad7b9146 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000107 # Nu sim_ticks 107237 # Number of ticks simulated final_tick 107237 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 14917 # Simulator instruction rate (inst/s) -host_op_rate 27022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 297251 # Simulator tick rate (ticks/s) -host_mem_usage 452416 # Number of bytes of host memory used -host_seconds 0.36 # Real time elapsed on the host +host_inst_rate 59170 # Simulator instruction rate (inst/s) +host_op_rate 107175 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1178869 # Simulator tick rate (ticks/s) +host_mem_usage 466480 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -238,29 +238,97 @@ system.mem_ctrls.readRowHitRate 64.11 # Ro system.mem_ctrls.writeRowHitRate 90.98 # Row buffer hit rate for writes system.mem_ctrls.avgGap 38.96 # Average gap between requests system.mem_ctrls.pageHitRate 77.75 # Row buffer hit rate, read and write combined -system.mem_ctrls.memoryStateTime::IDLE 6647 # Time in different power states -system.mem_ctrls.memoryStateTime::REF 3380 # Time in different power states -system.mem_ctrls.memoryStateTime::PRE_PDN 0 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT 91465 # Time in different power states -system.mem_ctrls.memoryStateTime::ACT_PDN 0 # Time in different power states -system.mem_ctrls.actEnergy::0 695520 # Energy for activate commands per rank (pJ) -system.mem_ctrls.actEnergy::1 1270080 # Energy for activate commands per rank (pJ) -system.mem_ctrls.preEnergy::0 386400 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.preEnergy::1 705600 # Energy for precharge commands per rank (pJ) -system.mem_ctrls.readEnergy::0 3219840 # Energy for read commands per rank (pJ) -system.mem_ctrls.readEnergy::1 4605120 # Energy for read commands per rank (pJ) -system.mem_ctrls.writeEnergy::0 2623104 # Energy for write commands per rank (pJ) -system.mem_ctrls.writeEnergy::1 3784320 # Energy for write commands per rank (pJ) -system.mem_ctrls.refreshEnergy::0 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.refreshEnergy::1 6611280 # Energy for refresh commands per rank (pJ) -system.mem_ctrls.actBackEnergy::0 57894444 # Energy for active background per rank (pJ) -system.mem_ctrls.actBackEnergy::1 62913636 # Energy for active background per rank (pJ) -system.mem_ctrls.preBackEnergy::0 10102200 # Energy for precharge background per rank (pJ) -system.mem_ctrls.preBackEnergy::1 5699400 # Energy for precharge background per rank (pJ) -system.mem_ctrls.totalEnergy::0 81532788 # Total energy per rank (pJ) -system.mem_ctrls.totalEnergy::1 85589436 # Total energy per rank (pJ) -system.mem_ctrls.averagePower::0 803.452847 # Core power per rank (mW) -system.mem_ctrls.averagePower::1 843.428487 # Core power per rank (mW) +system.mem_ctrls_0.actEnergy 695520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 386400 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 3219840 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 2623104 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 57895812 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 10101000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 81532956 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 803.454502 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 16443 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 81669 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1270080 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 705600 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 4605120 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 3784320 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 62916372 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 5697000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 85589772 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 843.431798 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 9164 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 89065 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.clk_domain.clock 1 # Clock period in ticks +system.cpu.apic_clk_domain.clock 16 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 107237 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5381 # Number of instructions committed +system.cpu.committedOps 9748 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 209 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls +system.cpu.num_int_insts 9654 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 18335 # number of times the integer registers were read +system.cpu.num_int_register_writes 7527 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written +system.cpu.num_mem_refs 1988 # number of memory refs +system.cpu.num_load_insts 1053 # Number of load instructions +system.cpu.num_store_insts 935 # Number of store instructions +system.cpu.num_idle_cycles 0.999991 # Number of idle cycles +system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles +system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000009 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction +system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction +system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction +system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.clk_domain.clock 1 # Clock period in ticks system.ruby.delayHist::bucket_size 1 # delay histogram for all message system.ruby.delayHist::max_bucket 9 # delay histogram for all message @@ -278,8 +346,8 @@ system.ruby.latency_hist::bucket_size 64 system.ruby.latency_hist::max_bucket 639 system.ruby.latency_hist::samples 8852 system.ruby.latency_hist::mean 11.114437 -system.ruby.latency_hist::gmean 4.638311 -system.ruby.latency_hist::stdev 22.978637 +system.ruby.latency_hist::gmean 4.638310 +system.ruby.latency_hist::stdev 22.979355 system.ruby.latency_hist | 8594 97.09% 97.09% | 215 2.43% 99.51% | 29 0.33% 99.84% | 6 0.07% 99.91% | 6 0.07% 99.98% | 2 0.02% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.latency_hist::total 8852 system.ruby.hit_latency_hist::bucket_size 1 @@ -293,16 +361,15 @@ system.ruby.miss_latency_hist::bucket_size 64 system.ruby.miss_latency_hist::max_bucket 639 system.ruby.miss_latency_hist::samples 1377 system.ruby.miss_latency_hist::mean 55.163399 -system.ruby.miss_latency_hist::gmean 49.389613 -system.ruby.miss_latency_hist::stdev 33.121212 +system.ruby.miss_latency_hist::gmean 49.389540 +system.ruby.miss_latency_hist::stdev 33.124416 system.ruby.miss_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist::total 1377 system.ruby.Directory.incomplete_times 1376 -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.cpu.clk_domain.clock 1 # Clock period in ticks +system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks system.ruby.network.routers0.percent_links_utilized 6.411034 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -338,68 +405,6 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 107237 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999991 # Number of idle cycles -system.cpu.num_busy_cycles 107236.000009 # Number of busy cycles -system.cpu.not_idle_fraction 0.999991 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000009 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction system.ruby.network.routers0.throttle0.link_utilization 6.418494 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -490,8 +495,8 @@ system.ruby.IFETCH.latency_hist::bucket_size 64 system.ruby.IFETCH.latency_hist::max_bucket 639 system.ruby.IFETCH.latency_hist::samples 6864 system.ruby.IFETCH.latency_hist::mean 8.263112 -system.ruby.IFETCH.latency_hist::gmean 3.900454 -system.ruby.IFETCH.latency_hist::stdev 20.208626 +system.ruby.IFETCH.latency_hist::gmean 3.900453 +system.ruby.IFETCH.latency_hist::stdev 20.209679 system.ruby.IFETCH.latency_hist | 6731 98.06% 98.06% | 102 1.49% 99.55% | 22 0.32% 99.87% | 3 0.04% 99.91% | 5 0.07% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.latency_hist::total 6864 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 @@ -505,8 +510,8 @@ system.ruby.IFETCH.miss_latency_hist::bucket_size 64 system.ruby.IFETCH.miss_latency_hist::max_bucket 639 system.ruby.IFETCH.miss_latency_hist::samples 623 system.ruby.IFETCH.miss_latency_hist::mean 60.987159 -system.ruby.IFETCH.miss_latency_hist::gmean 54.083768 -system.ruby.IFETCH.miss_latency_hist::stdev 37.997755 +system.ruby.IFETCH.miss_latency_hist::gmean 54.083593 +system.ruby.IFETCH.miss_latency_hist::stdev 38.003932 system.ruby.IFETCH.miss_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.miss_latency_hist::total 623 system.ruby.RMW_Read.latency_hist::bucket_size 4 @@ -536,8 +541,8 @@ system.ruby.Directory.miss_mach_latency_hist::bucket_size 64 system.ruby.Directory.miss_mach_latency_hist::max_bucket 639 system.ruby.Directory.miss_mach_latency_hist::samples 1377 system.ruby.Directory.miss_mach_latency_hist::mean 55.163399 -system.ruby.Directory.miss_mach_latency_hist::gmean 49.389613 -system.ruby.Directory.miss_mach_latency_hist::stdev 33.121212 +system.ruby.Directory.miss_mach_latency_hist::gmean 49.389540 +system.ruby.Directory.miss_mach_latency_hist::stdev 33.124416 system.ruby.Directory.miss_mach_latency_hist | 1119 81.26% 81.26% | 215 15.61% 96.88% | 29 2.11% 98.98% | 6 0.44% 99.42% | 6 0.44% 99.85% | 2 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.Directory.miss_mach_latency_hist::total 1377 system.ruby.Directory.miss_latency_hist.issue_to_initial_request::bucket_size 1 @@ -586,8 +591,8 @@ system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::bucket_size system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::max_bucket 639 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::samples 623 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::mean 60.987159 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083768 -system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 37.997755 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::gmean 54.083593 +system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::stdev 38.003932 system.ruby.IFETCH.Directory.miss_type_mach_latency_hist | 490 78.65% 78.65% | 102 16.37% 95.02% | 22 3.53% 98.56% | 3 0.48% 99.04% | 5 0.80% 99.84% | 1 0.16% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.IFETCH.Directory.miss_type_mach_latency_hist::total 623 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::bucket_size 4 @@ -598,6 +603,14 @@ system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::gmean 34.000000 system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::stdev nan system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% system.ruby.RMW_Read.Directory.miss_type_mach_latency_hist::total 1 +system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% +system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% +system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.Load 1045 0.00% 0.00% system.ruby.L1Cache_Controller.Ifetch 6864 0.00% 0.00% system.ruby.L1Cache_Controller.Store 943 0.00% 0.00% @@ -614,13 +627,5 @@ system.ruby.L1Cache_Controller.M.Replacement 1373 0.00% 0.00% system.ruby.L1Cache_Controller.MI.Writeback_Ack 1373 0.00% 0.00% system.ruby.L1Cache_Controller.IS.Data 1122 0.00% 0.00% system.ruby.L1Cache_Controller.IM.Data 255 0.00% 0.00% -system.ruby.Directory_Controller.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 1373 0.00% 0.00% -system.ruby.Directory_Controller.I.GETX 1377 0.00% 0.00% -system.ruby.Directory_Controller.M.PUTX 1373 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 1377 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 1373 0.00% 0.00% ---------- End Simulation Statistics ---------- |