diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby')
5 files changed, 56 insertions, 53 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index d97af8c71..33bd11300 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -130,7 +130,7 @@ version=0 [system.dir_cntrl0.directory] type=RubyDirectoryMemory map_levels=4 -numa_high_bit=6 +numa_high_bit=5 size=134217728 use_map=false version=0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index 5f61ae7e1..87c404fd6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -1,4 +1,4 @@ -Real time: Sep/10/2012 21:50:40 +Real time: Dec/30/2012 01:12:43 Profiler Stats -------------- @@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0 Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.48 -Virtual_time_in_minutes: 0.008 -Virtual_time_in_hours: 0.000133333 -Virtual_time_in_days: 5.55556e-06 +Virtual_time_in_seconds: 0.51 +Virtual_time_in_minutes: 0.0085 +Virtual_time_in_hours: 0.000141667 +Virtual_time_in_days: 5.90278e-06 Ruby_current_time: 121759 Ruby_start_time: 0 Ruby_cycles: 121759 -mbytes_resident: 57.9453 -mbytes_total: 275.082 -resident_ratio: 0.210662 +mbytes_resident: 60.1836 +mbytes_total: 277.391 +resident_ratio: 0.217006 ruby_cycles_executed: [ 121760 ] @@ -29,17 +29,17 @@ Directory-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8851 average: 1 | standard deviation: 0 | 0 8851 ] +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 8852 average: 1 | standard deviation: 0 | 0 8852 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 1 max: 125 count: 8850 average: 12.7581 | standard deviation: 22.8706 | 0 0 0 7473 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 1 max: 125 count: 8851 average: 12.7565 | standard deviation: 22.8681 | 0 0 0 7474 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_LD: [binsize: 1 max: 101 count: 1044 average: 33.113 | standard deviation: 31.8551 | 0 0 0 545 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ] -miss_latency_ST: [binsize: 1 max: 92 count: 934 average: 20.1188 | standard deviation: 28.2308 | 0 0 0 680 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ] -miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66288 | standard deviation: 18.0056 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 1 max: 92 count: 935 average: 20.0877 | standard deviation: 28.194 | 0 0 0 681 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ] +miss_latency_IFETCH: [binsize: 1 max: 125 count: 6864 average: 8.66404 | standard deviation: 18.01 | 0 0 0 6241 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_RMW_Read: [binsize: 1 max: 65 count: 8 average: 10.75 | standard deviation: 21.9219 | 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] -miss_latency_L1Cache: [binsize: 1 max: 3 count: 7473 average: 3 | standard deviation: 0 | 0 0 0 7473 ] -miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7153 | standard deviation: 6.33839 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 314 433 491 10 7 5 9 5 11 0 1 0 1 0 0 0 1 1 0 0 1 0 0 2 0 0 0 9 16 40 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 7474 average: 3 | standard deviation: 0 | 0 0 0 7474 ] +miss_latency_Directory: [binsize: 1 max: 125 count: 1377 average: 65.7124 | standard deviation: 6.32886 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 10 4 313 433 492 10 6 5 9 6 11 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 9 16 39 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -52,10 +52,10 @@ miss_latency_dir_first_response_to_completion: [binsize: 1 max: 61 count: 1 aver imcomplete_dir_Times: 1376 miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 545 average: 3 | standard deviation: 0 | 0 0 0 545 ] miss_latency_LD_Directory: [binsize: 1 max: 101 count: 499 average: 66.002 | standard deviation: 7.00186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 5 2 97 201 150 1 3 2 0 1 1 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 3 5 22 0 0 1 0 0 0 0 0 1 ] -miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 680 average: 3 | standard deviation: 0 | 0 0 0 680 ] -miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9488 | standard deviation: 6.5357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 2 3 9 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 681 average: 3 | standard deviation: 0 | 0 0 0 681 ] +miss_latency_ST_Directory: [binsize: 1 max: 92 count: 254 average: 65.9016 | standard deviation: 6.43269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 59 62 106 3 0 0 2 0 3 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 3 9 ] miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 6241 average: 3 | standard deviation: 0 | 0 0 0 6241 ] -miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.3917 | standard deviation: 5.66183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 158 170 234 6 4 3 7 4 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 125 count: 623 average: 65.4045 | standard deviation: 5.68761 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 157 170 235 6 3 3 7 5 7 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 8 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] miss_latency_RMW_Read_Directory: [binsize: 1 max: 65 count: 1 average: 65 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] @@ -89,10 +89,10 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11940 -page_faults: 0 +page_reclaims: 12527 +page_faults: 3 swaps: 0 -block_inputs: 24 +block_inputs: 1360 block_outputs: 88 Network Stats @@ -154,7 +154,7 @@ Cache Stats: system.l1_cntrl0.cacheMemory - Event Counts - Load [1044 ] 1044 Ifetch [6864 ] 6864 -Store [942 ] 942 +Store [943 ] 943 Data [1377 ] 1377 Fwd_GETX [0 ] 0 Inv [0 ] 0 @@ -173,7 +173,7 @@ II Writeback_Nack [0 ] 0 M Load [545 ] 545 M Ifetch [6241 ] 6241 -M Store [687 ] 687 +M Store [688 ] 688 M Fwd_GETX [0 ] 0 M Inv [0 ] 0 M Replacement [1373 ] 1373 @@ -194,16 +194,16 @@ Memory controller: system.dir_cntrl0.memBuffer: memory_reads: 1377 memory_writes: 1373 memory_refreshes: 846 - memory_total_request_delays: 1965 - memory_delays_per_request: 0.714545 + memory_total_request_delays: 1964 + memory_delays_per_request: 0.714182 memory_delays_in_input_queue: 0 - memory_delays_behind_head_of_bank_queue: 3 - memory_delays_stalled_at_head_of_bank_queue: 1962 - memory_stalls_for_bank_busy: 830 + memory_delays_behind_head_of_bank_queue: 4 + memory_delays_stalled_at_head_of_bank_queue: 1960 + memory_stalls_for_bank_busy: 826 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 memory_stalls_for_arbitration: 62 - memory_stalls_for_bus: 1039 + memory_stalls_for_bus: 1041 memory_stalls_for_tfaw: 0 memory_stalls_for_read_write_turnaround: 31 memory_stalls_for_read_read_turnaround: 0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index ac4ad20a5..723b3760f 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -1,4 +1,7 @@ +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections -warn: instruction 'fnstcw_Mw' unimplemented warn: instruction 'fldcw_Mw' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 33d7b7dce..55cf80cf6 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 21:50:34 -gem5 started Sep 10 2012 21:50:39 +gem5 compiled Dec 30 2012 00:35:18 +gem5 started Dec 30 2012 01:12:43 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 6f7115490..36958969e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,35 +4,35 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21174 # Simulator instruction rate (inst/s) -host_op_rate 38347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 479042 # Simulator tick rate (ticks/s) -host_mem_usage 281688 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 28531 # Simulator instruction rate (inst/s) +host_op_rate 51675 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 645460 # Simulator tick rate (ticks/s) +host_mem_usage 284052 # Number of bytes of host memory used +host_seconds 0.19 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated -sim_ops 9746 # Number of ops (including micro ops) simulated +sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7064 # Number of bytes read from this memory system.physmem.bytes_read::total 61976 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory -system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory +system.physmem.bytes_written::total 7112 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1052 # Number of read requests responded to by this memory system.physmem.num_reads::total 7916 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory -system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory +system.physmem.num_writes::total 935 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 450989249 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 58016245 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 509005494 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 450989249 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 450989249 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 58394041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58394041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 58410467 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58410467 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::cpu.inst 450989249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 116410286 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 567399535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 116426712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 567415961 # Total bandwidth to/from this memory (bytes/s) system.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl0.cacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -44,20 +44,20 @@ system.cpu.numCycles 121759 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9746 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9651 # Number of integer alu accesses +system.cpu.committedOps 9747 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 9653 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9651 # number of integer instructions +system.cpu.num_int_insts 9653 # number of integer instructions system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 24812 # number of times the integer registers were read -system.cpu.num_int_register_writes 11060 # number of times the integer registers were written +system.cpu.num_int_register_reads 24817 # number of times the integer registers were read +system.cpu.num_int_register_writes 11061 # number of times the integer registers were written system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1986 # number of memory refs +system.cpu.num_mem_refs 1987 # number of memory refs system.cpu.num_load_insts 1052 # Number of load instructions -system.cpu.num_store_insts 934 # Number of store instructions +system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles system.cpu.num_busy_cycles 121759 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles |