diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt | 322 |
1 files changed, 164 insertions, 158 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 9047321d1..afc430970 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30886500 # Number of ticks simulated -final_tick 30886500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 31247500 # Number of ticks simulated +final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211795 # Simulator instruction rate (inst/s) -host_op_rate 383429 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1214135841 # Simulator tick rate (ticks/s) -host_mem_usage 263924 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 85405 # Simulator instruction rate (inst/s) +host_op_rate 154687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 495766938 # Simulator tick rate (ticks/s) +host_mem_usage 269328 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory system.physmem.bytes_read::total 23104 # Number of bytes read from this memory @@ -22,23 +22,23 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 470367313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277661762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 748029074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 470367313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 470367313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 470367313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277661762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 748029074 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30886500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61773 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 62495 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -59,7 +59,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61772.998000 # Number of busy cycles +system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -98,23 +98,23 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.558239 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.558239 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019668 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019668 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits @@ -131,14 +131,14 @@ system.cpu.dcache.demand_misses::cpu.data 134 # n system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3410000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3410000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4898000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8308000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8308000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8308000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8308000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -155,14 +155,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,14 +177,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 134 system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3355000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4819000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4819000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8174000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8174000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses @@ -193,31 +193,31 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.267613 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.267613 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051400 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051400 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits @@ -230,12 +230,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14088500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14088500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14088500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14088500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14088500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14088500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -248,12 +248,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61791.666667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61791.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61791.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61791.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61791.666667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,43 +266,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13860500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13860500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13860500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13860500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60791.666667 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60791.666667 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60791.666667 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 60791.666667 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 133.672095 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.256135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.415959 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003212 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000867 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004079 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008606 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -321,18 +321,18 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4700500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13507000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13507000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3272500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13507000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7973000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21480000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13507000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7973000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21480000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) @@ -357,18 +357,18 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 59501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 59501.385042 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -387,18 +387,18 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3910500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3910500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11237000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11237000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2722500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17870000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11237000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17870000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses @@ -411,25 +411,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.385042 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution @@ -459,8 +459,14 @@ system.cpu.toL2Bus.reqLayer0.utilization 0.6 # La system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.pwrStateResidencyTicks::UNDEFINED 30886500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) +system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution system.membus.trans_dist::ReadExResp 79 # Transaction distribution |