diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86/linux')
7 files changed, 33 insertions, 22 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index f285016ae..95eaee017 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57117 # Simulator instruction rate (inst/s) -host_op_rate 103440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59566456 # Simulator tick rate (ticks/s) -host_mem_usage 237684 # Number of bytes of host memory used +host_inst_rate 57597 # Simulator instruction rate (inst/s) +host_op_rate 104318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60076981 # Simulator tick rate (ticks/s) +host_mem_usage 286548 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -65,5 +65,6 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 11231 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index d7786b69e..b20ae7d88 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges=0:268435455 memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload +branchPred=Null checker=Null clk_domain=system.cpu.clk_domain cpu_id=0 @@ -141,7 +143,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 53e9ad058..2e7d64a51 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 17:30:11 -gem5 executing on u200540-lin +gem5 compiled Feb 15 2014 16:30:59 +gem5 started Feb 15 2014 16:34:58 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 9b8cf8013..8fc84aed4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000122 # Nu sim_ticks 121759 # Number of ticks simulated final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 33614 # Simulator instruction rate (inst/s) -host_op_rate 60888 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 760469 # Simulator tick rate (ticks/s) -host_mem_usage 144688 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 29778 # Simulator instruction rate (inst/s) +host_op_rate 53940 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 673676 # Simulator tick rate (ticks/s) +host_mem_usage 193492 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -130,6 +130,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 121759 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched system.ruby.network.routers0.throttle0.link_utilization 5.652970 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index b6193f8c7..25de1cc29 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -18,6 +18,7 @@ eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 +load_offset=0 mem_mode=timing mem_ranges= memories=system.physmem @@ -42,6 +43,7 @@ voltage_domain=system.voltage_domain [system.cpu] type=TimingSimpleCPU children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -251,7 +253,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/test-progs/hello/bin/x86/linux/hello +executable=tests/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index bb364e541..ac02fa74d 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simout +Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 22 2014 17:10:34 -gem5 started Jan 22 2014 17:30:10 -gem5 executing on u200540-lin +gem5 compiled Feb 15 2014 16:30:59 +gem5 started Feb 15 2014 16:31:13 +gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 017ee7525..35c0c845e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44998 # Simulator instruction rate (inst/s) -host_op_rate 81497 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 237030591 # Simulator tick rate (ticks/s) -host_mem_usage 247544 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 50744 # Simulator instruction rate (inst/s) +host_op_rate 91910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 267330545 # Simulator tick rate (ticks/s) +host_mem_usage 295388 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -73,6 +73,7 @@ system.cpu.num_idle_cycles 0 # Nu system.cpu.num_busy_cycles 56716 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1208 # Number of branches fetched system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. |