diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86')
4 files changed, 52 insertions, 52 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index a38f35e7a..83799ecfd 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -288,7 +288,7 @@ system.cpu.fetch.Insts 15528 # Nu system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1202 # Number of cycles fetch has spent squashing +system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions @@ -491,11 +491,11 @@ system.cpu.iew.wb_penalized_rate 0 # fr system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19925 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489184 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394250 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16685 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle @@ -507,7 +507,7 @@ system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19925 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,8 +555,8 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # system.cpu.commit.op_class_0::total 9747 # Class of committed instruction system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 41132 # The number of ROB reads -system.cpu.rob.rob_writes 44928 # The number of ROB writes +system.cpu.rob.rob_reads 41131 # The number of ROB reads +system.cpu.rob.rob_writes 44929 # The number of ROB writes system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated @@ -565,7 +565,7 @@ system.cpu.cpi 7.315428 # CP system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21340 # number of integer regfile reads +system.cpu.int_regfile_reads 21341 # number of integer regfile reads system.cpu.int_regfile_writes 13120 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.cc_regfile_reads 8069 # number of cc regfile reads diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index baff57318..3bcc97a18 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -85,10 +85,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 11231 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index be3906efe..cdd2719ec 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -21,11 +21,11 @@ system.ruby.delayHist | 2750 100.00% 100.00% | system.ruby.delayHist::total 2750 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 8853 +system.ruby.outstanding_req_hist::samples 8852 system.ruby.outstanding_req_hist::mean 1 system.ruby.outstanding_req_hist::gmean 1 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 8853 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 8852 system.ruby.latency_hist::bucket_size 16 system.ruby.latency_hist::max_bucket 159 system.ruby.latency_hist::samples 8852 @@ -126,10 +126,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 121759 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.999992 # Number of idle cycles +system.cpu.num_busy_cycles 121758.000008 # Number of busy cycles +system.cpu.not_idle_fraction 0.999992 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000008 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 8118efe8c..b43d6cab2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -77,10 +77,10 @@ system.cpu.num_cc_register_writes 3536 # nu system.cpu.num_mem_refs 1988 # number of memory refs system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 56716 # Number of busy cycles -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction @@ -119,9 +119,9 @@ system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Cl system.cpu.op_class::total 9748 # Class of executed instruction system.cpu.icache.tags.replacements 0 # number of replacements system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6637 # Total number of references to valid blocks. +system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.109649 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy @@ -130,14 +130,14 @@ system.cpu.icache.tags.occ_task_id_blocks::1024 228 system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13958 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13958 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 6637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6637 # number of overall hits -system.cpu.icache.overall_hits::total 6637 # number of overall hits +system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13956 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits +system.cpu.icache.overall_hits::total 6636 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses @@ -150,18 +150,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12498000 system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6865 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6865 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6865 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6865 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033212 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.033212 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.033212 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.033212 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.033212 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.033212 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency @@ -188,12 +188,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033212 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.033212 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033212 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.033212 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency |