diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref/x86')
9 files changed, 209 insertions, 83 deletions
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ebb140a84..19d634444 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:03:58 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 5a009d0f1..b16a10afa 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000012 # Nu sim_ticks 12198000 # Number of ticks simulated final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27776 # Simulator instruction rate (inst/s) -host_op_rate 50299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62542635 # Simulator tick rate (ticks/s) -host_mem_usage 245428 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 39950 # Simulator instruction rate (inst/s) +host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89952499 # Simulator tick rate (ticks/s) +host_mem_usage 224288 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 451 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2366289556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2366289556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory +system.physmem.bytes_read::total 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 24397 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -321,11 +328,17 @@ system.cpu.icache.demand_accesses::total 1951 # nu system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,11 +366,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 10687000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.155818 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35154.605263 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35154.605263 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35154.605263 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35154.605263 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use @@ -401,13 +420,21 @@ system.cpu.dcache.demand_accesses::total 2556 # nu system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -439,13 +466,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 5263500 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5263500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 5263500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.058294 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.058294 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35260.273973 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35260.273973 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35388.157895 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35388.157895 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35325.503356 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35325.503356 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 179.622577 # Cycle average of tags in use @@ -499,18 +534,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 149 system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.994695 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.995585 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.995585 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.125828 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34278.666667 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34250 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34273.835920 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.125828 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34273.835920 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,18 +586,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index 0daaf6112..85d4b3244 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:09 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 2c5d9e840..971607574 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000006 # Nu sim_ticks 5651000 # Number of ticks simulated final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 8235 # Simulator instruction rate (inst/s) -host_op_rate 14913 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8590426 # Simulator tick rate (ticks/s) -host_mem_usage 234908 # Number of bytes of host memory used -host_seconds 0.66 # Real time elapsed on the host +host_inst_rate 420667 # Simulator instruction rate (inst/s) +host_op_rate 760787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 437668419 # Simulator tick rate (ticks/s) +host_mem_usage 214072 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7110 # Number of bytes written to this memory -system.physmem.num_reads 7966 # Number of read requests responded to by this memory -system.physmem.num_writes 934 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 11033091488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 9782339409 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 1258184392 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 12291275880 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory +system.physmem.bytes_read::total 62348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory +system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory +system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 9782339409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1250752079 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11033091488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 9782339409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 9782339409 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1258184392 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1258184392 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 9782339409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2508936471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12291275880 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 11303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats index a0ea73428..400138927 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jun/03/2012 13:31:00 +Real time: Jun/04/2012 15:04:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.36 +Virtual_time_in_minutes: 0.006 +Virtual_time_in_hours: 0.0001 +Virtual_time_in_days: 4.16667e-06 Ruby_current_time: 276484 Ruby_start_time: 0 Ruby_cycles: 276484 -mbytes_resident: 52.5547 -mbytes_total: 249.254 -resident_ratio: 0.210848 +mbytes_resident: 52.9648 +mbytes_total: 228.941 +resident_ratio: 0.232473 ruby_cycles_executed: [ 276485 ] @@ -125,7 +125,7 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11223 +page_reclaims: 14034 page_faults: 0 swaps: 0 block_inputs: 0 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index bef47caec..781f2a777 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:58 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:30 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 436ded977..37cc5b98f 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,23 +4,35 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 34222 # Simulator instruction rate (inst/s) -host_op_rate 61969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1746397 # Simulator tick rate (ticks/s) -host_mem_usage 255240 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 48659 # Simulator instruction rate (inst/s) +host_op_rate 88106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2482786 # Simulator tick rate (ticks/s) +host_mem_usage 234440 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 62348 # Number of bytes read from this memory -system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory -system.physmem.bytes_written 7110 # Number of bytes written to this memory -system.physmem.num_reads 7966 # Number of read requests responded to by this memory -system.physmem.num_writes 934 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 225503103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 199939237 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 25715774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 251218877 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 55280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7068 # Number of bytes read from this memory +system.physmem.bytes_read::total 62348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 55280 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 7110 # Number of bytes written to this memory +system.physmem.bytes_written::total 7110 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6910 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1056 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7966 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 934 # Number of write requests responded to by this memory +system.physmem.num_writes::total 934 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 199939237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 25563866 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 225503103 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 199939237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 25715774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 25715774 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 199939237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 51279640 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 251218877 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 276484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 91d5c9297..62a044b81 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 3 2012 13:30:44 -gem5 started Jun 3 2012 13:30:59 -gem5 executing on burrito +gem5 compiled Jun 4 2012 13:44:28 +gem5 started Jun 4 2012 15:04:19 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 2325f81a1..1e89d36d4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,22 +4,29 @@ sim_seconds 0.000029 # Nu sim_ticks 28768000 # Number of ticks simulated final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39729 # Simulator instruction rate (inst/s) -host_op_rate 71940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 210944443 # Simulator tick rate (ticks/s) -host_mem_usage 244104 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 318234 # Simulator instruction rate (inst/s) +host_op_rate 575684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1686451163 # Simulator tick rate (ticks/s) +host_mem_usage 223048 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 361 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 803114572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 803114572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory +system.physmem.bytes_read::total 23104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory +system.physmem.num_reads::total 361 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 505005562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 298109010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 803114572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 505005562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 505005562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 505005562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 298109010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 803114572 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -77,11 +84,17 @@ system.cpu.icache.demand_accesses::total 6911 # nu system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032991 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032991 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032991 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55815.789474 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -103,11 +116,17 @@ system.cpu.icache.demand_mshr_miss_latency::total 12042000 system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032991 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.032991 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.032991 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use @@ -151,13 +170,21 @@ system.cpu.dcache.demand_accesses::total 1990 # nu system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052083 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084582 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067337 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067337 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -183,13 +210,21 @@ system.cpu.dcache.demand_mshr_miss_latency::total 7102000 system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052083 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084582 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067337 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067337 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use @@ -243,18 +278,26 @@ system.cpu.l2cache.overall_accesses::cpu.data 134 system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.996466 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -287,18 +330,26 @@ system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |