diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref')
15 files changed, 1124 insertions, 1142 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 6a6ed7d49..773d3c5ec 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -126,11 +128,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.checker] type=O3Checker -children=dtb itb tracer +children=dtb isa itb tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -139,6 +140,7 @@ exitOnError=false function_trace=false function_trace_start=0 interrupts=Null +isa=system.cpu.checker.isa itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -147,6 +149,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.checker.tracer updateOnError=true @@ -166,6 +169,23 @@ num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] +[system.cpu.checker.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.checker.itb] type=ArmTLB children=walker @@ -189,21 +209,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -492,21 +507,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -515,6 +525,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -535,21 +562,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -576,7 +598,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index edb619587..dbd9474aa 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 1 2012 15:18:10 -gem5 started Nov 1 2012 22:40:56 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:26:41 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13371000 because target called exit() +Exiting @ tick 13372000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 28f275f3a..d1f8143b0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13371000 # Number of ticks simulated -final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13372000 # Number of ticks simulated +final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32987 # Simulator instruction rate (inst/s) -host_op_rate 41149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95942804 # Simulator tick rate (ticks/s) -host_mem_usage 272856 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 16216 # Simulator instruction rate (inst/s) +host_op_rate 20228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47166036 # Simulator tick rate (ticks/s) +host_mem_usage 230800 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13312500 # Total gap between requests +system.physmem.totGap 13314500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 11.79 # Data bus utilization in percentage @@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33788.07 # Average gap between requests +system.physmem.avgGap 33793.15 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -273,7 +273,7 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26743 # number of cpu cycles simulated +system.cpu.numCycles 26745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 2505 # Number of BP lookups @@ -284,22 +284,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) @@ -310,11 +309,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing @@ -327,17 +326,17 @@ system.cpu.rename.IdleCycles 7146 # Nu system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 44 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer @@ -352,13 +351,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle @@ -368,7 +367,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -438,10 +437,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.rate 0.336063 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -464,7 +463,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions @@ -482,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1446 # Number of branches executed system.cpu.iew.exec_stores 1164 # Number of stores executed -system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.exec_rate 0.320209 # Inst execution rate system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8109 # cumulative count of insts written-back system.cpu.iew.wb_producers 3899 # num instructions producing a value system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit @@ -526,64 +525,64 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 22988 # The number of ROB reads system.cpu.rob.rob_writes 23599 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 39369 # number of integer regfile reads system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # 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average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits @@ -654,16 +787,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -686,16 +819,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -722,14 +855,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # 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number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 675d12028..38f0d4bce 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 116fbeb57..b1b5545bf 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 18:52:17 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:26:30 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13371000 because target called exit() +Exiting @ tick 13372000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 11fc8e27b..5c779e5dd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13371000 # Number of ticks simulated -final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13372000 # Number of ticks simulated +final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36978 # Simulator instruction rate (inst/s) -host_op_rate 46127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107546339 # Simulator tick rate (ticks/s) -host_mem_usage 272728 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 20879 # Simulator instruction rate (inst/s) +host_op_rate 26045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60729168 # Simulator tick rate (ticks/s) +host_mem_usage 230484 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13312500 # Total gap between requests +system.physmem.totGap 13314500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 11.79 # Data bus utilization in percentage @@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33788.07 # Average gap between requests +system.physmem.avgGap 33793.15 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,7 +228,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26743 # number of cpu cycles simulated +system.cpu.numCycles 26745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 2505 # Number of BP lookups @@ -239,22 +239,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) @@ -265,11 +264,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing @@ -282,17 +281,17 @@ system.cpu.rename.IdleCycles 7146 # Nu system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 44 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer @@ -307,13 +306,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle @@ -323,7 +322,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -393,10 +392,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.rate 0.336063 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -419,7 +418,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions @@ -437,13 +436,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1446 # Number of branches executed system.cpu.iew.exec_stores 1164 # Number of stores executed -system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.exec_rate 0.320209 # Inst execution rate system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8109 # cumulative count of insts written-back system.cpu.iew.wb_producers 3899 # num instructions producing a value system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit @@ -481,64 +480,64 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 22988 # The number of ROB reads system.cpu.rob.rob_writes 23599 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 39369 # number of integer regfile reads system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -547,46 +546,180 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits @@ -609,16 +742,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # 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number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -641,16 +774,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -677,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # 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number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 6eeed9c1d..3748def17 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -116,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -132,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -426,21 +422,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -465,21 +456,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -506,7 +492,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello +executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 5f05c3882..f2fe39e9e 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:08:52 -gem5 started Oct 30 2012 13:57:41 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:13:46 +gem5 started Jan 4 2013 21:58:53 +gem5 executing on u200540 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index d0a749f15..f897666a8 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16532500 # Number of ticks simulated final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48770 # Simulator instruction rate (inst/s) -host_op_rate 48763 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156337427 # Simulator tick rate (ticks/s) -host_mem_usage 215260 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 25568 # Simulator instruction rate (inst/s) +host_op_rate 25564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81956278 # Simulator tick rate (ticks/s) +host_mem_usage 217336 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16452500 # Total gap between requests +system.physmem.totGap 16453500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2527972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests +system.physmem.totQLat 2530972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests system.physmem.totBusLat 1904000 # Total cycles spent in databus access system.physmem.totBankLat 8652000 # Total cycles spent in bank access -system.physmem.avgQLat 5310.87 # Average queueing delay per request +system.physmem.avgQLat 5317.17 # Average queueing delay per request system.physmem.avgBankLat 18176.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27487.34 # Average memory access latency +system.physmem.avgMemAccLat 27493.64 # Average memory access latency system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 376 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34564.08 # Average gap between requests +system.physmem.avgGap 34566.18 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -215,17 +215,16 @@ system.cpu.BPredUnit.BTBHits 517 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) @@ -471,50 +470,50 @@ system.cpu.fp_regfile_reads 3 # nu system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 147 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use +system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits system.cpu.icache.overall_hits::total 1502 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses -system.cpu.icache.overall_misses::total 446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses +system.cpu.icache.overall_misses::total 447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -523,48 +522,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 109 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 109 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 109 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 109 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 109 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 109 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173422 # 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Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 165.672562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.124752 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006830 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -582,17 +581,17 @@ system.cpu.l2cache.demand_misses::total 476 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16588000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22038000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16588000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24740000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses) @@ -615,17 +614,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993737 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51970.588235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51974.789916 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49516.417910 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57815.602837 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51974.789916 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -645,17 +644,17 @@ system.cpu.l2cache.demand_mshr_misses::total 476 system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12365045 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4341573 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16706618 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12365045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6412627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18777672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12365045 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6412627 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18777672 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses @@ -667,27 +666,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36910.582090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48239.700000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.689412 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 92.017211 # Cycle average of tags in use system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 92.017211 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022465 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022465 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -704,14 +703,14 @@ system.cpu.dcache.demand_misses::cpu.data 504 # n system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses system.cpu.dcache.overall_misses::total 504 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8905500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8905500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24508999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24508999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24508999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24508999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -728,14 +727,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58976.821192 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58976.821192 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48628.966270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48628.966270 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -760,14 +759,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -776,14 +775,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 71523c506..ed3b8ffac 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -57,7 +58,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -117,6 +117,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -133,21 +134,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -427,21 +423,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,21 +455,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -505,7 +491,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello +executable=/gem5/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 71a23fbd5..302c5d913 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:09:52 -gem5 started Oct 30 2012 13:58:22 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:14:12 +gem5 started Jan 4 2013 21:59:04 +gem5 executing on u200540 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b47dafade..32c8057b9 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 14065500 # Number of ticks simulated final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60799 # Simulator instruction rate (inst/s) -host_op_rate 60790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147601989 # Simulator tick rate (ticks/s) -host_mem_usage 210652 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 28037 # Simulator instruction rate (inst/s) +host_op_rate 28032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68062430 # Simulator tick rate (ticks/s) +host_mem_usage 213288 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13957000 # Total gap between requests +system.physmem.totGap 13958000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1923444 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11085444 # Sum of mem lat for all requests +system.physmem.totQLat 1923944 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests system.physmem.totBusLat 1784000 # Total cycles spent in databus access system.physmem.totBankLat 7378000 # Total cycles spent in bank access -system.physmem.avgQLat 4312.65 # Average queueing delay per request +system.physmem.avgQLat 4313.78 # Average queueing delay per request system.physmem.avgBankLat 16542.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24855.26 # Average memory access latency +system.physmem.avgMemAccLat 24856.38 # Average memory access latency system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 369 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31293.72 # Average gap between requests +system.physmem.avgGap 31295.96 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -215,16 +215,15 @@ system.cpu.BPredUnit.BTBHits 602 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1812 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 306 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) @@ -469,12 +468,12 @@ system.cpu.int_regfile_writes 7068 # nu system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.326699 # Cycle average of tags in use +system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.326699 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits @@ -483,36 +482,36 @@ system.cpu.icache.demand_hits::cpu.inst 1375 # nu system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits system.cpu.icache.overall_hits::total 1375 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20187000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20187000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20187000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20187000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20187000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20187000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1812 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1812 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1812 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1812 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241170 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241170 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241170 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241170 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241170 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241170 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46194.508009 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46194.508009 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46194.508009 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46194.508009 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses +system.cpu.icache.overall_misses::total 438 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20259000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20259000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20259000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241589 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241589 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241589 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241589 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.424658 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -521,44 +520,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 52 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 87 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 87 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16769000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193709 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.193709 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.193709 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47774.928775 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47774.928775 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16770000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16770000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16770000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47777.777778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47777.777778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.645490 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.645596 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.286066 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 167.286173 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy @@ -583,17 +582,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16357500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19338000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2765500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2765500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16357500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5746000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22103500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16357500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5746000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22103500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16358500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2981000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19339500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2766000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2766000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16358500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5747000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16358500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5747000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22105500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -616,17 +615,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47413.043478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55194.444444 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48466.165414 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58840.425532 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58840.425532 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49559.417040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49559.417040 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47415.942029 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55203.703704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48469.924812 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58851.063830 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58851.063830 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49563.901345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49563.901345 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +645,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035015 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2314548 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14349563 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2186544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2186544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4501092 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16536107 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035015 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4501092 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16536107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035515 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2315048 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14350563 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2187044 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2187044 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035515 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4502092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16537607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035515 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4502092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,17 +667,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34884.101449 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42862 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35963.817043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46522.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46522.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34885.550725 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use @@ -705,14 +704,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5221500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5221500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14127997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14127997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19349497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19349497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19349497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19349497 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5222000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14128997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14128997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19350997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19350997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19350997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19350997 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -729,14 +728,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.730769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.730769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42682.770393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42682.770393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44481.602299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44481.602299 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -761,14 +760,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2814999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2814999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5860999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5860999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5860999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5860999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -777,14 +776,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55381.818182 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55381.818182 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59893.595745 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59893.595745 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 26b2b0376..2a2790447 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/gem5/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 894b4b41a..8a267af68 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 01:12:54 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:09:04 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index f54c83934..59d569d41 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 15014000 # Number of ticks simulated final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27939 # Simulator instruction rate (inst/s) -host_op_rate 50607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77954156 # Simulator tick rate (ticks/s) -host_mem_usage 273052 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 15963 # Simulator instruction rate (inst/s) +host_op_rate 28915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44538984 # Simulator tick rate (ticks/s) +host_mem_usage 232848 # Number of bytes of host memory used +host_seconds 0.34 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14992500 # Total gap between requests +system.physmem.totGap 14993500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -184,7 +184,7 @@ system.physmem.readRowHits 352 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33316.67 # Average gap between requests +system.physmem.avgGap 33318.89 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 30029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -197,18 +197,18 @@ system.cpu.BPredUnit.BTBHits 796 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) @@ -451,12 +451,12 @@ system.cpu.int_regfile_writes 17233 # nu system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.misc_regfile_reads 7157 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use +system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits @@ -465,36 +465,36 @@ system.cpu.icache.demand_hits::cpu.inst 1482 # nu system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits system.cpu.icache.overall_hits::total 1482 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses -system.cpu.icache.overall_misses::total 398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses +system.cpu.icache.overall_misses::total 399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -503,12 +503,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 44 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses @@ -521,12 +521,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency @@ -534,118 +534,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use -system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits -system.cpu.dcache.overall_hits::total 2284 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses -system.cpu.dcache.overall_misses::total 202 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.021458 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.985394 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy @@ -667,16 +563,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 303 # system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 450 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18958000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7804000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22950500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses) @@ -700,16 +596,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50689.839572 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -729,17 +625,17 @@ system.cpu.l2cache.demand_mshr_misses::total 450 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336952 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14281024 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336952 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17309634 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336452 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17310134 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336952 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17309634 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17310134 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses @@ -751,17 +647,121 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.683168 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use +system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits +system.cpu.dcache.overall_hits::total 2284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses +system.cpu.dcache.overall_misses::total 202 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10557000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |