diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref')
60 files changed, 9284 insertions, 9114 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini index fc8ce75af..b967ed849 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/config.ini @@ -118,6 +118,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system threadPolicy=RoundRobin tracer=system.cpu.tracer @@ -155,10 +156,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -172,6 +173,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -184,15 +186,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -404,9 +407,9 @@ timings=system.cpu.executeFuncUnits.funcUnits4.timings [system.cpu.executeFuncUnits.funcUnits4.opClasses] type=MinorOpClassSet -children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 +children=opClasses00 opClasses01 opClasses02 opClasses03 opClasses04 opClasses05 opClasses06 opClasses07 opClasses08 opClasses09 opClasses10 opClasses11 opClasses12 opClasses13 opClasses14 opClasses15 opClasses16 opClasses17 opClasses18 opClasses19 opClasses20 opClasses21 opClasses22 opClasses23 opClasses24 opClasses25 opClasses26 opClasses27 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 +opClasses=system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses01 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses02 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26 system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27 [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses00] type=MinorOpClass @@ -426,116 +429,126 @@ opClass=FloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses03] type=MinorOpClass eventq_index=0 -opClass=FloatMult +opClass=FloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses04] type=MinorOpClass eventq_index=0 -opClass=FloatDiv +opClass=FloatMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses05] type=MinorOpClass eventq_index=0 -opClass=FloatSqrt +opClass=FloatMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses06] type=MinorOpClass eventq_index=0 -opClass=SimdAdd +opClass=FloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses07] type=MinorOpClass eventq_index=0 -opClass=SimdAddAcc +opClass=FloatSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses08] type=MinorOpClass eventq_index=0 -opClass=SimdAlu +opClass=SimdAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses09] type=MinorOpClass eventq_index=0 -opClass=SimdCmp +opClass=SimdAddAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses10] type=MinorOpClass eventq_index=0 -opClass=SimdCvt +opClass=SimdAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses11] type=MinorOpClass eventq_index=0 -opClass=SimdMisc +opClass=SimdCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses12] type=MinorOpClass eventq_index=0 -opClass=SimdMult +opClass=SimdCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses13] type=MinorOpClass eventq_index=0 -opClass=SimdMultAcc +opClass=SimdMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses14] type=MinorOpClass eventq_index=0 -opClass=SimdShift +opClass=SimdMult [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses15] type=MinorOpClass eventq_index=0 -opClass=SimdShiftAcc +opClass=SimdMultAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses16] type=MinorOpClass eventq_index=0 -opClass=SimdSqrt +opClass=SimdShift [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses17] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAdd +opClass=SimdShiftAcc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses18] type=MinorOpClass eventq_index=0 -opClass=SimdFloatAlu +opClass=SimdSqrt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses19] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCmp +opClass=SimdFloatAdd [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses20] type=MinorOpClass eventq_index=0 -opClass=SimdFloatCvt +opClass=SimdFloatAlu [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses21] type=MinorOpClass eventq_index=0 -opClass=SimdFloatDiv +opClass=SimdFloatCmp [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses22] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMisc +opClass=SimdFloatCvt [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses23] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMult +opClass=SimdFloatDiv [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses24] type=MinorOpClass eventq_index=0 -opClass=SimdFloatMultAcc +opClass=SimdFloatMisc [system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses25] type=MinorOpClass eventq_index=0 +opClass=SimdFloatMult + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses26] +type=MinorOpClass +eventq_index=0 +opClass=SimdFloatMultAcc + +[system.cpu.executeFuncUnits.funcUnits4.opClasses.opClasses27] +type=MinorOpClass +eventq_index=0 opClass=SimdFloatSqrt [system.cpu.executeFuncUnits.funcUnits4.timings] @@ -569,9 +582,9 @@ timings=system.cpu.executeFuncUnits.funcUnits5.timings [system.cpu.executeFuncUnits.funcUnits5.opClasses] type=MinorOpClassSet -children=opClasses0 opClasses1 +children=opClasses0 opClasses1 opClasses2 opClasses3 eventq_index=0 -opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 +opClasses=system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses1 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2 system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3 [system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses0] type=MinorOpClass @@ -583,6 +596,16 @@ type=MinorOpClass eventq_index=0 opClass=MemWrite +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses2] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemRead + +[system.cpu.executeFuncUnits.funcUnits5.opClasses.opClasses3] +type=MinorOpClass +eventq_index=0 +opClass=FloatMemWrite + [system.cpu.executeFuncUnits.funcUnits5.timings] type=MinorFUTiming children=opClasses @@ -635,10 +658,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -652,6 +675,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -664,15 +688,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -691,8 +716,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -703,8 +726,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -767,10 +788,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -784,6 +805,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -796,15 +818,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -840,7 +863,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -849,14 +872,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout index 6a285f351..0722728b6 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:42:59 -gem5 executing on e108600-lin, pid 17319 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54225 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/minor-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/minor-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 32719500 because target called exit() +Exiting @ tick 32617500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 218cf1458..4b0e86c1b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,878 +1,878 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32617500 # Number of ticks simulated -final_tick 32617500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 159604 # Simulator instruction rate (inst/s) -host_op_rate 186772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1129633158 # Simulator tick rate (ticks/s) -host_mem_usage 268376 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 4605 # Number of instructions simulated -sim_ops 5391 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 19456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7424 # Number of bytes read from this memory -system.physmem.bytes_read::total 26880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19456 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 304 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory -system.physmem.num_reads::total 420 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 596489614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 227607879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 824097494 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 596489614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 596489614 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 596489614 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 227607879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 824097494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 420 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 420 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26880 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 91 # Per bank write bursts -system.physmem.perBankRdBursts::1 52 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 21 # Per bank write bursts -system.physmem.perBankRdBursts::5 41 # Per bank write bursts -system.physmem.perBankRdBursts::6 36 # Per bank write bursts -system.physmem.perBankRdBursts::7 12 # Per bank write bursts -system.physmem.perBankRdBursts::8 5 # Per bank write bursts -system.physmem.perBankRdBursts::9 6 # Per bank write bursts -system.physmem.perBankRdBursts::10 27 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts -system.physmem.perBankRdBursts::13 8 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 32519500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 420 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 373.942857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.068407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 318.910277 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 18.57% 18.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 27.14% 45.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 15.71% 61.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 11.43% 72.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.29% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.86% 80.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5 7.14% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.86% 90.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7 10.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation -system.physmem.totQLat 5148000 # Total ticks spent queuing -system.physmem.totMemAccLat 13023000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12257.14 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31007.14 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 824.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 824.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.44 # Data bus utilization in percentage -system.physmem.busUtilRead 6.44 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 346 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.38 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 77427.38 # Average gap between requests -system.physmem.pageHitRate 82.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2256240 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4399260 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 59520 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 10401930 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 20101380 # Total energy per rank (pJ) -system.physmem_0.averagePower 616.275926 # Core power per rank (mW) -system.physmem_0.totalIdleTime 22764750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 30000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8725000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 22818750 # Time in different power states -system.physmem_1.actEnergy 178500 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 91080 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2458560.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1740780 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96960 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 12060060 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 806400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 18174900 # Total energy per rank (pJ) -system.physmem_1.averagePower 557.213152 # Core power per rank (mW) -system.physmem_1.totalIdleTime 28278000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 141000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 2099750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2887500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26449250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 1965 # Number of BP lookups -system.cpu.branchPred.condPredicted 1175 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 349 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1668 # Number of BTB lookups -system.cpu.branchPred.BTBHits 324 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 19.424460 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 220 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 137 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 8 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 129 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 63 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 32617500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 65235 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4605 # Number of instructions committed -system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1187 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.166124 # CPI: cycles per instruction -system.cpu.ipc 0.070591 # IPC: instructions per cycle -system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.op_class_0::IntAlu 3419 63.42% 63.42% # Class of committed instruction -system.cpu.op_class_0::IntMult 4 0.07% 63.49% # Class of committed instruction -system.cpu.op_class_0::IntDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMult 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMultAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatMisc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::FloatSqrt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAddAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdAlu 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMisc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMult 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdMultAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdShift 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdShiftAcc 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdSqrt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAdd 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatAlu 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCmp 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatCvt 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatDiv 0 0.00% 63.49% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMisc 3 0.06% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMult 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 63.55% # Class of committed instruction -system.cpu.op_class_0::MemRead 1027 19.05% 82.60% # Class of committed instruction -system.cpu.op_class_0::MemWrite 922 17.10% 99.70% # Class of committed instruction -system.cpu.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.op_class_0::total 5391 # Class of committed instruction -system.cpu.tickCycles 10712 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54523 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.828759 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.828759 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021198 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021198 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4334 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4334 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 109 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 109 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 67 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 176 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 176 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 176 # number of overall misses -system.cpu.dcache.overall_misses::total 176 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7434500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7434500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5464500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5464500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12899000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12899000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12899000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12899000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1159 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1159 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2072 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2072 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2072 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2072 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.094047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.084942 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.084942 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.084942 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.084942 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68206.422018 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68206.422018 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81559.701493 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81559.701493 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 73289.772727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 73289.772727 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 73289.772727 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 24 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7061000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3488000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3488000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10549000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10549000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10549000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10549000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088870 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070463 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070463 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68553.398058 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68553.398058 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81116.279070 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81116.279070 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72253.424658 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72253.424658 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4 # number of replacements -system.cpu.icache.tags.tagsinuse 162.068358 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1966 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.124611 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.068358 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079135 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079135 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 317 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 219 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.154785 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4895 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4895 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1966 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1966 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1966 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1966 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1966 # number of overall hits -system.cpu.icache.overall_hits::total 1966 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses -system.cpu.icache.overall_misses::total 321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25981000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25981000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25981000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25981000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25981000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25981000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2287 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2287 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2287 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2287 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2287 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.140359 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.140359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.140359 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.140359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.140359 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.140359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.694704 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80937.694704 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80937.694704 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.694704 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80937.694704 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4 # number of writebacks -system.cpu.icache.writebacks::total 4 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 321 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 321 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 321 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25660000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25660000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25660000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25660000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.140359 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.140359 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.140359 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.140359 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79937.694704 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79937.694704 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79937.694704 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79937.694704 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 223.784324 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 420 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.100000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.947993 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 68.836332 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006829 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012817 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4180 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4180 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 3 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 3 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 22 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 22 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits -system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 304 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 304 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 81 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 81 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 304 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 124 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 304 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses -system.cpu.l2cache.overall_misses::total 428 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3423500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24983000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 24983000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6647000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24983000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10070500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35053500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24983000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10070500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35053500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 321 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 321 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 321 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 467 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 321 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 467 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947040 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947040 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.786408 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947040 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.849315 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947040 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79616.279070 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82180.921053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82180.921053 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82061.728395 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 81900.700935 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82180.921053 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81213.709677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 81900.700935 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 304 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 304 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 73 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 116 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2993500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 21943000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 21943000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5321000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21943000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8314500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21943000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8314500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947040 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.708738 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947040 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69616.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72180.921053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72180.921053 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72890.410959 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72180.921053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71676.724138 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72041.666667 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 471 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 50 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100642 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 239500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 481500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222992 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 420 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 377 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 420 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 420 # Request fanout histogram -system.membus.reqLayer0.occupancy 489000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2233000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +sim_seconds 0.000033 +sim_ticks 32617500 +final_tick 32617500 +sim_freq 1000000000000 +host_inst_rate 73373 +host_op_rate 85866 +host_tick_rate 519360115 +host_mem_usage 279788 +host_seconds 0.06 +sim_insts 4605 +sim_ops 5391 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 32617500 +system.physmem.bytes_read::cpu.inst 19456 +system.physmem.bytes_read::cpu.data 7424 +system.physmem.bytes_read::total 26880 +system.physmem.bytes_inst_read::cpu.inst 19456 +system.physmem.bytes_inst_read::total 19456 +system.physmem.num_reads::cpu.inst 304 +system.physmem.num_reads::cpu.data 116 +system.physmem.num_reads::total 420 +system.physmem.bw_read::cpu.inst 596489614 +system.physmem.bw_read::cpu.data 227607879 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+system.cpu.toL2Bus.trans_dist::ReadExReq 43 +system.cpu.toL2Bus.trans_dist::ReadExResp 43 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 321 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 +system.cpu.toL2Bus.pkt_count::total 938 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20800 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 +system.cpu.toL2Bus.pkt_size::total 30144 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 467 +system.cpu.toL2Bus.snoop_fanout::mean 0.100642 +system.cpu.toL2Bus.snoop_fanout::stdev 0.301177 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 420 89.94% 89.94% +system.cpu.toL2Bus.snoop_fanout::1 47 10.06% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 467 +system.cpu.toL2Bus.reqLayer0.occupancy 239500 +system.cpu.toL2Bus.reqLayer0.utilization 0.7 +system.cpu.toL2Bus.respLayer0.occupancy 481500 +system.cpu.toL2Bus.respLayer0.utilization 1.5 +system.cpu.toL2Bus.respLayer1.occupancy 222992 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 420 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 32617500 +system.membus.trans_dist::ReadResp 377 +system.membus.trans_dist::ReadExReq 43 +system.membus.trans_dist::ReadExResp 43 +system.membus.trans_dist::ReadSharedReq 377 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 +system.membus.pkt_count::total 840 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 +system.membus.pkt_size::total 26880 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 420 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 420 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 420 +system.membus.reqLayer0.occupancy 489000 +system.membus.reqLayer0.utilization 1.5 +system.membus.respLayer1.occupancy 2233000 +system.membus.respLayer1.utilization 6.8 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index ff436d924..64046a027 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=system.cpu.checker clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -206,6 +207,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=true @@ -276,8 +278,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -288,8 +288,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -356,10 +354,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -373,6 +371,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -385,15 +384,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -517,10 +517,10 @@ pipelined=true [system.cpu.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 +children=opList0 opList1 opList2 opList3 opList4 count=2 eventq_index=0 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 [system.cpu.fuPool.FUList3.opList0] type=OpDesc @@ -532,11 +532,25 @@ pipelined=true [system.cpu.fuPool.FUList3.opList1] type=OpDesc eventq_index=0 +opClass=FloatMultAcc +opLat=5 +pipelined=true + +[system.cpu.fuPool.FUList3.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMisc +opLat=3 +pipelined=true + +[system.cpu.fuPool.FUList3.opList3] +type=OpDesc +eventq_index=0 opClass=FloatDiv opLat=12 pipelined=false -[system.cpu.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList4] type=OpDesc eventq_index=0 opClass=FloatSqrt @@ -545,18 +559,25 @@ pipelined=false [system.cpu.fuPool.FUList4] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList4.opList +opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 -[system.cpu.fuPool.FUList4.opList] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc eventq_index=0 opClass=MemRead opLat=1 pipelined=true +[system.cpu.fuPool.FUList4.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList5] type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 @@ -706,24 +727,31 @@ pipelined=true [system.cpu.fuPool.FUList6] type=FUDesc -children=opList +children=opList0 opList1 count=0 eventq_index=0 -opList=system.cpu.fuPool.FUList6.opList +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu.fuPool.FUList6.opList] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc eventq_index=0 opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList6.opList1] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList7] type=FUDesc -children=opList0 opList1 +children=opList0 opList1 opList2 opList3 count=4 eventq_index=0 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 +opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 [system.cpu.fuPool.FUList7.opList0] type=OpDesc @@ -739,6 +767,20 @@ opClass=MemWrite opLat=1 pipelined=true +[system.cpu.fuPool.FUList7.opList2] +type=OpDesc +eventq_index=0 +opClass=FloatMemRead +opLat=1 +pipelined=true + +[system.cpu.fuPool.FUList7.opList3] +type=OpDesc +eventq_index=0 +opClass=FloatMemWrite +opLat=1 +pipelined=true + [system.cpu.fuPool.FUList8] type=FUDesc children=opList @@ -760,10 +802,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -777,6 +819,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -789,15 +832,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -816,8 +860,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -828,8 +870,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -892,10 +932,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -909,6 +949,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -921,15 +962,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -965,7 +1007,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -974,14 +1016,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr index 57447a9b7..1f8287d96 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simerr @@ -2,3 +2,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index e9b447feb..122f716a7 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 20:42:58 -gem5 executing on e108600-lin, pid 17311 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:05:15 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55322 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 18422500 because target called exit() +Exiting @ tick 18517500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index b3c6058a4..306010dfa 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,1273 +1,1273 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18517500 # Number of ticks simulated -final_tick 18517500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74881 # Simulator instruction rate (inst/s) -host_op_rate 87684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 301872470 # Simulator tick rate (ticks/s) -host_mem_usage 270416 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25344 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 396 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 950452275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 418199001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1368651276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 950452275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 950452275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 418199001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1368651276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 396 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 89 # Per bank write bursts -system.physmem.perBankRdBursts::1 45 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 35 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 10 # Per bank write bursts -system.physmem.perBankRdBursts::13 6 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18432000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 396 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.779661 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 269.610222 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 346.645206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation -system.physmem.totQLat 5212000 # Total ticks spent queuing -system.physmem.totMemAccLat 12637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13161.62 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31911.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1368.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1368.65 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.69 # Data bus utilization in percentage -system.physmem.busUtilRead 10.69 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.87 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 329 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.08 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 46545.45 # Average gap between requests -system.physmem.pageHitRate 83.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 314160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 151800 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2084880 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3085980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 37920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5290170 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 19200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 12213390 # Total energy per rank (pJ) -system.physmem_0.averagePower 659.559336 # Core power per rank (mW) -system.physmem_0.totalIdleTime 11496500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 49250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6316250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 11602500 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 72105 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 742560 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1457490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 66240 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6092730 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 686400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10511025 # Total energy per rank (pJ) -system.physmem_1.averagePower 567.626569 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15098500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 116000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1787250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2733750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13360500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2820 # Number of BP lookups -system.cpu.branchPred.condPredicted 1728 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2384 # Number of BTB lookups -system.cpu.branchPred.BTBHits 844 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.402685 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 322 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 260 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 247 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 64 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 5391 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 18517500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 37036 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7733 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12373 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2820 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5113 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 985 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 260 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1982 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 291 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.093052 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461769 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10916 80.17% 80.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 271 1.99% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 182 1.34% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 206 1.51% 85.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 259 1.90% 86.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 398 2.92% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 138 1.01% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.41% 92.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1054 7.74% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13616 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076142 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.334080 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6341 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4657 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2138 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 909 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12250 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6573 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 835 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2470 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2036 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1364 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11552 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 181 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 144 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1170 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11673 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 53030 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12530 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 199 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6179 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 40 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 442 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2293 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1619 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10296 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8207 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 43 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4962 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12830 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13616 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.602747 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.340306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10392 76.32% 76.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1145 8.41% 84.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 5.60% 90.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 485 3.56% 93.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.61% 96.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 278 2.04% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 127 0.93% 99.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 61 0.45% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13616 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.42% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 83 50.00% 55.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 61 36.75% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 92.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 13 7.83% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5024 61.22% 61.22% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.09% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1962 23.91% 85.24% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1178 14.35% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 33 0.40% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8207 # Type of FU issued -system.cpu.iq.rate 0.221595 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020227 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30145 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15189 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7438 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 94 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 46 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1266 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 681 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 707 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10349 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2293 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1619 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 93 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 267 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7885 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1840 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9 # number of nop insts executed -system.cpu.iew.exec_refs 3007 # number of memory reference insts executed -system.cpu.iew.exec_branches 1490 # Number of branches executed -system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.212901 # Inst execution rate -system.cpu.iew.wb_sent 7581 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7470 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3518 # num instructions producing a value -system.cpu.iew.wb_consumers 6872 # num instructions consuming a value -system.cpu.iew.wb_rate 0.201696 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.511932 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4970 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12743 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.422036 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.264076 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10698 83.95% 83.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 879 6.90% 90.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 416 3.26% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 216 1.70% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.87% 96.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 220 1.73% 98.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.43% 98.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.31% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 109 0.86% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12743 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 109 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22825 # The number of ROB reads -system.cpu.rob.rob_writes 21580 # The number of ROB writes -system.cpu.timesIdled 193 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 23420 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.065331 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.065331 # CPI: Total CPI of All Threads -system.cpu.ipc 0.123987 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.123987 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7779 # number of integer regfile reads -system.cpu.int_regfile_writes 4297 # number of integer regfile writes -system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28140 # number of cc regfile reads -system.cpu.cc_regfile_writes 3276 # number of cc regfile writes -system.cpu.misc_regfile_reads 3029 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.889702 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2158 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.680272 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.889702 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021457 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5471 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5471 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 597 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 597 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits -system.cpu.dcache.overall_hits::total 2137 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 186 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 186 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11381500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11381500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24478000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24478000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 156000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35859500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35859500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35859500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1726 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2639 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2639 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.107764 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.346112 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190224 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190224 # miss rate for demand accesses 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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 71433.266932 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71433.266932 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 274 # number of WriteReq MSHR hits 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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69885.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74870.748299 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74870.748299 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 148.671994 # Cycle average of tags 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(read+write) misses -system.cpu.icache.overall_misses::cpu.inst 395 # number of overall misses -system.cpu.icache.overall_misses::total 395 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29663500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29663500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29663500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29663500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29663500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1982 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1982 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1982 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1982 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1982 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199294 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199294 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199294 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199294 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199294 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75097.468354 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 75097.468354 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 75097.468354 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 75097.468354 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 422 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 105.500000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2 # number of writebacks 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misses -system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23439000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23439000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23439000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23439000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.147830 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.147830 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.147830 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79996.587031 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79996.587031 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 79996.587031 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 213.492112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 396 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.098485 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.462705 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 74.029407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004256 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006515 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012085 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3924 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3924 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 18 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 18 # number of ReadCleanReq hits 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-system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 293 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 105 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.938567 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.809524 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938567 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.913636 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938567 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.913636 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 85785.714286 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82878.181818 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81688.235294 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82930.348259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82878.181818 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83043.307087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82930.348259 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 275 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 79 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20041500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5712000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20041500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8895000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28936500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20041500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8895000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28936500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.938567 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.752381 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938567 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75785.714286 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72878.181818 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72303.797468 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72878.181818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73512.396694 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73071.969697 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 442 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 293 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 105 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.100000 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.300341 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 396 90.00% 90.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 44 10.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 223000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 439500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 223494 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 396 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 18517500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 354 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 354 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 396 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 396 # Request fanout histogram -system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2091500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.3 # Layer utilization (%) +sim_seconds 0.000019 +sim_ticks 18517500 +final_tick 18517500 +sim_freq 1000000000000 +host_inst_rate 45460 +host_op_rate 53229 +host_tick_rate 183240261 +host_mem_usage 280812 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 18517500 +system.physmem.bytes_read::cpu.inst 17600 +system.physmem.bytes_read::cpu.data 7744 +system.physmem.bytes_read::total 25344 +system.physmem.bytes_inst_read::cpu.inst 17600 +system.physmem.bytes_inst_read::total 17600 +system.physmem.num_reads::cpu.inst 275 +system.physmem.num_reads::cpu.data 121 +system.physmem.num_reads::total 396 +system.physmem.bw_read::cpu.inst 950452275 +system.physmem.bw_read::cpu.data 418199001 +system.physmem.bw_read::total 1368651276 +system.physmem.bw_inst_read::cpu.inst 950452275 +system.physmem.bw_inst_read::total 950452275 +system.physmem.bw_total::cpu.inst 950452275 +system.physmem.bw_total::cpu.data 418199001 +system.physmem.bw_total::total 1368651276 +system.physmem.readReqs 396 +system.physmem.writeReqs 0 +system.physmem.readBursts 396 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 25344 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 25344 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 89 +system.physmem.perBankRdBursts::1 45 +system.physmem.perBankRdBursts::2 20 +system.physmem.perBankRdBursts::3 43 +system.physmem.perBankRdBursts::4 18 +system.physmem.perBankRdBursts::5 32 +system.physmem.perBankRdBursts::6 35 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 4 +system.physmem.perBankRdBursts::9 8 +system.physmem.perBankRdBursts::10 28 +system.physmem.perBankRdBursts::11 42 +system.physmem.perBankRdBursts::12 10 +system.physmem.perBankRdBursts::13 6 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 6 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 18432000 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 396 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 204 +system.physmem.rdQLenPdf::1 121 +system.physmem.rdQLenPdf::2 52 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 4 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 59 +system.physmem.bytesPerActivate::mean 406.779661 +system.physmem.bytesPerActivate::gmean 269.610222 +system.physmem.bytesPerActivate::stdev 346.645206 +system.physmem.bytesPerActivate::0-127 11 18.64% 18.64% +system.physmem.bytesPerActivate::128-255 16 27.12% 45.76% +system.physmem.bytesPerActivate::256-383 7 11.86% 57.63% +system.physmem.bytesPerActivate::384-511 8 13.56% 71.19% +system.physmem.bytesPerActivate::512-639 1 1.69% 72.88% +system.physmem.bytesPerActivate::640-767 3 5.08% 77.97% +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% 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0.00% +system.membus.snoop_fanout::0 396 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 396 +system.membus.reqLayer0.occupancy 484000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2091500 +system.membus.respLayer1.utilization 11.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 3cdf3afd3..72771fa1e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -65,7 +65,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -141,6 +141,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -626,8 +627,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=34 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -638,8 +637,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -807,7 +804,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -816,14 +813,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index d64ac9ed3..9ae67891c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 19:03:48 -gem5 started Nov 29 2016 19:06:55 -gem5 executing on zizzer, pid 5766 -command line: /z/powerjg/gem5-upstream/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:08:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55753 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 20302000 because target called exit() +Exiting @ tick 20302000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 6ea38295f..f88830f40 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,1179 +1,1179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 20302000 # Number of ticks simulated -final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93691 # Simulator instruction rate (inst/s) -host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 414022055 # Simulator tick rate (ticks/s) -host_mem_usage 265936 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 28416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 445 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 103 # Per bank write bursts -system.physmem.perBankRdBursts::1 48 # Per bank write bursts -system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts -system.physmem.perBankRdBursts::4 19 # Per bank write bursts -system.physmem.perBankRdBursts::5 37 # Per bank write bursts -system.physmem.perBankRdBursts::6 46 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 27 # Per bank write bursts -system.physmem.perBankRdBursts::11 47 # Per bank write bursts -system.physmem.perBankRdBursts::12 17 # Per bank write bursts -system.physmem.perBankRdBursts::13 8 # Per bank write bursts -system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20260500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 445 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation -system.physmem.totQLat 6135000 # Total ticks spent queuing -system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.96 # Data bus utilization in percentage -system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 373 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 45529.21 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) -system.physmem_0.averagePower 656.916882 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states -system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) -system.physmem_1.averagePower 566.475803 # Core power per rank (mW) -system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2438 # Number of BP lookups -system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups -system.cpu.branchPred.BTBHits 446 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 40605 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5171 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4182 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7227 # Type of FU issued -system.cpu.iq.rate 0.177983 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 13 # number of nop insts executed -system.cpu.iew.exec_refs 2443 # number of memory reference insts executed -system.cpu.iew.exec_branches 1299 # Number of branches executed -system.cpu.iew.exec_stores 1024 # Number of stores executed -system.cpu.iew.exec_rate 0.168033 # Inst execution rate -system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6639 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2983 # num instructions producing a value -system.cpu.iew.wb_consumers 5430 # num instructions consuming a value -system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4592 # Number of instructions committed -system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1965 # Number of memory references committed -system.cpu.commit.loads 1027 # Number of loads committed -system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1008 # Number of branches committed -system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4624 # Number of committed integer instructions. -system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5378 # Class of committed instruction -system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 23224 # The number of ROB reads -system.cpu.rob.rob_writes 16731 # The number of ROB writes -system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4592 # Number of Instructions Simulated -system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads -system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6850 # number of integer regfile reads -system.cpu.int_regfile_writes 3795 # number of integer regfile writes -system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24229 # number of cc regfile reads -system.cpu.cc_regfile_writes 2927 # number of cc regfile writes -system.cpu.misc_regfile_reads 2559 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits -system.cpu.dcache.overall_hits::total 1903 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses -system.cpu.dcache.overall_misses::total 361 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu.dcache.writebacks::total 1 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 44 # number of replacements -system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # 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3532 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits -system.cpu.icache.overall_hits::total 3532 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for 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cycles access was blocked -system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 44 # number of writebacks -system.cpu.icache.writebacks::total 44 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue -system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 11 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 19 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 11 # number of overall hits -system.cpu.l2cache.overall_hits::total 19 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 291 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 291 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 103 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 103 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 133 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 424 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses -system.cpu.l2cache.overall_misses::total 424 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles -system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.923611 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.957111 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 98 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 98 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 69 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 414 # Transaction distribution -system.membus.trans_dist::ReadExReq 30 # Transaction distribution -system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 445 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 445 # Request fanout histogram -system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +sim_seconds 0.000020 +sim_ticks 20302000 +final_tick 20302000 +sim_freq 1000000000000 +host_inst_rate 45535 +host_op_rate 53318 +host_tick_rate 201173118 +host_mem_usage 277864 +host_seconds 0.10 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 +system.physmem.bytes_read::cpu.inst 18560 +system.physmem.bytes_read::cpu.data 8128 +system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 +system.physmem.bytes_read::total 28416 +system.physmem.bytes_inst_read::cpu.inst 18560 +system.physmem.bytes_inst_read::total 18560 +system.physmem.num_reads::cpu.inst 290 +system.physmem.num_reads::cpu.data 127 +system.physmem.num_reads::cpu.l2cache.prefetcher 27 +system.physmem.num_reads::total 444 +system.physmem.bw_read::cpu.inst 914195646 +system.physmem.bw_read::cpu.data 400354645 +system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 +system.physmem.bw_read::total 1399665058 +system.physmem.bw_inst_read::cpu.inst 914195646 +system.physmem.bw_inst_read::total 914195646 +system.physmem.bw_total::cpu.inst 914195646 +system.physmem.bw_total::cpu.data 400354645 +system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 +system.physmem.bw_total::total 1399665058 +system.physmem.readReqs 445 +system.physmem.writeReqs 0 +system.physmem.readBursts 445 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 28480 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 28480 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 103 +system.physmem.perBankRdBursts::1 48 +system.physmem.perBankRdBursts::2 19 +system.physmem.perBankRdBursts::3 45 +system.physmem.perBankRdBursts::4 19 +system.physmem.perBankRdBursts::5 37 +system.physmem.perBankRdBursts::6 46 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 4 +system.physmem.perBankRdBursts::9 8 +system.physmem.perBankRdBursts::10 27 +system.physmem.perBankRdBursts::11 47 +system.physmem.perBankRdBursts::12 17 +system.physmem.perBankRdBursts::13 8 +system.physmem.perBankRdBursts::14 0 +system.physmem.perBankRdBursts::15 7 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 20260500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 445 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 241 +system.physmem.rdQLenPdf::1 136 +system.physmem.rdQLenPdf::2 36 +system.physmem.rdQLenPdf::3 17 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 2 +system.physmem.rdQLenPdf::6 2 +system.physmem.rdQLenPdf::7 2 +system.physmem.rdQLenPdf::8 2 +system.physmem.rdQLenPdf::9 2 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 62 +system.physmem.bytesPerActivate::mean 435.612903 +system.physmem.bytesPerActivate::gmean 295.844737 +system.physmem.bytesPerActivate::stdev 352.802892 +system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% 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+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 +system.cpu.toL2Bus.pkt_count::total 930 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 +system.cpu.toL2Bus.pkt_size::total 31168 +system.cpu.toL2Bus.snoops 69 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 512 +system.cpu.toL2Bus.snoop_fanout::mean 0.134766 +system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% +system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% +system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 2 +system.cpu.toL2Bus.snoop_fanout::total 512 +system.cpu.toL2Bus.reqLayer0.occupancy 289000 +system.cpu.toL2Bus.reqLayer0.utilization 1.4 +system.cpu.toL2Bus.respLayer0.occupancy 448999 +system.cpu.toL2Bus.respLayer0.utilization 2.2 +system.cpu.toL2Bus.respLayer1.occupancy 216995 +system.cpu.toL2Bus.respLayer1.utilization 1.1 +system.membus.snoop_filter.tot_requests 445 +system.membus.snoop_filter.hit_single_requests 35 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 +system.membus.trans_dist::ReadResp 414 +system.membus.trans_dist::ReadExReq 30 +system.membus.trans_dist::ReadExResp 30 +system.membus.trans_dist::ReadSharedReq 415 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 +system.membus.pkt_count::total 889 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 +system.membus.pkt_size::total 28416 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 445 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 445 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 445 +system.membus.reqLayer0.occupancy 554444 +system.membus.reqLayer0.utilization 2.7 +system.membus.respLayer1.occupancy 2338250 +system.membus.respLayer1.utilization 11.5 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index be532b0c0..3b9285ab6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -131,6 +132,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.checker.tracer updateOnError=false @@ -200,8 +202,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -212,8 +212,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -340,8 +338,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -352,8 +348,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -414,7 +408,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -423,14 +417,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -454,6 +449,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -465,7 +461,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -473,6 +469,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -481,6 +484,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -488,7 +492,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr index 2b0e974b5..d46032821 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simerr @@ -1,3 +1,4 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a4f08df89..6f0847911 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:49:47 -gem5 executing on e108600-lin, pid 23301 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:56:13 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54232 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index cf15c6ad1..d2c8b968b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,384 +1,384 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 707147 # Simulator instruction rate (inst/s) -host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 413753949 # Simulator tick rate (ticks/s) -host_mem_usage 259056 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.inst_hits 0 # ITB inst hits -system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 0 # DTB read hits -system.cpu.checker.dtb.read_misses 0 # DTB read misses -system.cpu.checker.dtb.write_hits 0 # DTB write hits -system.cpu.checker.dtb.write_misses 0 # DTB write misses -system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 0 # DTB read accesses -system.cpu.checker.dtb.write_accesses 0 # DTB write accesses -system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 0 # DTB hits -system.cpu.checker.dtb.misses 0 # DTB misses -system.cpu.checker.dtb.accesses 0 # DTB accesses -system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.itb.walker.walks 0 # Table walker walks requested -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 0 # ITB inst hits -system.cpu.checker.itb.inst_misses 0 # ITB inst misses -system.cpu.checker.itb.read_hits 0 # DTB read hits -system.cpu.checker.itb.read_misses 0 # DTB read misses -system.cpu.checker.itb.write_hits 0 # DTB write hits -system.cpu.checker.itb.write_misses 0 # DTB write misses -system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.checker.itb.read_accesses 0 # DTB read accesses -system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.itb.hits 0 # DTB hits -system.cpu.checker.itb.misses 0 # DTB misses -system.cpu.checker.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.checker.numCycles 0 # number of cpu cycles simulated -system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 413531 +host_op_rate 483368 +host_tick_rate 241807981 +host_mem_usage 270560 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 +system.physmem.bytes_inst_read::total 18420 +system.physmem.bytes_written::cpu.data 3648 +system.physmem.bytes_written::total 3648 +system.physmem.num_reads::cpu.inst 4605 +system.physmem.num_reads::cpu.data 1003 +system.physmem.num_reads::total 5608 +system.physmem.num_writes::cpu.data 924 +system.physmem.num_writes::total 924 +system.physmem.bw_read::cpu.inst 6834879406 +system.physmem.bw_read::cpu.data 1666419295 +system.physmem.bw_read::total 8501298701 +system.physmem.bw_inst_read::cpu.inst 6834879406 +system.physmem.bw_inst_read::total 6834879406 +system.physmem.bw_write::cpu.data 1353617811 +system.physmem.bw_write::total 1353617811 +system.physmem.bw_total::cpu.inst 6834879406 +system.physmem.bw_total::cpu.data 3020037106 +system.physmem.bw_total::total 9854916512 +system.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu_clk_domain.clock 500 +system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 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+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.pwrStateResidencyTicks::ON 2695000 +system.cpu.numCycles 5391 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4592 +system.cpu.committedOps 5378 +system.cpu.num_int_alu_accesses 4624 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 203 +system.cpu.num_conditional_control_insts 722 +system.cpu.num_int_insts 4624 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 7572 +system.cpu.num_int_register_writes 2728 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 16175 +system.cpu.num_cc_register_writes 2432 +system.cpu.num_mem_refs 1965 +system.cpu.num_load_insts 1027 +system.cpu.num_store_insts 938 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5391 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1008 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3419 63.42% 63.42% +system.cpu.op_class::IntMult 4 0.07% 63.49% +system.cpu.op_class::IntDiv 0 0.00% 63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 8f8064fa0..c1120b4bf 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -90,6 +90,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -165,8 +166,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -177,8 +176,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -239,7 +236,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -248,14 +245,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -279,6 +277,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -290,7 +289,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -298,6 +297,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -306,6 +312,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -313,7 +320,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 813c1fdca..ffacc8975 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23087 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 17:58:26 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54584 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2695000 because target called exit() +Exiting @ tick 2695000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 18ea66efd..9a08bb729 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,260 +1,260 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2695000 # Number of ticks simulated -final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 709054 # Simulator instruction rate (inst/s) -host_op_rate 829008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 414799236 # Simulator tick rate (ticks/s) -host_mem_usage 257780 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4592 # Number of instructions simulated -sim_ops 5378 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22911 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory -system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory -system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5391 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4592 # Number of instructions committed -system.cpu.committedOps 5378 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7572 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 5597 # Transaction distribution -system.membus.trans_dist::ReadResp 5608 # Transaction distribution -system.membus.trans_dist::WriteReq 913 # Transaction distribution -system.membus.trans_dist::WriteResp 913 # Transaction distribution -system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondReq 11 # Transaction distribution -system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6532 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6532 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2695000 +final_tick 2695000 +sim_freq 1000000000000 +host_inst_rate 427927 +host_op_rate 500175 +host_tick_rate 250203319 +host_mem_usage 269284 +host_seconds 0.01 +sim_insts 4592 +sim_ops 5378 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 +system.physmem.bytes_read::cpu.inst 18420 +system.physmem.bytes_read::cpu.data 4491 +system.physmem.bytes_read::total 22911 +system.physmem.bytes_inst_read::cpu.inst 18420 +system.physmem.bytes_inst_read::total 18420 +system.physmem.bytes_written::cpu.data 3648 +system.physmem.bytes_written::total 3648 +system.physmem.num_reads::cpu.inst 4605 +system.physmem.num_reads::cpu.data 1003 +system.physmem.num_reads::total 5608 +system.physmem.num_writes::cpu.data 924 +system.physmem.num_writes::total 924 +system.physmem.bw_read::cpu.inst 6834879406 +system.physmem.bw_read::cpu.data 1666419295 +system.physmem.bw_read::total 8501298701 +system.physmem.bw_inst_read::cpu.inst 6834879406 +system.physmem.bw_inst_read::total 6834879406 +system.physmem.bw_write::cpu.data 1353617811 +system.physmem.bw_write::total 1353617811 +system.physmem.bw_total::cpu.inst 6834879406 +system.physmem.bw_total::cpu.data 3020037106 +system.physmem.bw_total::total 9854916512 +system.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu_clk_domain.clock 500 +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.dstage2_mmu.stage2_tlb.hits 0 +system.cpu.dstage2_mmu.stage2_tlb.misses 0 +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.dtb.walker.walks 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.dtb.walker.walkRequestOrigin::total 0 +system.cpu.dtb.inst_hits 0 +system.cpu.dtb.inst_misses 0 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.flush_tlb 0 +system.cpu.dtb.flush_tlb_mva 0 +system.cpu.dtb.flush_tlb_mva_asid 0 +system.cpu.dtb.flush_tlb_asid 0 +system.cpu.dtb.flush_entries 0 +system.cpu.dtb.align_faults 0 +system.cpu.dtb.prefetch_faults 0 +system.cpu.dtb.domain_faults 0 +system.cpu.dtb.perms_faults 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.inst_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 +system.cpu.istage2_mmu.stage2_tlb.hits 0 +system.cpu.istage2_mmu.stage2_tlb.misses 0 +system.cpu.istage2_mmu.stage2_tlb.accesses 0 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 +system.cpu.itb.walker.walks 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 +system.cpu.itb.walker.walkRequestOrigin::total 0 +system.cpu.itb.inst_hits 0 +system.cpu.itb.inst_misses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.flush_tlb 0 +system.cpu.itb.flush_tlb_mva 0 +system.cpu.itb.flush_tlb_mva_asid 0 +system.cpu.itb.flush_tlb_asid 0 +system.cpu.itb.flush_entries 0 +system.cpu.itb.align_faults 0 +system.cpu.itb.prefetch_faults 0 +system.cpu.itb.domain_faults 0 +system.cpu.itb.perms_faults 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.inst_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 13 +system.cpu.pwrStateResidencyTicks::ON 2695000 +system.cpu.numCycles 5391 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 4592 +system.cpu.committedOps 5378 +system.cpu.num_int_alu_accesses 4624 +system.cpu.num_fp_alu_accesses 16 +system.cpu.num_func_calls 203 +system.cpu.num_conditional_control_insts 722 +system.cpu.num_int_insts 4624 +system.cpu.num_fp_insts 16 +system.cpu.num_int_register_reads 7572 +system.cpu.num_int_register_writes 2728 +system.cpu.num_fp_register_reads 16 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 16175 +system.cpu.num_cc_register_writes 2432 +system.cpu.num_mem_refs 1965 +system.cpu.num_load_insts 1027 +system.cpu.num_store_insts 938 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5391 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1008 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3419 63.42% 63.42% +system.cpu.op_class::IntMult 4 0.07% 63.49% +system.cpu.op_class::IntDiv 0 0.00% 63.49% +system.cpu.op_class::FloatAdd 0 0.00% 63.49% +system.cpu.op_class::FloatCmp 0 0.00% 63.49% +system.cpu.op_class::FloatCvt 0 0.00% 63.49% +system.cpu.op_class::FloatMult 0 0.00% 63.49% +system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% +system.cpu.op_class::FloatDiv 0 0.00% 63.49% +system.cpu.op_class::FloatMisc 0 0.00% 63.49% +system.cpu.op_class::FloatSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdAdd 0 0.00% 63.49% +system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% +system.cpu.op_class::SimdAlu 0 0.00% 63.49% +system.cpu.op_class::SimdCmp 0 0.00% 63.49% +system.cpu.op_class::SimdCvt 0 0.00% 63.49% +system.cpu.op_class::SimdMisc 0 0.00% 63.49% +system.cpu.op_class::SimdMult 0 0.00% 63.49% +system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% +system.cpu.op_class::SimdShift 0 0.00% 63.49% +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% +system.cpu.op_class::SimdSqrt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% +system.cpu.op_class::MemRead 1027 19.05% 82.60% +system.cpu.op_class::MemWrite 922 17.10% 99.70% +system.cpu.op_class::FloatMemRead 0 0.00% 99.70% +system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5391 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 +system.membus.trans_dist::ReadReq 5597 +system.membus.trans_dist::ReadResp 5608 +system.membus.trans_dist::WriteReq 913 +system.membus.trans_dist::WriteResp 913 +system.membus.trans_dist::LoadLockedReq 11 +system.membus.trans_dist::StoreCondReq 11 +system.membus.trans_dist::StoreCondResp 11 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 +system.membus.pkt_count::total 13064 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 +system.membus.pkt_size::total 26559 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6532 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6532 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6532 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index b1081da03..4f88d60dc 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -87,6 +87,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -117,6 +118,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -129,15 +131,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dstage2_mmu] type=ArmStage2MMU @@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -214,6 +217,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -226,15 +230,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=ArmInterrupts @@ -253,8 +258,6 @@ id_aa64isar0_el1=0 id_aa64isar1_el1=0 id_aa64mmfr0_el1=15728642 id_aa64mmfr1_el1=0 -id_aa64pfr0_el1=17 -id_aa64pfr1_el1=0 id_isar0=34607377 id_isar1=34677009 id_isar2=555950401 @@ -265,8 +268,6 @@ id_mmfr0=270536963 id_mmfr1=0 id_mmfr2=19070976 id_mmfr3=34611729 -id_pfr0=49 -id_pfr1=4113 midr=1091551472 pmu=Null system=system @@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -346,6 +347,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -358,15 +360,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -402,7 +405,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -411,14 +414,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -442,6 +446,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -453,7 +458,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -461,6 +466,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -469,6 +481,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -476,7 +489,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 4f7f76cdc..b914fe569 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:37:41 -gem5 started Jul 21 2016 14:38:23 -gem5 executing on e108600-lin, pid 23085 -command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing +gem5 compiled Apr 3 2017 17:55:48 +gem5 started Apr 3 2017 18:13:17 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56989 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 28298500 because target called exit() +Exiting @ tick 28648500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 3c58db434..76c17a485 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,630 +1,630 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28648500 # Number of ticks simulated -final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 484095 # Simulator instruction rate (inst/s) -host_op_rate 564461 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3030833923 # Simulator tick rate (ticks/s) -host_mem_usage 267516 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4566 # Number of instructions simulated -sim_ops 5330 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 22400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dtb.walker.walks 0 # Table walker walks requested -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.inst_hits 0 # ITB inst hits -system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits -system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses -system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits -system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses -system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits -system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses -system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses -system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses -system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses -system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits -system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses -system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.walks 0 # Table walker walks requested -system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 0 # ITB inst hits -system.cpu.itb.inst_misses 0 # ITB inst misses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed -system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB -system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch -system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 0 # ITB inst accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 13 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 57297 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4566 # Number of instructions committed -system.cpu.committedOps 5330 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls -system.cpu.num_int_insts 4624 # number of integer instructions -system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 7538 # number of times the integer registers were read -system.cpu.num_int_register_writes 2728 # number of times the integer registers were written -system.cpu.num_fp_register_reads 16 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read -system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written -system.cpu.num_mem_refs 1965 # number of memory refs -system.cpu.num_load_insts 1027 # Number of load instructions -system.cpu.num_store_insts 938 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1008 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction -system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction -system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction -system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5391 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits -system.cpu.dcache.overall_hits::total 1764 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.dcache.overall_misses::total 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits -system.cpu.icache.overall_hits::total 4365 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1 # number of writebacks -system.cpu.icache.writebacks::total 1 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits -system.cpu.l2cache.overall_hits::total 32 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses -system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 307 # Transaction distribution -system.membus.trans_dist::ReadExReq 43 # Transaction distribution -system.membus.trans_dist::ReadExResp 43 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 350 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.1 # Layer utilization (%) +sim_seconds 0.000029 +sim_ticks 28648500 +final_tick 28648500 +sim_freq 1000000000000 +host_inst_rate 277751 +host_op_rate 323869 +host_tick_rate 1739012040 +host_mem_usage 279272 +host_seconds 0.02 +sim_insts 4566 +sim_ops 5330 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 +system.physmem.bytes_read::cpu.inst 14400 +system.physmem.bytes_read::cpu.data 8000 +system.physmem.bytes_read::total 22400 +system.physmem.bytes_inst_read::cpu.inst 14400 +system.physmem.bytes_inst_read::total 14400 +system.physmem.num_reads::cpu.inst 225 +system.physmem.num_reads::cpu.data 125 +system.physmem.num_reads::total 350 +system.physmem.bw_read::cpu.inst 502644117 +system.physmem.bw_read::cpu.data 279246732 +system.physmem.bw_read::total 781890849 +system.physmem.bw_inst_read::cpu.inst 502644117 +system.physmem.bw_inst_read::total 502644117 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+system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 +system.cpu.toL2Bus.trans_dist::ReadResp 339 +system.cpu.toL2Bus.trans_dist::WritebackClean 1 +system.cpu.toL2Bus.trans_dist::ReadExReq 43 +system.cpu.toL2Bus.trans_dist::ReadExResp 43 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 +system.cpu.toL2Bus.pkt_count::total 765 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 +system.cpu.toL2Bus.pkt_size::total 24512 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 382 +system.cpu.toL2Bus.snoop_fanout::mean 0.083770 +system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% +system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 382 +system.cpu.toL2Bus.reqLayer0.occupancy 192500 +system.cpu.toL2Bus.reqLayer0.utilization 0.7 +system.cpu.toL2Bus.respLayer0.occupancy 361500 +system.cpu.toL2Bus.respLayer0.utilization 1.3 +system.cpu.toL2Bus.respLayer1.occupancy 211500 +system.cpu.toL2Bus.respLayer1.utilization 0.7 +system.membus.snoop_filter.tot_requests 350 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 +system.membus.trans_dist::ReadResp 307 +system.membus.trans_dist::ReadExReq 43 +system.membus.trans_dist::ReadExResp 43 +system.membus.trans_dist::ReadSharedReq 307 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 +system.membus.pkt_count::total 700 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 +system.membus.pkt_size::total 22400 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 350 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 350 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 350 +system.membus.reqLayer0.occupancy 355500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1750000 +system.membus.respLayer1.utilization 6.1 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 70198a6d7..c234169e9 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -66,7 +66,7 @@ UnifiedTLB=true activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -140,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -716,7 +717,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -725,14 +726,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 5b262649f..a796e3972 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:37:43 -gem5 started Nov 29 2016 18:37:59 -gem5 executing on zizzer, pid 53433 -command line: /z/powerjg/gem5-upstream/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing +gem5 compiled Apr 3 2017 19:22:30 +gem5 started Apr 3 2017 19:22:48 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 103796 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 21268000 because target called exit() +Exiting @ tick 21189000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 804710aed..189de9f2f 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,1012 +1,1012 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21189000 # Number of ticks simulated -final_tick 21189000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 143245 # Simulator instruction rate (inst/s) -host_op_rate 143198 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 523712790 # Simulator tick rate (ticks/s) -host_mem_usage 249592 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5792 # Number of instructions simulated -sim_ops 5792 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28352 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 443 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1029968380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308084383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1338052763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1029968380 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1029968380 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308084383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1338052763 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 444 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 71 # Per bank write bursts -system.physmem.perBankRdBursts::1 42 # Per bank write bursts -system.physmem.perBankRdBursts::2 55 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts -system.physmem.perBankRdBursts::4 53 # Per bank write bursts -system.physmem.perBankRdBursts::5 61 # Per bank write bursts -system.physmem.perBankRdBursts::6 52 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 9 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 1 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 0 # Per bank write bursts -system.physmem.perBankRdBursts::13 0 # Per bank write bursts -system.physmem.perBankRdBursts::14 4 # Per bank write bursts -system.physmem.perBankRdBursts::15 0 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21128500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 444 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 235 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.631579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 212.894378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.912685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 11.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation -system.physmem.totQLat 5920000 # Total ticks spent queuing -system.physmem.totMemAccLat 14245000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13333.33 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32083.33 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1341.07 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1341.07 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.48 # Data bus utilization in percentage -system.physmem.busUtilRead 10.48 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 358 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47586.71 # Average gap between requests -system.physmem.pageHitRate 80.63 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 528360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 254265 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2870280 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3925590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5657820 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 38400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 14532315 # Total energy per rank (pJ) -system.physmem_0.averagePower 685.810052 # Core power per rank (mW) -system.physmem_0.totalIdleTime 12505250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 100250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8146250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12405000 # Time in different power states -system.physmem_1.actEnergy 85680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 34155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 299880 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 759810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1412160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 6380010 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 712320 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 10913295 # Total energy per rank (pJ) -system.physmem_1.averagePower 515.021000 # Core power per rank (mW) -system.physmem_1.totalIdleTime 13660000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3594000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1854750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1229000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 13991250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 2458 # Number of BP lookups -system.cpu.branchPred.condPredicted 2033 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 409 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2104 # Number of BTB lookups -system.cpu.branchPred.BTBHits 724 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.410646 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 228 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 135 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 18 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 117 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 37 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 21189000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 42379 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7639 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13455 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2458 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4277 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 847 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 146 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1865 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.075368 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.471061 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10164 81.23% 81.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 163 1.30% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 210 1.68% 84.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 146 1.17% 85.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 1.97% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 148 1.18% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 304 2.43% 90.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 158 1.26% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 972 7.77% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.058000 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.317492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7217 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2933 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1957 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 275 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 791 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 149 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11520 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 456 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 275 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7386 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 930 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1904 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11074 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 22 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1496 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9775 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17991 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17965 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4777 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 402 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1923 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1570 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 32 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8807 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 41 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4477 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3567 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12512 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.703884 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.500750 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9387 75.02% 75.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 964 7.70% 82.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 667 5.33% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 467 3.73% 91.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 439 3.51% 95.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.32% 97.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 213 1.70% 99.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 56 0.45% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 29 0.23% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12512 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 12 6.22% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 87 45.08% 51.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 83 43.01% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 94.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 11 5.70% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5542 62.93% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1815 20.61% 83.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1422 16.15% 99.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 2 0.02% 99.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 24 0.27% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8807 # Type of FU issued -system.cpu.iq.rate 0.207815 # Inst issue rate -system.cpu.iq.fu_busy_cnt 193 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.021914 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14716 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8133 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 67 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8961 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 39 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 84 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 962 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 524 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 275 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10269 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1923 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1570 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 53 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 256 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 327 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8488 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1719 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 319 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3083 # number of memory reference insts executed -system.cpu.iew.exec_branches 1364 # Number of branches executed -system.cpu.iew.exec_stores 1364 # Number of stores executed -system.cpu.iew.exec_rate 0.200288 # Inst execution rate -system.cpu.iew.wb_sent 8262 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8160 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4466 # num instructions producing a value -system.cpu.iew.wb_consumers 7207 # num instructions consuming a value -system.cpu.iew.wb_rate 0.192548 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619675 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 4479 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 270 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11808 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.351526 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9643 81.66% 81.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 845 7.16% 88.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 531 4.50% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 215 1.82% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.50% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 0.93% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 132 1.12% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 50 0.42% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.89% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11808 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5792 # Number of instructions committed -system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2007 # Number of memory references committed -system.cpu.commit.loads 961 # Number of loads committed -system.cpu.commit.membars 7 # Number of memory barriers committed -system.cpu.commit.branches 1037 # Number of branches committed -system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. -system.cpu.commit.int_insts 5698 # Number of committed integer instructions. -system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 960 16.57% 81.92% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 1027 17.73% 99.65% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.67% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 19 0.33% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 21974 # The number of ROB reads -system.cpu.rob.rob_writes 21247 # The number of ROB writes -system.cpu.timesIdled 227 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29867 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5792 # Number of Instructions Simulated -system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.316816 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.316816 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136671 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136671 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13468 # number of integer regfile reads -system.cpu.int_regfile_writes 7187 # number of integer regfile writes -system.cpu.fp_regfile_reads 25 # number of floating regfile reads -system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 66.953799 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2204 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 104 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 21.192308 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 66.953799 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.016346 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 80 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.025391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5386 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5386 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 721 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 721 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2204 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2204 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2204 # number of overall hits -system.cpu.dcache.overall_hits::total 2204 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8129500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8129500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 32497996 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 32497996 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 40627496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 40627496 # number of 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# average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 92969.098398 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 92969.098398 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 749 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.222222 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 278 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 278 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 332 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 332 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 58 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 58 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83068.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83068.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99882.936170 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99882.936170 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90595.219048 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 90595.219048 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states 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Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4079 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4079 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1435 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1435 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1435 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1435 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1435 # number of overall hits -system.cpu.icache.overall_hits::total 1435 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 430 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 430 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 430 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 430 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 430 # number of overall misses -system.cpu.icache.overall_misses::total 430 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 33426000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 33426000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 33426000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 33426000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 33426000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1865 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1865 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1865 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1865 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1865 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230563 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230563 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230563 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230563 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230563 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230563 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77734.883721 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77734.883721 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77734.883721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77734.883721 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77734.883721 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 569 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 113.800000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28154000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28154000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28154000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28154000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.187668 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.187668 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.187668 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80440 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80440 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80440 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 80440 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 232.210591 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 443 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.022573 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 166.990617 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 65.219974 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005096 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001990 # Average percentage of cache occupancy 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number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 10 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 10 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 56 # number of ReadSharedReq misses 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for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.977143 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.965517 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.977143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.978022 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.977143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.978022 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98308.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98308.510638 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80520.467836 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80520.467836 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84089.285714 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84089.285714 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80520.467836 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90577.669903 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82848.314607 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 56 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4150500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24128000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4159000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24128000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8309500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32437500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24128000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8309500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32437500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.977143 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.965517 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.978022 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.977143 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.978022 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88308.510638 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70549.707602 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 74267.857143 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70549.707602 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.757282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72893.258427 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 455 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 350 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 58 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 209 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 908 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 455 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021978 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.146773 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 445 97.80% 97.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 10 2.20% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 455 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 227500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 523500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 156000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 444 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 396 # Transaction distribution -system.membus.trans_dist::ReadExReq 47 # Transaction distribution -system.membus.trans_dist::ReadExResp 47 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 397 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 887 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28352 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 444 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 553000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2325750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.0 # Layer utilization (%) +sim_seconds 0.000021 +sim_ticks 21189000 +final_tick 21189000 +sim_freq 1000000000000 +host_inst_rate 70012 +host_op_rate 69995 +host_tick_rate 256014000 +host_mem_usage 260844 +host_seconds 0.08 +sim_insts 5792 +sim_ops 5792 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 21189000 +system.physmem.bytes_read::cpu.inst 21824 +system.physmem.bytes_read::cpu.data 6528 +system.physmem.bytes_read::total 28352 +system.physmem.bytes_inst_read::cpu.inst 21824 +system.physmem.bytes_inst_read::total 21824 +system.physmem.num_reads::cpu.inst 341 +system.physmem.num_reads::cpu.data 102 +system.physmem.num_reads::total 443 +system.physmem.bw_read::cpu.inst 1029968380 +system.physmem.bw_read::cpu.data 308084383 +system.physmem.bw_read::total 1338052763 +system.physmem.bw_inst_read::cpu.inst 1029968380 +system.physmem.bw_inst_read::total 1029968380 +system.physmem.bw_total::cpu.inst 1029968380 +system.physmem.bw_total::cpu.data 308084383 +system.physmem.bw_total::total 1338052763 +system.physmem.readReqs 444 +system.physmem.writeReqs 0 +system.physmem.readBursts 444 +system.physmem.writeBursts 0 +system.physmem.bytesReadDRAM 28416 +system.physmem.bytesReadWrQ 0 +system.physmem.bytesWritten 0 +system.physmem.bytesReadSys 28416 +system.physmem.bytesWrittenSys 0 +system.physmem.servicedByWrQ 0 +system.physmem.mergedWrBursts 0 +system.physmem.neitherReadNorWriteReqs 0 +system.physmem.perBankRdBursts::0 71 +system.physmem.perBankRdBursts::1 42 +system.physmem.perBankRdBursts::2 55 +system.physmem.perBankRdBursts::3 58 +system.physmem.perBankRdBursts::4 53 +system.physmem.perBankRdBursts::5 61 +system.physmem.perBankRdBursts::6 52 +system.physmem.perBankRdBursts::7 10 +system.physmem.perBankRdBursts::8 9 +system.physmem.perBankRdBursts::9 28 +system.physmem.perBankRdBursts::10 1 +system.physmem.perBankRdBursts::11 0 +system.physmem.perBankRdBursts::12 0 +system.physmem.perBankRdBursts::13 0 +system.physmem.perBankRdBursts::14 4 +system.physmem.perBankRdBursts::15 0 +system.physmem.perBankWrBursts::0 0 +system.physmem.perBankWrBursts::1 0 +system.physmem.perBankWrBursts::2 0 +system.physmem.perBankWrBursts::3 0 +system.physmem.perBankWrBursts::4 0 +system.physmem.perBankWrBursts::5 0 +system.physmem.perBankWrBursts::6 0 +system.physmem.perBankWrBursts::7 0 +system.physmem.perBankWrBursts::8 0 +system.physmem.perBankWrBursts::9 0 +system.physmem.perBankWrBursts::10 0 +system.physmem.perBankWrBursts::11 0 +system.physmem.perBankWrBursts::12 0 +system.physmem.perBankWrBursts::13 0 +system.physmem.perBankWrBursts::14 0 +system.physmem.perBankWrBursts::15 0 +system.physmem.numRdRetry 0 +system.physmem.numWrRetry 0 +system.physmem.totGap 21128500 +system.physmem.readPktSize::0 0 +system.physmem.readPktSize::1 0 +system.physmem.readPktSize::2 0 +system.physmem.readPktSize::3 0 +system.physmem.readPktSize::4 0 +system.physmem.readPktSize::5 0 +system.physmem.readPktSize::6 444 +system.physmem.writePktSize::0 0 +system.physmem.writePktSize::1 0 +system.physmem.writePktSize::2 0 +system.physmem.writePktSize::3 0 +system.physmem.writePktSize::4 0 +system.physmem.writePktSize::5 0 +system.physmem.writePktSize::6 0 +system.physmem.rdQLenPdf::0 235 +system.physmem.rdQLenPdf::1 144 +system.physmem.rdQLenPdf::2 45 +system.physmem.rdQLenPdf::3 14 +system.physmem.rdQLenPdf::4 5 +system.physmem.rdQLenPdf::5 1 +system.physmem.rdQLenPdf::6 0 +system.physmem.rdQLenPdf::7 0 +system.physmem.rdQLenPdf::8 0 +system.physmem.rdQLenPdf::9 0 +system.physmem.rdQLenPdf::10 0 +system.physmem.rdQLenPdf::11 0 +system.physmem.rdQLenPdf::12 0 +system.physmem.rdQLenPdf::13 0 +system.physmem.rdQLenPdf::14 0 +system.physmem.rdQLenPdf::15 0 +system.physmem.rdQLenPdf::16 0 +system.physmem.rdQLenPdf::17 0 +system.physmem.rdQLenPdf::18 0 +system.physmem.rdQLenPdf::19 0 +system.physmem.rdQLenPdf::20 0 +system.physmem.rdQLenPdf::21 0 +system.physmem.rdQLenPdf::22 0 +system.physmem.rdQLenPdf::23 0 +system.physmem.rdQLenPdf::24 0 +system.physmem.rdQLenPdf::25 0 +system.physmem.rdQLenPdf::26 0 +system.physmem.rdQLenPdf::27 0 +system.physmem.rdQLenPdf::28 0 +system.physmem.rdQLenPdf::29 0 +system.physmem.rdQLenPdf::30 0 +system.physmem.rdQLenPdf::31 0 +system.physmem.wrQLenPdf::0 0 +system.physmem.wrQLenPdf::1 0 +system.physmem.wrQLenPdf::2 0 +system.physmem.wrQLenPdf::3 0 +system.physmem.wrQLenPdf::4 0 +system.physmem.wrQLenPdf::5 0 +system.physmem.wrQLenPdf::6 0 +system.physmem.wrQLenPdf::7 0 +system.physmem.wrQLenPdf::8 0 +system.physmem.wrQLenPdf::9 0 +system.physmem.wrQLenPdf::10 0 +system.physmem.wrQLenPdf::11 0 +system.physmem.wrQLenPdf::12 0 +system.physmem.wrQLenPdf::13 0 +system.physmem.wrQLenPdf::14 0 +system.physmem.wrQLenPdf::15 0 +system.physmem.wrQLenPdf::16 0 +system.physmem.wrQLenPdf::17 0 +system.physmem.wrQLenPdf::18 0 +system.physmem.wrQLenPdf::19 0 +system.physmem.wrQLenPdf::20 0 +system.physmem.wrQLenPdf::21 0 +system.physmem.wrQLenPdf::22 0 +system.physmem.wrQLenPdf::23 0 +system.physmem.wrQLenPdf::24 0 +system.physmem.wrQLenPdf::25 0 +system.physmem.wrQLenPdf::26 0 +system.physmem.wrQLenPdf::27 0 +system.physmem.wrQLenPdf::28 0 +system.physmem.wrQLenPdf::29 0 +system.physmem.wrQLenPdf::30 0 +system.physmem.wrQLenPdf::31 0 +system.physmem.wrQLenPdf::32 0 +system.physmem.wrQLenPdf::33 0 +system.physmem.wrQLenPdf::34 0 +system.physmem.wrQLenPdf::35 0 +system.physmem.wrQLenPdf::36 0 +system.physmem.wrQLenPdf::37 0 +system.physmem.wrQLenPdf::38 0 +system.physmem.wrQLenPdf::39 0 +system.physmem.wrQLenPdf::40 0 +system.physmem.wrQLenPdf::41 0 +system.physmem.wrQLenPdf::42 0 +system.physmem.wrQLenPdf::43 0 +system.physmem.wrQLenPdf::44 0 +system.physmem.wrQLenPdf::45 0 +system.physmem.wrQLenPdf::46 0 +system.physmem.wrQLenPdf::47 0 +system.physmem.wrQLenPdf::48 0 +system.physmem.wrQLenPdf::49 0 +system.physmem.wrQLenPdf::50 0 +system.physmem.wrQLenPdf::51 0 +system.physmem.wrQLenPdf::52 0 +system.physmem.wrQLenPdf::53 0 +system.physmem.wrQLenPdf::54 0 +system.physmem.wrQLenPdf::55 0 +system.physmem.wrQLenPdf::56 0 +system.physmem.wrQLenPdf::57 0 +system.physmem.wrQLenPdf::58 0 +system.physmem.wrQLenPdf::59 0 +system.physmem.wrQLenPdf::60 0 +system.physmem.wrQLenPdf::61 0 +system.physmem.wrQLenPdf::62 0 +system.physmem.wrQLenPdf::63 0 +system.physmem.bytesPerActivate::samples 76 +system.physmem.bytesPerActivate::mean 348.631579 +system.physmem.bytesPerActivate::gmean 212.894378 +system.physmem.bytesPerActivate::stdev 337.912685 +system.physmem.bytesPerActivate::0-127 24 31.58% 31.58% +system.physmem.bytesPerActivate::128-255 17 22.37% 53.95% +system.physmem.bytesPerActivate::256-383 12 15.79% 69.74% +system.physmem.bytesPerActivate::384-511 2 2.63% 72.37% +system.physmem.bytesPerActivate::512-639 3 3.95% 76.32% +system.physmem.bytesPerActivate::640-767 4 5.26% 81.58% +system.physmem.bytesPerActivate::768-895 2 2.63% 84.21% +system.physmem.bytesPerActivate::896-1023 3 3.95% 88.16% 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+system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 21189000 +system.membus.trans_dist::ReadResp 396 +system.membus.trans_dist::ReadExReq 47 +system.membus.trans_dist::ReadExResp 47 +system.membus.trans_dist::ReadSharedReq 397 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887 +system.membus.pkt_count::total 887 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28352 +system.membus.pkt_size::total 28352 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 444 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 444 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 444 +system.membus.reqLayer0.occupancy 553000 +system.membus.reqLayer0.utilization 2.6 +system.membus.respLayer1.occupancy 2325750 +system.membus.respLayer1.utilization 11.0 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index b654cdd15..a94f4dc46 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -89,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -119,7 +120,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -128,14 +129,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/power/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -159,6 +161,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -170,7 +173,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -178,6 +181,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -186,6 +196,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -193,7 +204,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index cbf63eeba..e1a395fe5 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:27:08 -gem5 started Jul 21 2016 14:27:33 -gem5 executing on e108600-lin, pid 28000 -command line: /work/curdun01/gem5-external.hg/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic +gem5 compiled Apr 3 2017 19:22:30 +gem5 started Apr 3 2017 19:22:48 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 103795 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2896000 because target called exit() +Exiting @ tick 2896000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index d149f60ec..ecd255c85 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2896000 # Number of ticks simulated -final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1025115 # Simulator instruction rate (inst/s) -host_op_rate 1023244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 510651564 # Simulator tick rate (ticks/s) -host_mem_usage 238048 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5793 # Number of instructions simulated -sim_ops 5793 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 3720 # Number of bytes read from this memory -system.physmem.bytes_read::total 26892 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 23172 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 23172 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 4209 # Number of bytes written to this memory -system.physmem.bytes_written::total 4209 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5793 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 961 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6754 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 1046 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8001381215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1284530387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9285911602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8001381215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8001381215 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1453383978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1453383978 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.numSyscalls 9 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2896000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5793 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5793 # Number of instructions committed -system.cpu.committedOps 5793 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 5698 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses -system.cpu.num_func_calls 200 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 895 # number of instructions that are conditional controls -system.cpu.num_int_insts 5698 # number of integer instructions -system.cpu.num_fp_insts 22 # number of float instructions -system.cpu.num_int_register_reads 9529 # number of times the integer registers were read -system.cpu.num_int_register_writes 4996 # number of times the integer registers were written -system.cpu.num_fp_register_reads 20 # number of times the floating registers were read -system.cpu.num_fp_register_writes 2 # number of times the floating registers were written -system.cpu.num_mem_refs 2007 # number of memory refs -system.cpu.num_load_insts 961 # Number of load instructions -system.cpu.num_store_insts 1046 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5792.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1037 # Number of branches fetched -system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3784 65.32% 65.32% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 65.32% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 65.32% # Class of executed instruction -system.cpu.op_class::FloatAdd 2 0.03% 65.35% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% # Class of executed instruction -system.cpu.op_class::MemRead 960 16.57% 81.93% # Class of executed instruction -system.cpu.op_class::MemWrite 1027 17.73% 99.65% # Class of executed instruction -system.cpu.op_class::FloatMemRead 1 0.02% 99.67% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5793 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6754 # Transaction distribution -system.membus.trans_dist::ReadResp 6754 # Transaction distribution -system.membus.trans_dist::WriteReq 1046 # Transaction distribution -system.membus.trans_dist::WriteResp 1046 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7800 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7800 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7800 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2896000 +final_tick 2896000 +sim_freq 1000000000000 +host_inst_rate 591136 +host_op_rate 589882 +host_tick_rate 294306849 +host_mem_usage 250080 +host_seconds 0.01 +sim_insts 5793 +sim_ops 5793 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2896000 +system.physmem.bytes_read::cpu.inst 23172 +system.physmem.bytes_read::cpu.data 3720 +system.physmem.bytes_read::total 26892 +system.physmem.bytes_inst_read::cpu.inst 23172 +system.physmem.bytes_inst_read::total 23172 +system.physmem.bytes_written::cpu.data 4209 +system.physmem.bytes_written::total 4209 +system.physmem.num_reads::cpu.inst 5793 +system.physmem.num_reads::cpu.data 961 +system.physmem.num_reads::total 6754 +system.physmem.num_writes::cpu.data 1046 +system.physmem.num_writes::total 1046 +system.physmem.bw_read::cpu.inst 8001381215 +system.physmem.bw_read::cpu.data 1284530387 +system.physmem.bw_read::total 9285911602 +system.physmem.bw_inst_read::cpu.inst 8001381215 +system.physmem.bw_inst_read::total 8001381215 +system.physmem.bw_write::cpu.data 1453383978 +system.physmem.bw_write::total 1453383978 +system.physmem.bw_total::cpu.inst 8001381215 +system.physmem.bw_total::cpu.data 2737914365 +system.physmem.bw_total::total 10739295580 +system.pwrStateResidencyTicks::UNDEFINED 2896000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.read_hits 0 +system.cpu.dtb.read_misses 0 +system.cpu.dtb.read_accesses 0 +system.cpu.dtb.write_hits 0 +system.cpu.dtb.write_misses 0 +system.cpu.dtb.write_accesses 0 +system.cpu.dtb.hits 0 +system.cpu.dtb.misses 0 +system.cpu.dtb.accesses 0 +system.cpu.itb.read_hits 0 +system.cpu.itb.read_misses 0 +system.cpu.itb.read_accesses 0 +system.cpu.itb.write_hits 0 +system.cpu.itb.write_misses 0 +system.cpu.itb.write_accesses 0 +system.cpu.itb.hits 0 +system.cpu.itb.misses 0 +system.cpu.itb.accesses 0 +system.cpu.workload.numSyscalls 9 +system.cpu.pwrStateResidencyTicks::ON 2896000 +system.cpu.numCycles 5793 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5793 +system.cpu.committedOps 5793 +system.cpu.num_int_alu_accesses 5698 +system.cpu.num_fp_alu_accesses 22 +system.cpu.num_func_calls 200 +system.cpu.num_conditional_control_insts 895 +system.cpu.num_int_insts 5698 +system.cpu.num_fp_insts 22 +system.cpu.num_int_register_reads 9529 +system.cpu.num_int_register_writes 4996 +system.cpu.num_fp_register_reads 20 +system.cpu.num_fp_register_writes 2 +system.cpu.num_mem_refs 2007 +system.cpu.num_load_insts 961 +system.cpu.num_store_insts 1046 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5793 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1037 +system.cpu.op_class::No_OpClass 0 0.00% 0.00% +system.cpu.op_class::IntAlu 3784 65.32% 65.32% +system.cpu.op_class::IntMult 0 0.00% 65.32% +system.cpu.op_class::IntDiv 0 0.00% 65.32% +system.cpu.op_class::FloatAdd 2 0.03% 65.35% +system.cpu.op_class::FloatCmp 0 0.00% 65.35% +system.cpu.op_class::FloatCvt 0 0.00% 65.35% +system.cpu.op_class::FloatMult 0 0.00% 65.35% +system.cpu.op_class::FloatMultAcc 0 0.00% 65.35% +system.cpu.op_class::FloatDiv 0 0.00% 65.35% +system.cpu.op_class::FloatMisc 0 0.00% 65.35% +system.cpu.op_class::FloatSqrt 0 0.00% 65.35% +system.cpu.op_class::SimdAdd 0 0.00% 65.35% +system.cpu.op_class::SimdAddAcc 0 0.00% 65.35% +system.cpu.op_class::SimdAlu 0 0.00% 65.35% +system.cpu.op_class::SimdCmp 0 0.00% 65.35% +system.cpu.op_class::SimdCvt 0 0.00% 65.35% +system.cpu.op_class::SimdMisc 0 0.00% 65.35% +system.cpu.op_class::SimdMult 0 0.00% 65.35% +system.cpu.op_class::SimdMultAcc 0 0.00% 65.35% +system.cpu.op_class::SimdShift 0 0.00% 65.35% +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.35% +system.cpu.op_class::SimdSqrt 0 0.00% 65.35% +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.35% +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.35% +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.35% +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.35% +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMisc 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMult 0 0.00% 65.35% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.35% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.35% +system.cpu.op_class::MemRead 960 16.57% 81.93% +system.cpu.op_class::MemWrite 1027 17.73% 99.65% +system.cpu.op_class::FloatMemRead 1 0.02% 99.67% +system.cpu.op_class::FloatMemWrite 19 0.33% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5793 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2896000 +system.membus.trans_dist::ReadReq 6754 +system.membus.trans_dist::ReadResp 6754 +system.membus.trans_dist::WriteReq 1046 +system.membus.trans_dist::WriteResp 1046 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 +system.membus.pkt_count::total 15600 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 +system.membus.pkt_size::total 31101 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 7800 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 7800 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 7800 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index c79232133..90a496871 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -88,6 +88,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -118,7 +119,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -127,14 +128,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -158,6 +160,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -169,7 +172,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -177,6 +180,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -185,6 +195,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -192,7 +203,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 0783a6d90..cac26c8a8 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38676 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:40 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64886 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 2694500 because target called exit() +Hello World!Exiting @ tick 2694500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 22810bda7..6ce9e512f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -1,135 +1,135 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2694500 # Number of ticks simulated -final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 818529 # Simulator instruction rate (inst/s) -host_op_rate 815458 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 411063520 # Simulator tick rate (ticks/s) -host_mem_usage 239556 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4602 # Number of bytes read from this memory -system.physmem.bytes_read::total 26082 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21480 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 5065 # Number of bytes written to this memory -system.physmem.bytes_written::total 5065 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5370 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 715 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6085 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 673 # Number of write requests responded to by this memory -system.physmem.num_writes::total 673 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7971794396 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1707923548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9679717944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7971794396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7971794396 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1879755057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1879755057 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 2694500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 5390 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4846 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 6085 # Transaction distribution -system.membus.trans_dist::ReadResp 6085 # Transaction distribution -system.membus.trans_dist::WriteReq 673 # Transaction distribution -system.membus.trans_dist::WriteResp 673 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 6758 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6758 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6758 # Request fanout histogram +sim_seconds 0.000003 +sim_ticks 2694500 +final_tick 2694500 +sim_freq 1000000000000 +host_inst_rate 549051 +host_op_rate 547755 +host_tick_rate 276495662 +host_mem_usage 251832 +host_seconds 0.01 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 2694500 +system.physmem.bytes_read::cpu.inst 21480 +system.physmem.bytes_read::cpu.data 4602 +system.physmem.bytes_read::total 26082 +system.physmem.bytes_inst_read::cpu.inst 21480 +system.physmem.bytes_inst_read::total 21480 +system.physmem.bytes_written::cpu.data 5065 +system.physmem.bytes_written::total 5065 +system.physmem.num_reads::cpu.inst 5370 +system.physmem.num_reads::cpu.data 715 +system.physmem.num_reads::total 6085 +system.physmem.num_writes::cpu.data 673 +system.physmem.num_writes::total 673 +system.physmem.bw_read::cpu.inst 7971794396 +system.physmem.bw_read::cpu.data 1707923548 +system.physmem.bw_read::total 9679717944 +system.physmem.bw_inst_read::cpu.inst 7971794396 +system.physmem.bw_inst_read::total 7971794396 +system.physmem.bw_write::cpu.data 1879755057 +system.physmem.bw_write::total 1879755057 +system.physmem.bw_total::cpu.inst 7971794396 +system.physmem.bw_total::cpu.data 3587678605 +system.physmem.bw_total::total 11559473001 +system.pwrStateResidencyTicks::UNDEFINED 2694500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 2694500 +system.cpu.numCycles 5390 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5327 +system.cpu.committedOps 5327 +system.cpu.num_int_alu_accesses 4505 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 773 +system.cpu.num_int_insts 4505 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10598 +system.cpu.num_int_register_writes 4846 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1401 +system.cpu.num_load_insts 723 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 5390 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1121 +system.cpu.op_class::No_OpClass 173 3.22% 3.22% +system.cpu.op_class::IntAlu 3796 70.69% 73.91% +system.cpu.op_class::IntMult 0 0.00% 73.91% +system.cpu.op_class::IntDiv 0 0.00% 73.91% +system.cpu.op_class::FloatAdd 0 0.00% 73.91% +system.cpu.op_class::FloatCmp 0 0.00% 73.91% +system.cpu.op_class::FloatCvt 0 0.00% 73.91% +system.cpu.op_class::FloatMult 0 0.00% 73.91% +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::FloatDiv 0 0.00% 73.91% +system.cpu.op_class::FloatMisc 0 0.00% 73.91% +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdAdd 0 0.00% 73.91% +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% +system.cpu.op_class::SimdAlu 0 0.00% 73.91% +system.cpu.op_class::SimdCmp 0 0.00% 73.91% +system.cpu.op_class::SimdCvt 0 0.00% 73.91% +system.cpu.op_class::SimdMisc 0 0.00% 73.91% +system.cpu.op_class::SimdMult 0 0.00% 73.91% +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdShift 0 0.00% 73.91% +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% +system.cpu.op_class::MemRead 723 13.46% 87.37% +system.cpu.op_class::MemWrite 678 12.63% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5370 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 2694500 +system.membus.trans_dist::ReadReq 6085 +system.membus.trans_dist::ReadResp 6085 +system.membus.trans_dist::WriteReq 673 +system.membus.trans_dist::WriteResp 673 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 +system.membus.pkt_count::total 13516 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 +system.membus.pkt_size::total 31147 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 6758 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 6758 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 6758 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 7609bf228..74133b340 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -122,7 +123,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -131,14 +132,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -297,6 +299,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 36ed80c84..8d604768a 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 13 2016 20:43:27 -gem5 started Oct 13 2016 20:46:33 -gem5 executing on e108600-lin, pid 17405 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:37 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64825 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 86746 because target called exit() +Hello World!Exiting @ tick 86746 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 05934eae0..83a3d1ad4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -1,355 +1,355 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000087 # Number of seconds simulated -sim_ticks 86746 # Number of ticks simulated -final_tick 86746 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 122857 # Simulator instruction rate (inst/s) -host_op_rate 122829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1999767 # Simulator tick rate (ticks/s) -host_mem_usage 415460 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 82496 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 82240 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1289 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1285 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 951006386 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 948055242 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1899061628 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1289 # Number of read requests accepted -system.mem_ctrls.writeReqs 1285 # Number of write requests accepted -system.mem_ctrls.readBursts 1289 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1285 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 44800 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 37696 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 45504 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 82496 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 82240 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 589 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 555 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 17 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 119 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 121 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 55 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 31 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 13 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 62 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 21 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 61 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 14 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 18 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 1 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 118 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 114 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 141 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 61 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 14 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 62 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 23 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 64 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 16 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 8 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 86680 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1289 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1285 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 700 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 3 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 35 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 45 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 49 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 46 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 247 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 359.384615 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 236.451062 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 319.751749 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 247 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 44 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 15.840909 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.640724 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.183849 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 44 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 44 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.159091 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.147705 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.644951 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 44 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12987 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 26287 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3500 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 18.55 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 37.55 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 516.45 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 524.57 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 951.01 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 948.06 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 8.13 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 4.03 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 4.10 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.18 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 508 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 652 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 72.57 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 89.32 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.68 # Average gap between requests -system.mem_ctrls.pageHitRate 81.12 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 1099560 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 587328 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 4969440 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 3574656 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10338432 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 148224 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 27605784 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 1209216 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 56293680 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 648.948424 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 63519 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 64 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 20134 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 # Time in different power states -system.mem_ctrls_1.actEnergy 692580 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 367080 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 3027360 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 2363616 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9621600 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 296448 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 26302992 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 2761728 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 52194444 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 601.692804 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 64843 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 422 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2860 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18590 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86746 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 86746 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.999988 # Number of idle cycles -system.cpu.num_busy_cycles 86745.000012 # Number of busy cycles -system.cpu.not_idle_fraction 0.999988 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000012 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2574 # delay histogram for all message -system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2574 # delay histogram for all message +sim_seconds 0.000087 +sim_ticks 86746 +final_tick 86746 +sim_freq 1000000000 +host_inst_rate 50496 +host_op_rate 50484 +host_tick_rate 821944 +host_mem_usage 426428 +host_seconds 0.11 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 86746 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 82496 +system.mem_ctrls.bytes_read::total 82496 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 82240 +system.mem_ctrls.bytes_written::total 82240 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1289 +system.mem_ctrls.num_reads::total 1289 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1285 +system.mem_ctrls.num_writes::total 1285 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 951006386 +system.mem_ctrls.bw_read::total 951006386 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 948055242 +system.mem_ctrls.bw_write::total 948055242 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1899061628 +system.mem_ctrls.bw_total::total 1899061628 +system.mem_ctrls.readReqs 1289 +system.mem_ctrls.writeReqs 1285 +system.mem_ctrls.readBursts 1289 +system.mem_ctrls.writeBursts 1285 +system.mem_ctrls.bytesReadDRAM 44800 +system.mem_ctrls.bytesReadWrQ 37696 +system.mem_ctrls.bytesWritten 45504 +system.mem_ctrls.bytesReadSys 82496 +system.mem_ctrls.bytesWrittenSys 82240 +system.mem_ctrls.servicedByWrQ 589 +system.mem_ctrls.mergedWrBursts 555 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 28 +system.mem_ctrls.perBankRdBursts::1 17 +system.mem_ctrls.perBankRdBursts::2 1 +system.mem_ctrls.perBankRdBursts::3 8 +system.mem_ctrls.perBankRdBursts::4 0 +system.mem_ctrls.perBankRdBursts::5 119 +system.mem_ctrls.perBankRdBursts::6 121 +system.mem_ctrls.perBankRdBursts::7 141 +system.mem_ctrls.perBankRdBursts::8 55 +system.mem_ctrls.perBankRdBursts::9 31 +system.mem_ctrls.perBankRdBursts::10 13 +system.mem_ctrls.perBankRdBursts::11 62 +system.mem_ctrls.perBankRdBursts::12 21 +system.mem_ctrls.perBankRdBursts::13 61 +system.mem_ctrls.perBankRdBursts::14 14 +system.mem_ctrls.perBankRdBursts::15 8 +system.mem_ctrls.perBankWrBursts::0 28 +system.mem_ctrls.perBankWrBursts::1 18 +system.mem_ctrls.perBankWrBursts::2 1 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 0 +system.mem_ctrls.perBankWrBursts::5 118 +system.mem_ctrls.perBankWrBursts::6 114 +system.mem_ctrls.perBankWrBursts::7 141 +system.mem_ctrls.perBankWrBursts::8 61 +system.mem_ctrls.perBankWrBursts::9 35 +system.mem_ctrls.perBankWrBursts::10 14 +system.mem_ctrls.perBankWrBursts::11 62 +system.mem_ctrls.perBankWrBursts::12 23 +system.mem_ctrls.perBankWrBursts::13 64 +system.mem_ctrls.perBankWrBursts::14 16 +system.mem_ctrls.perBankWrBursts::15 8 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 86680 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1289 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1285 +system.mem_ctrls.rdQLenPdf::0 700 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 +system.mem_ctrls.rdQLenPdf::26 0 +system.mem_ctrls.rdQLenPdf::27 0 +system.mem_ctrls.rdQLenPdf::28 0 +system.mem_ctrls.rdQLenPdf::29 0 +system.mem_ctrls.rdQLenPdf::30 0 +system.mem_ctrls.rdQLenPdf::31 0 +system.mem_ctrls.wrQLenPdf::0 1 +system.mem_ctrls.wrQLenPdf::1 1 +system.mem_ctrls.wrQLenPdf::2 1 +system.mem_ctrls.wrQLenPdf::3 1 +system.mem_ctrls.wrQLenPdf::4 1 +system.mem_ctrls.wrQLenPdf::5 1 +system.mem_ctrls.wrQLenPdf::6 1 +system.mem_ctrls.wrQLenPdf::7 1 +system.mem_ctrls.wrQLenPdf::8 1 +system.mem_ctrls.wrQLenPdf::9 1 +system.mem_ctrls.wrQLenPdf::10 1 +system.mem_ctrls.wrQLenPdf::11 1 +system.mem_ctrls.wrQLenPdf::12 1 +system.mem_ctrls.wrQLenPdf::13 1 +system.mem_ctrls.wrQLenPdf::14 1 +system.mem_ctrls.wrQLenPdf::15 3 +system.mem_ctrls.wrQLenPdf::16 3 +system.mem_ctrls.wrQLenPdf::17 35 +system.mem_ctrls.wrQLenPdf::18 45 +system.mem_ctrls.wrQLenPdf::19 45 +system.mem_ctrls.wrQLenPdf::20 49 +system.mem_ctrls.wrQLenPdf::21 49 +system.mem_ctrls.wrQLenPdf::22 46 +system.mem_ctrls.wrQLenPdf::23 44 +system.mem_ctrls.wrQLenPdf::24 44 +system.mem_ctrls.wrQLenPdf::25 44 +system.mem_ctrls.wrQLenPdf::26 44 +system.mem_ctrls.wrQLenPdf::27 44 +system.mem_ctrls.wrQLenPdf::28 44 +system.mem_ctrls.wrQLenPdf::29 44 +system.mem_ctrls.wrQLenPdf::30 44 +system.mem_ctrls.wrQLenPdf::31 44 +system.mem_ctrls.wrQLenPdf::32 44 +system.mem_ctrls.wrQLenPdf::33 0 +system.mem_ctrls.wrQLenPdf::34 0 +system.mem_ctrls.wrQLenPdf::35 0 +system.mem_ctrls.wrQLenPdf::36 0 +system.mem_ctrls.wrQLenPdf::37 0 +system.mem_ctrls.wrQLenPdf::38 0 +system.mem_ctrls.wrQLenPdf::39 0 +system.mem_ctrls.wrQLenPdf::40 0 +system.mem_ctrls.wrQLenPdf::41 0 +system.mem_ctrls.wrQLenPdf::42 0 +system.mem_ctrls.wrQLenPdf::43 0 +system.mem_ctrls.wrQLenPdf::44 0 +system.mem_ctrls.wrQLenPdf::45 0 +system.mem_ctrls.wrQLenPdf::46 0 +system.mem_ctrls.wrQLenPdf::47 0 +system.mem_ctrls.wrQLenPdf::48 0 +system.mem_ctrls.wrQLenPdf::49 0 +system.mem_ctrls.wrQLenPdf::50 0 +system.mem_ctrls.wrQLenPdf::51 0 +system.mem_ctrls.wrQLenPdf::52 0 +system.mem_ctrls.wrQLenPdf::53 0 +system.mem_ctrls.wrQLenPdf::54 0 +system.mem_ctrls.wrQLenPdf::55 0 +system.mem_ctrls.wrQLenPdf::56 0 +system.mem_ctrls.wrQLenPdf::57 0 +system.mem_ctrls.wrQLenPdf::58 0 +system.mem_ctrls.wrQLenPdf::59 0 +system.mem_ctrls.wrQLenPdf::60 0 +system.mem_ctrls.wrQLenPdf::61 0 +system.mem_ctrls.wrQLenPdf::62 0 +system.mem_ctrls.wrQLenPdf::63 0 +system.mem_ctrls.bytesPerActivate::samples 247 +system.mem_ctrls.bytesPerActivate::mean 359.384615 +system.mem_ctrls.bytesPerActivate::gmean 236.451062 +system.mem_ctrls.bytesPerActivate::stdev 319.751749 +system.mem_ctrls.bytesPerActivate::0-127 54 21.86% 21.86% +system.mem_ctrls.bytesPerActivate::128-255 65 26.32% 48.18% +system.mem_ctrls.bytesPerActivate::256-383 38 15.38% 63.56% +system.mem_ctrls.bytesPerActivate::384-511 27 10.93% 74.49% +system.mem_ctrls.bytesPerActivate::512-639 8 3.24% 77.73% +system.mem_ctrls.bytesPerActivate::640-767 10 4.05% 81.78% +system.mem_ctrls.bytesPerActivate::768-895 11 4.45% 86.23% +system.mem_ctrls.bytesPerActivate::896-1023 9 3.64% 89.88% +system.mem_ctrls.bytesPerActivate::1024-1151 25 10.12% 100.00% +system.mem_ctrls.bytesPerActivate::total 247 +system.mem_ctrls.rdPerTurnAround::samples 44 +system.mem_ctrls.rdPerTurnAround::mean 15.840909 +system.mem_ctrls.rdPerTurnAround::gmean 15.640724 +system.mem_ctrls.rdPerTurnAround::stdev 3.183849 +system.mem_ctrls.rdPerTurnAround::12-13 2 4.55% 4.55% +system.mem_ctrls.rdPerTurnAround::14-15 21 47.73% 52.27% +system.mem_ctrls.rdPerTurnAround::16-17 18 40.91% 93.18% +system.mem_ctrls.rdPerTurnAround::18-19 2 4.55% 97.73% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.27% 100.00% +system.mem_ctrls.rdPerTurnAround::total 44 +system.mem_ctrls.wrPerTurnAround::samples 44 +system.mem_ctrls.wrPerTurnAround::mean 16.159091 +system.mem_ctrls.wrPerTurnAround::gmean 16.147705 +system.mem_ctrls.wrPerTurnAround::stdev 0.644951 +system.mem_ctrls.wrPerTurnAround::16 41 93.18% 93.18% +system.mem_ctrls.wrPerTurnAround::17 1 2.27% 95.45% +system.mem_ctrls.wrPerTurnAround::19 2 4.55% 100.00% +system.mem_ctrls.wrPerTurnAround::total 44 +system.mem_ctrls.totQLat 12987 +system.mem_ctrls.totMemAccLat 26287 +system.mem_ctrls.totBusLat 3500 +system.mem_ctrls.avgQLat 18.55 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 37.55 +system.mem_ctrls.avgRdBW 516.45 +system.mem_ctrls.avgWrBW 524.57 +system.mem_ctrls.avgRdBWSys 951.01 +system.mem_ctrls.avgWrBWSys 948.06 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 8.13 +system.mem_ctrls.busUtilRead 4.03 +system.mem_ctrls.busUtilWrite 4.10 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.18 +system.mem_ctrls.readRowHits 508 +system.mem_ctrls.writeRowHits 652 +system.mem_ctrls.readRowHitRate 72.57 +system.mem_ctrls.writeRowHitRate 89.32 +system.mem_ctrls.avgGap 33.68 +system.mem_ctrls.pageHitRate 81.12 +system.mem_ctrls_0.actEnergy 1099560 +system.mem_ctrls_0.preEnergy 587328 +system.mem_ctrls_0.readEnergy 4969440 +system.mem_ctrls_0.writeEnergy 3574656 +system.mem_ctrls_0.refreshEnergy 6761040.000000 +system.mem_ctrls_0.actBackEnergy 10338432 +system.mem_ctrls_0.preBackEnergy 148224 +system.mem_ctrls_0.actPowerDownEnergy 27605784 +system.mem_ctrls_0.prePowerDownEnergy 1209216 +system.mem_ctrls_0.selfRefreshEnergy 0 +system.mem_ctrls_0.totalEnergy 56293680 +system.mem_ctrls_0.averagePower 648.948424 +system.mem_ctrls_0.totalIdleTime 63519 +system.mem_ctrls_0.memoryStateTime::IDLE 64 +system.mem_ctrls_0.memoryStateTime::REF 2860 +system.mem_ctrls_0.memoryStateTime::SREF 0 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 3149 +system.mem_ctrls_0.memoryStateTime::ACT 20134 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 60539 +system.mem_ctrls_1.actEnergy 692580 +system.mem_ctrls_1.preEnergy 367080 +system.mem_ctrls_1.readEnergy 3027360 +system.mem_ctrls_1.writeEnergy 2363616 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9621600 +system.mem_ctrls_1.preBackEnergy 296448 +system.mem_ctrls_1.actPowerDownEnergy 26302992 +system.mem_ctrls_1.prePowerDownEnergy 2761728 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 52194444 +system.mem_ctrls_1.averagePower 601.692804 +system.mem_ctrls_1.totalIdleTime 64843 +system.mem_ctrls_1.memoryStateTime::IDLE 422 +system.mem_ctrls_1.memoryStateTime::REF 2860 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 7192 +system.mem_ctrls_1.memoryStateTime::ACT 18590 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 57682 +system.pwrStateResidencyTicks::UNDEFINED 86746 +system.cpu.clk_domain.clock 1 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 86746 +system.cpu.numCycles 86746 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5327 +system.cpu.committedOps 5327 +system.cpu.num_int_alu_accesses 4505 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 146 +system.cpu.num_conditional_control_insts 773 +system.cpu.num_int_insts 4505 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 10598 +system.cpu.num_int_register_writes 4845 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_mem_refs 1401 +system.cpu.num_load_insts 723 +system.cpu.num_store_insts 678 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 86746 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1121 +system.cpu.op_class::No_OpClass 173 3.22% 3.22% +system.cpu.op_class::IntAlu 3796 70.69% 73.91% +system.cpu.op_class::IntMult 0 0.00% 73.91% +system.cpu.op_class::IntDiv 0 0.00% 73.91% +system.cpu.op_class::FloatAdd 0 0.00% 73.91% +system.cpu.op_class::FloatCmp 0 0.00% 73.91% +system.cpu.op_class::FloatCvt 0 0.00% 73.91% +system.cpu.op_class::FloatMult 0 0.00% 73.91% +system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::FloatDiv 0 0.00% 73.91% +system.cpu.op_class::FloatMisc 0 0.00% 73.91% +system.cpu.op_class::FloatSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdAdd 0 0.00% 73.91% +system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% +system.cpu.op_class::SimdAlu 0 0.00% 73.91% +system.cpu.op_class::SimdCmp 0 0.00% 73.91% +system.cpu.op_class::SimdCvt 0 0.00% 73.91% +system.cpu.op_class::SimdMisc 0 0.00% 73.91% +system.cpu.op_class::SimdMult 0 0.00% 73.91% +system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdShift 0 0.00% 73.91% +system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% +system.cpu.op_class::SimdSqrt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% +system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% +system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% +system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% +system.cpu.op_class::MemRead 723 13.46% 87.37% +system.cpu.op_class::MemWrite 678 12.63% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 5370 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2574 +system.ruby.delayHist | 2574 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2574 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 system.ruby.outstanding_req_hist_seqr::samples 6759 @@ -381,36 +381,36 @@ system.ruby.miss_latency_hist_seqr::stdev 35.397665 system.ruby.miss_latency_hist_seqr | 610 47.32% 47.32% | 633 49.11% 96.43% | 36 2.79% 99.22% | 1 0.08% 99.30% | 6 0.47% 99.77% | 2 0.16% 99.92% | 0 0.00% 99.92% | 1 0.08% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1289 system.ruby.Directory.incomplete_times_seqr 1288 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014813 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.995735 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029672 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.745697 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014859 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999205 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029672 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999216 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 5469 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1289 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 6758 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014813 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.969659 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.077916 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999988 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059345 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999931 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014859 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.993948 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 86746 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014813 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.974063 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014859 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.994882 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.088925 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.746619 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers0.percent_links_utilized 7.418209 system.ruby.network.routers0.msg_count.Control::2 1289 system.ruby.network.routers0.msg_count.Data::2 1285 @@ -420,13 +420,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 10312 system.ruby.network.routers0.msg_bytes.Data::2 92520 system.ruby.network.routers0.msg_bytes.Response_Data::4 92808 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029672 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.745928 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014813 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.991446 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014859 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998386 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers1.percent_links_utilized 7.418209 system.ruby.network.routers1.msg_count.Control::2 1289 system.ruby.network.routers1.msg_count.Data::2 1285 @@ -436,25 +436,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 10312 system.ruby.network.routers1.msg_bytes.Data::2 92520 system.ruby.network.routers1.msg_bytes.Response_Data::4 92808 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029672 +system.ruby.network.int_link_buffers02.avg_stall_time 7.746481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014813 +system.ruby.network.int_link_buffers08.avg_stall_time 2.987135 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014859 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997545 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014813 +system.ruby.network.int_link_buffers13.avg_stall_time 4.978443 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014859 +system.ruby.network.int_link_buffers14.avg_stall_time 4.995792 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029672 +system.ruby.network.int_link_buffers17.avg_stall_time 9.746135 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014813 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.982801 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014859 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996680 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029672 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.746320 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers2.percent_links_utilized 7.418209 system.ruby.network.routers2.msg_count.Control::2 1289 system.ruby.network.routers2.msg_count.Data::2 1285 @@ -464,7 +464,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 10312 system.ruby.network.routers2.msg_bytes.Data::2 92520 system.ruby.network.routers2.msg_bytes.Response_Data::4 92808 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10280 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.msg_count.Control 3867 system.ruby.network.msg_count.Data 3855 system.ruby.network.msg_count.Response_Data 3867 @@ -473,7 +473,7 @@ system.ruby.network.msg_byte.Control 30936 system.ruby.network.msg_byte.Data 277560 system.ruby.network.msg_byte.Response_Data 278424 system.ruby.network.msg_byte.Writeback_Control 30840 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 86746 system.ruby.network.routers0.throttle0.link_utilization 7.427432 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1289 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1285 @@ -504,16 +504,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1289 system.ruby.network.routers2.throttle1.msg_count.Data::2 1285 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 10312 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 92520 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1289 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1289 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1285 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1285 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1289 +system.ruby.delayVCHist.vnet_1 | 1289 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1289 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1285 +system.ruby.delayVCHist.vnet_2 | 1285 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1285 system.ruby.LD.latency_hist_seqr::bucket_size 64 system.ruby.LD.latency_hist_seqr::max_bucket 639 system.ruby.LD.latency_hist_seqr::samples 715 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 467bc0996..48a2ce7b0 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -85,6 +85,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -115,6 +116,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -127,15 +129,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=SparcTLB @@ -145,14 +148,14 @@ size=64 [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -166,6 +169,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -178,15 +182,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=SparcInterrupts @@ -204,14 +209,14 @@ size=64 [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -225,6 +230,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -237,15 +243,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -281,7 +288,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -290,14 +297,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/sparc/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -321,6 +329,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -332,7 +341,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -340,6 +349,13 @@ width=16 master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -348,6 +364,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -355,7 +372,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index a65457027..55314358f 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -3,11 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:30:06 -gem5 started Jul 21 2016 14:30:36 -gem5 executing on e108600-lin, pid 38670 -command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing +gem5 compiled Apr 3 2017 18:41:19 +gem5 started Apr 3 2017 18:41:41 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 64913 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 30526500 because target called exit() +Hello World!Exiting @ tick 30915500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 7d03d8b84..058393673 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,497 +1,497 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30915500 # Number of ticks simulated -final_tick 30915500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 536275 # Simulator instruction rate (inst/s) -host_op_rate 534981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3098223884 # Simulator tick rate (ticks/s) -host_mem_usage 250312 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 24896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 16320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 16320 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 527890540 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 277401304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 805291844 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 527890540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 527890540 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 527890540 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 277401304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 805291844 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 30915500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 61831 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5327 # Number of instructions committed -system.cpu.committedOps 5327 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4505 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 146 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 773 # number of instructions that are conditional controls -system.cpu.num_int_insts 4505 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 10598 # number of times the integer registers were read -system.cpu.num_int_register_writes 4845 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 1401 # number of memory refs -system.cpu.num_load_insts 723 # Number of load instructions -system.cpu.num_store_insts 678 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 61830.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1121 # Number of branches fetched -system.cpu.op_class::No_OpClass 173 3.22% 3.22% # Class of executed instruction -system.cpu.op_class::IntAlu 3796 70.69% 73.91% # Class of executed instruction -system.cpu.op_class::IntMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 73.91% # Class of executed instruction -system.cpu.op_class::MemRead 723 13.46% 87.37% # Class of executed instruction -system.cpu.op_class::MemWrite 678 12.63% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5370 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.942328 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.942328 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020005 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3353000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3353000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5103000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5103000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8456000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8456000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8456000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62092.592593 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62092.592593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62637.037037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62637.037037 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was 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cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8321000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8321000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8321000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8321000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for 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overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61637.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61637.037037 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 116.844047 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 116.844047 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057053 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057053 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.125488 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10999 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10999 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 5114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5114 # number of overall hits -system.cpu.icache.overall_hits::total 5114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses -system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16093500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16093500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16093500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16093500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16093500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16093500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5371 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5371 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5371 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047850 # miss rate for ReadReq accesses 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-system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15836500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15836500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15836500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15836500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15836500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15836500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses 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Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 197.305193 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.007712 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.297024 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.008169 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002472 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006021 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011871 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3525 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3525 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 255 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 255 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 53 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses 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ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992218 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.981481 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.981481 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.992347 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.960784 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.285347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.960784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.285347 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 255 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 255 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4090500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4090500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 12878000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 12878000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12878000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19645000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12878000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19645000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992218 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.981481 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.960784 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.960784 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.285347 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 392 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 257 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 54 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.007653 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.087258 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 389 99.23% 99.23% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3 0.77% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 389 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 30915500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1945000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.3 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 30915500 +final_tick 30915500 +sim_freq 1000000000000 +host_inst_rate 330902 +host_op_rate 330442 +host_tick_rate 1915496347 +host_mem_usage 261572 +host_seconds 0.02 +sim_insts 5327 +sim_ops 5327 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 30915500 +system.physmem.bytes_read::cpu.inst 16320 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 24896 +system.physmem.bytes_inst_read::cpu.inst 16320 +system.physmem.bytes_inst_read::total 16320 +system.physmem.num_reads::cpu.inst 255 +system.physmem.num_reads::cpu.data 134 +system.physmem.num_reads::total 389 +system.physmem.bw_read::cpu.inst 527890540 +system.physmem.bw_read::cpu.data 277401304 +system.physmem.bw_read::total 805291844 +system.physmem.bw_inst_read::cpu.inst 527890540 +system.physmem.bw_inst_read::total 527890540 +system.physmem.bw_total::cpu.inst 527890540 +system.physmem.bw_total::cpu.data 277401304 +system.physmem.bw_total::total 805291844 +system.pwrStateResidencyTicks::UNDEFINED 30915500 +system.cpu_clk_domain.clock 500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 30915500 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81.942328 +system.cpu.dcache.tags.occ_percent::cpu.data 0.020005 +system.cpu.dcache.tags.occ_percent::total 0.020005 +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 +system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 +system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 +system.cpu.dcache.tags.tag_accesses 2911 +system.cpu.dcache.tags.data_accesses 2911 +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 30915500 +system.cpu.dcache.ReadReq_hits::cpu.data 661 +system.cpu.dcache.ReadReq_hits::total 661 +system.cpu.dcache.WriteReq_hits::cpu.data 592 +system.cpu.dcache.WriteReq_hits::total 592 +system.cpu.dcache.demand_hits::cpu.data 1253 +system.cpu.dcache.demand_hits::total 1253 +system.cpu.dcache.overall_hits::cpu.data 1253 +system.cpu.dcache.overall_hits::total 1253 +system.cpu.dcache.ReadReq_misses::cpu.data 54 +system.cpu.dcache.ReadReq_misses::total 54 +system.cpu.dcache.WriteReq_misses::cpu.data 81 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+system.cpu.dcache.overall_avg_miss_latency::total 62637.037037 +system.cpu.dcache.blocked_cycles::no_mshrs 0 +system.cpu.dcache.blocked_cycles::no_targets 0 +system.cpu.dcache.blocked::no_mshrs 0 +system.cpu.dcache.blocked::no_targets 0 +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan +system.cpu.dcache.avg_blocked_cycles::no_targets nan +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 +system.cpu.dcache.ReadReq_mshr_misses::total 54 +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 +system.cpu.dcache.WriteReq_mshr_misses::total 81 +system.cpu.dcache.demand_mshr_misses::cpu.data 135 +system.cpu.dcache.demand_mshr_misses::total 135 +system.cpu.dcache.overall_mshr_misses::cpu.data 135 +system.cpu.dcache.overall_mshr_misses::total 135 +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3299000 +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3299000 +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5022000 +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5022000 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+system.membus.snoop_fanout::samples 389 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 389 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 389 +system.membus.reqLayer0.occupancy 389500 +system.membus.reqLayer0.utilization 1.3 +system.membus.respLayer1.occupancy 1945000 +system.membus.respLayer1.utilization 6.3 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 5809007c6..b5dc4aa3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -65,7 +66,7 @@ SSITSize=1024 activity=0 backComSize=5 branchPred=system.cpu.branchPred -cachePorts=200 +cacheStorePorts=200 checker=Null clk_domain=system.cpu_clk_domain commitToDecodeDelay=1 @@ -139,6 +140,7 @@ socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer trapLatency=13 @@ -764,7 +766,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -773,14 +775,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr index bbcd9d751..707fed98b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr @@ -1,3 +1,4 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 5ab7e4cb5..d96836b29 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 29 2016 18:55:59 -gem5 started Nov 29 2016 18:56:21 -gem5 executing on zizzer, pid 719 -command line: /z/powerjg/gem5-upstream/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87180 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 22466500 because target called exit() +Exiting @ tick 22516500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index a160b1441..f96155fcc 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,995 +1,995 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 22516500 # Number of ticks simulated -final_tick 22516500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69174 # Simulator instruction rate (inst/s) -host_op_rate 125309 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 289442861 # Simulator tick rate (ticks/s) -host_mem_usage 271352 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -sim_insts 5380 # Number of instructions simulated -sim_ops 9747 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 17728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17728 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory -system.physmem.num_reads::total 417 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 787333733 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 397930407 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1185264140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 787333733 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 787333733 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 397930407 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1185264140 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 417 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26688 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26688 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 31 # Per bank write bursts -system.physmem.perBankRdBursts::1 1 # Per bank write bursts -system.physmem.perBankRdBursts::2 5 # Per bank write bursts -system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 51 # Per bank write bursts -system.physmem.perBankRdBursts::5 44 # Per bank write bursts -system.physmem.perBankRdBursts::6 21 # Per bank write bursts -system.physmem.perBankRdBursts::7 36 # Per bank write bursts -system.physmem.perBankRdBursts::8 24 # Per bank write bursts -system.physmem.perBankRdBursts::9 71 # Per bank write bursts -system.physmem.perBankRdBursts::10 64 # Per bank write bursts -system.physmem.perBankRdBursts::11 16 # Per bank write bursts -system.physmem.perBankRdBursts::12 2 # Per bank write bursts -system.physmem.perBankRdBursts::13 20 # Per bank write bursts -system.physmem.perBankRdBursts::14 6 # Per bank write bursts -system.physmem.perBankRdBursts::15 17 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22387500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 417 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 239.673469 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 154.283411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.721287 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 41.84% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22 22.45% 64.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16 16.33% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 7.14% 87.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1 1.02% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 3.06% 91.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 2.04% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 2.04% 95.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4 4.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 6651000 # Total ticks spent queuing -system.physmem.totMemAccLat 14469750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15949.64 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34699.64 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1185.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1185.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.26 # Data bus utilization in percentage -system.physmem.busUtilRead 9.26 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.67 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 307 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 53687.05 # Average gap between requests -system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 307020 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140415 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1406580 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2488050 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 28320 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 7581570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 138720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 13319955 # Total energy per rank (pJ) -system.physmem_0.averagePower 591.537915 # Core power per rank (mW) -system.physmem_0.totalIdleTime 16888750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 17500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 0 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 361000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 4997500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 16620500 # Time in different power states -system.physmem_1.actEnergy 478380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 231495 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1570800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2961150 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 80160 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 7211640 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 13762905 # Total energy per rank (pJ) -system.physmem_1.averagePower 611.209282 # Core power per rank (mW) -system.physmem_1.totalIdleTime 15691750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 103000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 0 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6065500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 15828000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 3542 # Number of BP lookups -system.cpu.branchPred.condPredicted 3542 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 576 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 3006 # Number of BTB lookups -system.cpu.branchPred.BTBHits 0 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 386 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 97 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3006 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 514 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 2492 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 416 # Number of mispredicted indirect branches. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 22516500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 45034 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12047 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16169 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3542 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 900 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 10333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1321 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 74 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1582 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 15 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2077 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175931 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.701309 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20389 82.42% 82.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 178 0.72% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 168 0.68% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 246 0.99% 84.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 0.87% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 220 0.89% 86.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 262 1.06% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 167 0.68% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2892 11.69% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.078652 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.359040 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12032 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8141 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3437 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 467 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 660 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26977 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 660 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 12302 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1085 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3589 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4966 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 25351 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 77 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 4831 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 28444 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61768 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35524 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 17381 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 24 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1430 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2685 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22118 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18234 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 157 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12393 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17118 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24737 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.737114 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.712019 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19548 79.02% 79.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1204 4.87% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 865 3.50% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 579 2.34% 89.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 831 3.36% 93.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 615 2.49% 95.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 628 2.54% 98.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 340 1.37% 99.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127 0.51% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24737 # Number of insts issued each cycle -system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 218 79.85% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 79.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 40 14.65% 94.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 15 5.49% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14605 80.10% 80.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.03% 80.14% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2269 12.44% 92.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1341 7.35% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 4 0.02% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18234 # Type of FU issued -system.cpu.iq.rate 0.404894 # Inst issue rate -system.cpu.iq.fu_busy_cnt 273 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014972 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 61627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 34538 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16576 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 8 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18501 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 199 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1632 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 658 # Number of stores squashed -system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 660 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1518 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 153 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 22140 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 9 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2685 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 152 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 127 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 676 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 803 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17166 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2051 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1068 # Number of squashed instructions skipped in execute -system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3303 # number of memory reference insts executed -system.cpu.iew.exec_branches 1740 # Number of branches executed -system.cpu.iew.exec_stores 1252 # Number of stores executed -system.cpu.iew.exec_rate 0.381179 # Inst execution rate -system.cpu.iew.wb_sent 16892 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16580 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11141 # num instructions producing a value -system.cpu.iew.wb_consumers 17351 # num instructions consuming a value -system.cpu.iew.wb_rate 0.368166 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642096 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 12392 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 648 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22646 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.430407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.314219 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19391 85.63% 85.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1011 4.46% 90.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 560 2.47% 92.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 726 3.21% 95.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 383 1.69% 97.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 128 0.57% 98.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.52% 98.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.33% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 255 1.13% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22646 # Number of insts commited each cycle -system.cpu.commit.committedInsts 5380 # Number of instructions committed -system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed -system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 1988 # Number of memory references committed -system.cpu.commit.loads 1053 # Number of loads committed -system.cpu.commit.membars 0 # Number of memory barriers committed -system.cpu.commit.branches 1208 # Number of branches committed -system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 9653 # Number of committed integer instructions. -system.cpu.commit.function_calls 106 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 1 0.01% 0.01% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 7748 79.49% 79.50% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 3 0.03% 79.53% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 7 0.07% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 79.60% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 1053 10.80% 90.41% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 255 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 44530 # The number of ROB reads -system.cpu.rob.rob_writes 46401 # The number of ROB writes -system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20297 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5380 # Number of Instructions Simulated -system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.370632 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.370632 # CPI: Total CPI of All Threads -system.cpu.ipc 0.119465 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.119465 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21947 # number of integer regfile reads -system.cpu.int_regfile_writes 13377 # number of integer regfile writes -system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8355 # number of cc regfile reads -system.cpu.cc_regfile_writes 5130 # number of cc regfile writes -system.cpu.misc_regfile_reads 7644 # number of misc regfile reads -system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 81.908470 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2549 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 18.207143 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 81.908470 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019997 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5608 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5608 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 1687 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1687 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2549 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2549 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2549 # number of overall hits -system.cpu.dcache.overall_hits::total 2549 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 185 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 185 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 185 # number of overall misses -system.cpu.dcache.overall_misses::total 185 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9812000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9812000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6772000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6772000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16584000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16584000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16584000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2734 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2734 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2734 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2734 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062257 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078075 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067666 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067666 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067666 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067666 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87607.142857 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 87607.142857 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 92767.123288 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 92767.123288 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 89643.243243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 89643.243243 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 89643.243243 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 67 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 67 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6419000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6699000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13118000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13118000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.037243 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.078075 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051207 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051207 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95805.970149 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91767.123288 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 93700 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 93700 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 130.523512 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1695 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 278 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.097122 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 130.523512 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063732 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 278 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.135742 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4432 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 1695 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1695 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1695 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1695 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1695 # number of overall hits -system.cpu.icache.overall_hits::total 1695 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 382 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 382 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 382 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 382 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 382 # number of overall misses -system.cpu.icache.overall_misses::total 382 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30098500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30098500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30098500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30098500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30098500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2077 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2077 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2077 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2077 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2077 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183919 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183919 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183919 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183919 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183919 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 78791.884817 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 78791.884817 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 78791.884817 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 78791.884817 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 159 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 104 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 104 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 104 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 104 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 104 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 278 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 278 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 278 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23308500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23308500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23308500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23308500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133847 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133847 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133847 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.525180 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.525180 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.525180 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 212.529421 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002398 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.555666 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 81.973755 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003984 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002502 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012726 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3761 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3761 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 277 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 67 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 67 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 277 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 417 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 277 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses -system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6589500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 22879500 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6317500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 6317500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22879500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12907000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35786500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22879500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12907000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35786500 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 278 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 67 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 278 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 140 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 278 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 140 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996403 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996403 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997608 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996403 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82597.472924 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94291.044776 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82597.472924 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92192.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 85818.944844 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 277 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 67 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 277 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 417 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 277 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5859500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20109500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5647500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20109500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11507000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 31616500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20109500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11507000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 31616500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996403 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996403 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80267.123288 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72597.472924 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84291.044776 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72597.472924 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82192.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75818.944844 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 418 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 26752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002392 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 417000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 417 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 344 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 344 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 834 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 417 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2226500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.9 # Layer utilization (%) +sim_seconds 0.000023 +sim_ticks 22516500 +final_tick 22516500 +sim_freq 1000000000000 +host_inst_rate 26720 +host_op_rate 48405 +host_tick_rate 111808950 +host_mem_usage 281880 +host_seconds 0.20 +sim_insts 5380 +sim_ops 9747 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 22516500 +system.physmem.bytes_read::cpu.inst 17728 +system.physmem.bytes_read::cpu.data 8960 +system.physmem.bytes_read::total 26688 +system.physmem.bytes_inst_read::cpu.inst 17728 +system.physmem.bytes_inst_read::total 17728 +system.physmem.num_reads::cpu.inst 277 +system.physmem.num_reads::cpu.data 140 +system.physmem.num_reads::total 417 +system.physmem.bw_read::cpu.inst 787333733 +system.physmem.bw_read::cpu.data 397930407 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+system.cpu.toL2Bus.trans_dist::ReadResp 345 +system.cpu.toL2Bus.trans_dist::ReadExReq 73 +system.cpu.toL2Bus.trans_dist::ReadExResp 73 +system.cpu.toL2Bus.trans_dist::ReadCleanReq 278 +system.cpu.toL2Bus.trans_dist::ReadSharedReq 67 +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 556 +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 +system.cpu.toL2Bus.pkt_count::total 836 +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17792 +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8960 +system.cpu.toL2Bus.pkt_size::total 26752 +system.cpu.toL2Bus.snoops 0 +system.cpu.toL2Bus.snoopTraffic 0 +system.cpu.toL2Bus.snoop_fanout::samples 418 +system.cpu.toL2Bus.snoop_fanout::mean 0.002392 +system.cpu.toL2Bus.snoop_fanout::stdev 0.048912 +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% +system.cpu.toL2Bus.snoop_fanout::0 417 99.76% 99.76% +system.cpu.toL2Bus.snoop_fanout::1 1 0.24% 100.00% +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% +system.cpu.toL2Bus.snoop_fanout::min_value 0 +system.cpu.toL2Bus.snoop_fanout::max_value 1 +system.cpu.toL2Bus.snoop_fanout::total 418 +system.cpu.toL2Bus.reqLayer0.occupancy 209000 +system.cpu.toL2Bus.reqLayer0.utilization 0.9 +system.cpu.toL2Bus.respLayer0.occupancy 417000 +system.cpu.toL2Bus.respLayer0.utilization 1.9 +system.cpu.toL2Bus.respLayer1.occupancy 210000 +system.cpu.toL2Bus.respLayer1.utilization 0.9 +system.membus.snoop_filter.tot_requests 417 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 22516500 +system.membus.trans_dist::ReadResp 344 +system.membus.trans_dist::ReadExReq 73 +system.membus.trans_dist::ReadExResp 73 +system.membus.trans_dist::ReadSharedReq 344 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 834 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 834 +system.membus.pkt_count::total 834 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26688 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26688 +system.membus.pkt_size::total 26688 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 417 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 417 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 417 +system.membus.reqLayer0.occupancy 504000 +system.membus.reqLayer0.utilization 2.2 +system.membus.respLayer1.occupancy 2226500 +system.membus.respLayer1.utilization 9.9 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index 62043a3c5..8968a4ed6 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=atomic @@ -88,6 +89,7 @@ simulate_data_stalls=false simulate_inst_stalls=false socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer width=1 @@ -167,7 +169,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -176,14 +178,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -207,6 +210,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -218,7 +222,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -226,6 +230,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -234,6 +245,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -241,7 +253,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index bd2d6df6a..8dcc9cbbd 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:19 -gem5 executing on e108600-lin, pid 18561 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87156 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 5615000 because target called exit() +Exiting @ tick 5615000 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 54ef40828..2360c7c26 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 5615000 # Number of ticks simulated -final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340881 # Simulator instruction rate (inst/s) -host_op_rate 616836 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 354943212 # Simulator tick rate (ticks/s) -host_mem_usage 258192 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7066 # Number of bytes read from this memory -system.physmem.bytes_read::total 61978 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 54912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::cpu.data 7112 # Number of bytes written to this memory -system.physmem.bytes_written::total 7112 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1053 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7917 # Number of read requests responded to by this memory -system.physmem.num_writes::cpu.data 935 # Number of write requests responded to by this memory -system.physmem.num_writes::total 935 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 9779519145 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1258414960 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11037934105 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 9779519145 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1266607302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 5615000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 11231 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11230.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 7917 # Transaction distribution -system.membus.trans_dist::ReadResp 7917 # Transaction distribution -system.membus.trans_dist::WriteReq 935 # Transaction distribution -system.membus.trans_dist::WriteResp 935 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 8852 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 8852 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 8852 # Request fanout histogram +sim_seconds 0.000006 +sim_ticks 5615000 +final_tick 5615000 +sim_freq 1000000000000 +host_inst_rate 289662 +host_op_rate 524226 +host_tick_rate 301675446 +host_mem_usage 269844 +host_seconds 0.02 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 5615000 +system.physmem.bytes_read::cpu.inst 54912 +system.physmem.bytes_read::cpu.data 7066 +system.physmem.bytes_read::total 61978 +system.physmem.bytes_inst_read::cpu.inst 54912 +system.physmem.bytes_inst_read::total 54912 +system.physmem.bytes_written::cpu.data 7112 +system.physmem.bytes_written::total 7112 +system.physmem.num_reads::cpu.inst 6864 +system.physmem.num_reads::cpu.data 1053 +system.physmem.num_reads::total 7917 +system.physmem.num_writes::cpu.data 935 +system.physmem.num_writes::total 935 +system.physmem.bw_read::cpu.inst 9779519145 +system.physmem.bw_read::cpu.data 1258414960 +system.physmem.bw_read::total 11037934105 +system.physmem.bw_inst_read::cpu.inst 9779519145 +system.physmem.bw_inst_read::total 9779519145 +system.physmem.bw_write::cpu.data 1266607302 +system.physmem.bw_write::total 1266607302 +system.physmem.bw_total::cpu.inst 9779519145 +system.physmem.bw_total::cpu.data 2525022262 +system.physmem.bw_total::total 12304541407 +system.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5615000 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 5615000 +system.cpu.numCycles 11231 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 11231 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.membus.snoop_filter.tot_requests 0 +system.membus.snoop_filter.hit_single_requests 0 +system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 5615000 +system.membus.trans_dist::ReadReq 7917 +system.membus.trans_dist::ReadResp 7917 +system.membus.trans_dist::WriteReq 935 +system.membus.trans_dist::WriteResp 935 +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 +system.membus.pkt_count_system.cpu.icache_port::total 13728 +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 +system.membus.pkt_count_system.cpu.dcache_port::total 3976 +system.membus.pkt_count::total 17704 +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 +system.membus.pkt_size_system.cpu.icache_port::total 54912 +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 +system.membus.pkt_size_system.cpu.dcache_port::total 14178 +system.membus.pkt_size::total 69090 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 8852 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 8852 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 8852 ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 49adea038..155aa9c1d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -171,7 +173,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -180,14 +182,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -346,6 +349,7 @@ type=RubyDirectoryMemory eventq_index=0 numa_high_bit=5 size=268435456 +system=system version=0 [system.ruby.dir_cntrl0.dmaRequestToDir] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr index f6f6f15a5..95500d55b 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr @@ -7,4 +7,5 @@ warn: rounding error > tolerance warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 60c5b94b3..18eac1046 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 11 2016 00:00:58 -gem5 started Oct 13 2016 21:09:01 -gem5 executing on e108600-lin, pid 17636 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:22 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87199 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 91859 because target called exit() +Exiting @ tick 91859 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 843ed7643..f79527e54 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -1,369 +1,369 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000092 # Number of seconds simulated -sim_ticks 91859 # Number of ticks simulated -final_tick 91859 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 94122 # Simulator instruction rate (inst/s) -host_op_rate 170479 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1606243 # Simulator tick rate (ticks/s) -host_mem_usage 432368 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1 # Clock period in ticks -system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_read::total 88128 # Number of bytes read from this memory -system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 # Number of bytes written to this memory -system.mem_ctrls.bytes_written::total 87872 # Number of bytes written to this memory -system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_reads::total 1377 # Number of read requests responded to by this memory -system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 # Number of write requests responded to by this memory -system.mem_ctrls.num_writes::total 1373 # Number of write requests responded to by this memory -system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_read::total 959383403 # Total read bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_write::total 956596523 # Write bandwidth from this memory (bytes/s) -system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.bw_total::total 1915979926 # Total bandwidth to/from this memory (bytes/s) -system.mem_ctrls.readReqs 1377 # Number of read requests accepted -system.mem_ctrls.writeReqs 1373 # Number of write requests accepted -system.mem_ctrls.readBursts 1377 # Number of DRAM read bursts, including those serviced by the write queue -system.mem_ctrls.writeBursts 1373 # Number of DRAM write bursts, including those merged in the write queue -system.mem_ctrls.bytesReadDRAM 41408 # Total number of bytes read from DRAM -system.mem_ctrls.bytesReadWrQ 46720 # Total number of bytes read from write queue -system.mem_ctrls.bytesWritten 41728 # Total number of bytes written to DRAM -system.mem_ctrls.bytesReadSys 88128 # Total read bytes from the system interface side -system.mem_ctrls.bytesWrittenSys 87872 # Total written bytes from the system interface side -system.mem_ctrls.servicedByWrQ 730 # Number of DRAM read bursts serviced by the write queue -system.mem_ctrls.mergedWrBursts 702 # Number of DRAM write bursts merged with an existing one -system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.mem_ctrls.perBankRdBursts::0 60 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::3 10 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::4 51 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::5 53 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::6 39 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::7 57 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::9 129 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::10 115 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::13 28 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankRdBursts::15 35 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::0 55 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::1 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::2 6 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::3 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::4 52 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::5 48 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::6 38 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::7 60 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::8 28 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::9 130 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::10 123 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::11 24 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::12 2 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::13 31 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::14 8 # Per bank write bursts -system.mem_ctrls.perBankWrBursts::15 37 # Per bank write bursts -system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry -system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry -system.mem_ctrls.totGap 91773 # Total gap between requests -system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) -system.mem_ctrls.readPktSize::6 1377 # Read request sizes (log2) -system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) -system.mem_ctrls.writePktSize::6 1373 # Write request sizes (log2) -system.mem_ctrls.rdQLenPdf::0 647 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::15 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::16 6 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::17 33 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::18 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::19 42 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::20 43 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::21 44 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::22 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::23 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::24 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::25 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::26 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::27 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::28 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::29 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::30 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::31 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::32 40 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.mem_ctrls.bytesPerActivate::samples 263 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::mean 304.669202 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::gmean 201.653389 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::stdev 284.735596 # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::0-127 72 27.38% 27.38% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::128-255 68 25.86% 53.23% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::256-383 44 16.73% 69.96% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::384-511 29 11.03% 80.99% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::512-639 12 4.56% 85.55% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::640-767 9 3.42% 88.97% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% # Bytes accessed per row activation -system.mem_ctrls.bytesPerActivate::total 263 # Bytes accessed per row activation -system.mem_ctrls.rdPerTurnAround::samples 40 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::mean 16.100000 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::gmean 15.846587 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::stdev 3.484765 # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% # Reads before turning the bus around for writes -system.mem_ctrls.rdPerTurnAround::total 40 # Reads before turning the bus around for writes -system.mem_ctrls.wrPerTurnAround::samples 40 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::mean 16.300000 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::gmean 16.281263 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::stdev 0.822753 # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% # Writes before turning the bus around for reads -system.mem_ctrls.wrPerTurnAround::total 40 # Writes before turning the bus around for reads -system.mem_ctrls.totQLat 12721 # Total ticks spent queuing -system.mem_ctrls.totMemAccLat 25014 # Total ticks spent from burst creation until serviced by the DRAM -system.mem_ctrls.totBusLat 3235 # Total ticks spent in databus transfers -system.mem_ctrls.avgQLat 19.66 # Average queueing delay per DRAM burst -system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst -system.mem_ctrls.avgMemAccLat 38.66 # Average memory access latency per DRAM burst -system.mem_ctrls.avgRdBW 450.78 # Average DRAM read bandwidth in MiByte/s -system.mem_ctrls.avgWrBW 454.26 # Average achieved write bandwidth in MiByte/s -system.mem_ctrls.avgRdBWSys 959.38 # Average system read bandwidth in MiByte/s -system.mem_ctrls.avgWrBWSys 956.60 # Average system write bandwidth in MiByte/s -system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.mem_ctrls.busUtil 7.07 # Data bus utilization in percentage -system.mem_ctrls.busUtilRead 3.52 # Data bus utilization in percentage for reads -system.mem_ctrls.busUtilWrite 3.55 # Data bus utilization in percentage for writes -system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing -system.mem_ctrls.avgWrQLen 25.84 # Average write queue length when enqueuing -system.mem_ctrls.readRowHits 435 # Number of row buffer hits during reads -system.mem_ctrls.writeRowHits 591 # Number of row buffer hits during writes -system.mem_ctrls.readRowHitRate 67.23 # Row buffer hit rate for reads -system.mem_ctrls.writeRowHitRate 88.08 # Row buffer hit rate for writes -system.mem_ctrls.avgGap 33.37 # Average gap between requests -system.mem_ctrls.pageHitRate 77.85 # Row buffer hit rate, read and write combined -system.mem_ctrls_0.actEnergy 664020 # Energy for activate commands per rank (pJ) -system.mem_ctrls_0.preEnergy 340032 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_0.readEnergy 3175872 # Energy for read commands per rank (pJ) -system.mem_ctrls_0.writeEnergy 2246688 # Energy for write commands per rank (pJ) -system.mem_ctrls_0.refreshEnergy 7375680.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_0.actBackEnergy 10273224 # Energy for active background per rank (pJ) -system.mem_ctrls_0.preBackEnergy 269568 # Energy for precharge background per rank (pJ) -system.mem_ctrls_0.actPowerDownEnergy 25208136 # Energy for active power-down per rank (pJ) -system.mem_ctrls_0.prePowerDownEnergy 4818816 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_0.selfRefreshEnergy 743760.000000 # Energy for self refresh per rank (pJ) -system.mem_ctrls_0.totalEnergy 55115796 # Total energy per rank (pJ) -system.mem_ctrls_0.averagePower 600.004311 # Core power per rank (mW) -system.mem_ctrls_0.totalIdleTime 68393 # Total Idle time Per DRAM Rank -system.mem_ctrls_0.memoryStateTime::IDLE 346 # Time in different power states -system.mem_ctrls_0.memoryStateTime::REF 3126 # Time in different power states -system.mem_ctrls_0.memoryStateTime::SREF 798 # Time in different power states -system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT 19759 # Time in different power states -system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 # Time in different power states -system.mem_ctrls_1.actEnergy 1285200 # Energy for activate commands per rank (pJ) -system.mem_ctrls_1.preEnergy 676200 # Energy for precharge commands per rank (pJ) -system.mem_ctrls_1.readEnergy 4215456 # Energy for read commands per rank (pJ) -system.mem_ctrls_1.writeEnergy 3198816 # Energy for write commands per rank (pJ) -system.mem_ctrls_1.refreshEnergy 6761040.000000 # Energy for refresh commands per rank (pJ) -system.mem_ctrls_1.actBackEnergy 9576912 # Energy for active background per rank (pJ) -system.mem_ctrls_1.preBackEnergy 183552 # Energy for precharge background per rank (pJ) -system.mem_ctrls_1.actPowerDownEnergy 28147512 # Energy for active power-down per rank (pJ) -system.mem_ctrls_1.prePowerDownEnergy 3322368 # Energy for precharge power-down per rank (pJ) -system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) -system.mem_ctrls_1.totalEnergy 57367056 # Total energy per rank (pJ) -system.mem_ctrls_1.averagePower 624.512089 # Core power per rank (mW) -system.mem_ctrls_1.totalIdleTime 70328 # Total Idle time Per DRAM Rank -system.mem_ctrls_1.memoryStateTime::IDLE 150 # Time in different power states -system.mem_ctrls_1.memoryStateTime::REF 2866 # Time in different power states -system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states -system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT 18464 # Time in different power states -system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.clk_domain.clock 1 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 16 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 91859 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 91859 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.999989 # Number of idle cycles -system.cpu.num_busy_cycles 91858.000011 # Number of busy cycles -system.cpu.not_idle_fraction 0.999989 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000011 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.ruby.clk_domain.clock 1 # Clock period in ticks -system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.delayHist::bucket_size 1 # delay histogram for all message -system.ruby.delayHist::max_bucket 9 # delay histogram for all message -system.ruby.delayHist::samples 2750 # delay histogram for all message -system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 2750 # delay histogram for all message +sim_seconds 0.000092 +sim_ticks 91859 +final_tick 91859 +sim_freq 1000000000 +host_inst_rate 44912 +host_op_rate 81347 +host_tick_rate 766447 +host_mem_usage 444688 +host_seconds 0.12 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1 +system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 91859 +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 88128 +system.mem_ctrls.bytes_read::total 88128 +system.mem_ctrls.bytes_written::ruby.dir_cntrl0 87872 +system.mem_ctrls.bytes_written::total 87872 +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1377 +system.mem_ctrls.num_reads::total 1377 +system.mem_ctrls.num_writes::ruby.dir_cntrl0 1373 +system.mem_ctrls.num_writes::total 1373 +system.mem_ctrls.bw_read::ruby.dir_cntrl0 959383403 +system.mem_ctrls.bw_read::total 959383403 +system.mem_ctrls.bw_write::ruby.dir_cntrl0 956596523 +system.mem_ctrls.bw_write::total 956596523 +system.mem_ctrls.bw_total::ruby.dir_cntrl0 1915979926 +system.mem_ctrls.bw_total::total 1915979926 +system.mem_ctrls.readReqs 1377 +system.mem_ctrls.writeReqs 1373 +system.mem_ctrls.readBursts 1377 +system.mem_ctrls.writeBursts 1373 +system.mem_ctrls.bytesReadDRAM 41408 +system.mem_ctrls.bytesReadWrQ 46720 +system.mem_ctrls.bytesWritten 41728 +system.mem_ctrls.bytesReadSys 88128 +system.mem_ctrls.bytesWrittenSys 87872 +system.mem_ctrls.servicedByWrQ 730 +system.mem_ctrls.mergedWrBursts 702 +system.mem_ctrls.neitherReadNorWriteReqs 0 +system.mem_ctrls.perBankRdBursts::0 60 +system.mem_ctrls.perBankRdBursts::1 2 +system.mem_ctrls.perBankRdBursts::2 6 +system.mem_ctrls.perBankRdBursts::3 10 +system.mem_ctrls.perBankRdBursts::4 51 +system.mem_ctrls.perBankRdBursts::5 53 +system.mem_ctrls.perBankRdBursts::6 39 +system.mem_ctrls.perBankRdBursts::7 57 +system.mem_ctrls.perBankRdBursts::8 28 +system.mem_ctrls.perBankRdBursts::9 129 +system.mem_ctrls.perBankRdBursts::10 115 +system.mem_ctrls.perBankRdBursts::11 24 +system.mem_ctrls.perBankRdBursts::12 2 +system.mem_ctrls.perBankRdBursts::13 28 +system.mem_ctrls.perBankRdBursts::14 8 +system.mem_ctrls.perBankRdBursts::15 35 +system.mem_ctrls.perBankWrBursts::0 55 +system.mem_ctrls.perBankWrBursts::1 2 +system.mem_ctrls.perBankWrBursts::2 6 +system.mem_ctrls.perBankWrBursts::3 8 +system.mem_ctrls.perBankWrBursts::4 52 +system.mem_ctrls.perBankWrBursts::5 48 +system.mem_ctrls.perBankWrBursts::6 38 +system.mem_ctrls.perBankWrBursts::7 60 +system.mem_ctrls.perBankWrBursts::8 28 +system.mem_ctrls.perBankWrBursts::9 130 +system.mem_ctrls.perBankWrBursts::10 123 +system.mem_ctrls.perBankWrBursts::11 24 +system.mem_ctrls.perBankWrBursts::12 2 +system.mem_ctrls.perBankWrBursts::13 31 +system.mem_ctrls.perBankWrBursts::14 8 +system.mem_ctrls.perBankWrBursts::15 37 +system.mem_ctrls.numRdRetry 0 +system.mem_ctrls.numWrRetry 0 +system.mem_ctrls.totGap 91773 +system.mem_ctrls.readPktSize::0 0 +system.mem_ctrls.readPktSize::1 0 +system.mem_ctrls.readPktSize::2 0 +system.mem_ctrls.readPktSize::3 0 +system.mem_ctrls.readPktSize::4 0 +system.mem_ctrls.readPktSize::5 0 +system.mem_ctrls.readPktSize::6 1377 +system.mem_ctrls.writePktSize::0 0 +system.mem_ctrls.writePktSize::1 0 +system.mem_ctrls.writePktSize::2 0 +system.mem_ctrls.writePktSize::3 0 +system.mem_ctrls.writePktSize::4 0 +system.mem_ctrls.writePktSize::5 0 +system.mem_ctrls.writePktSize::6 1373 +system.mem_ctrls.rdQLenPdf::0 647 +system.mem_ctrls.rdQLenPdf::1 0 +system.mem_ctrls.rdQLenPdf::2 0 +system.mem_ctrls.rdQLenPdf::3 0 +system.mem_ctrls.rdQLenPdf::4 0 +system.mem_ctrls.rdQLenPdf::5 0 +system.mem_ctrls.rdQLenPdf::6 0 +system.mem_ctrls.rdQLenPdf::7 0 +system.mem_ctrls.rdQLenPdf::8 0 +system.mem_ctrls.rdQLenPdf::9 0 +system.mem_ctrls.rdQLenPdf::10 0 +system.mem_ctrls.rdQLenPdf::11 0 +system.mem_ctrls.rdQLenPdf::12 0 +system.mem_ctrls.rdQLenPdf::13 0 +system.mem_ctrls.rdQLenPdf::14 0 +system.mem_ctrls.rdQLenPdf::15 0 +system.mem_ctrls.rdQLenPdf::16 0 +system.mem_ctrls.rdQLenPdf::17 0 +system.mem_ctrls.rdQLenPdf::18 0 +system.mem_ctrls.rdQLenPdf::19 0 +system.mem_ctrls.rdQLenPdf::20 0 +system.mem_ctrls.rdQLenPdf::21 0 +system.mem_ctrls.rdQLenPdf::22 0 +system.mem_ctrls.rdQLenPdf::23 0 +system.mem_ctrls.rdQLenPdf::24 0 +system.mem_ctrls.rdQLenPdf::25 0 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+system.mem_ctrls.bytesPerActivate::768-895 6 2.28% 91.25% +system.mem_ctrls.bytesPerActivate::896-1023 3 1.14% 92.40% +system.mem_ctrls.bytesPerActivate::1024-1151 20 7.60% 100.00% +system.mem_ctrls.bytesPerActivate::total 263 +system.mem_ctrls.rdPerTurnAround::samples 40 +system.mem_ctrls.rdPerTurnAround::mean 16.100000 +system.mem_ctrls.rdPerTurnAround::gmean 15.846587 +system.mem_ctrls.rdPerTurnAround::stdev 3.484765 +system.mem_ctrls.rdPerTurnAround::12-13 3 7.50% 7.50% +system.mem_ctrls.rdPerTurnAround::14-15 12 30.00% 37.50% +system.mem_ctrls.rdPerTurnAround::16-17 19 47.50% 85.00% +system.mem_ctrls.rdPerTurnAround::18-19 4 10.00% 95.00% +system.mem_ctrls.rdPerTurnAround::20-21 1 2.50% 97.50% +system.mem_ctrls.rdPerTurnAround::34-35 1 2.50% 100.00% +system.mem_ctrls.rdPerTurnAround::total 40 +system.mem_ctrls.wrPerTurnAround::samples 40 +system.mem_ctrls.wrPerTurnAround::mean 16.300000 +system.mem_ctrls.wrPerTurnAround::gmean 16.281263 +system.mem_ctrls.wrPerTurnAround::stdev 0.822753 +system.mem_ctrls.wrPerTurnAround::16 35 87.50% 87.50% +system.mem_ctrls.wrPerTurnAround::18 3 7.50% 95.00% +system.mem_ctrls.wrPerTurnAround::19 2 5.00% 100.00% +system.mem_ctrls.wrPerTurnAround::total 40 +system.mem_ctrls.totQLat 12721 +system.mem_ctrls.totMemAccLat 25014 +system.mem_ctrls.totBusLat 3235 +system.mem_ctrls.avgQLat 19.66 +system.mem_ctrls.avgBusLat 5.00 +system.mem_ctrls.avgMemAccLat 38.66 +system.mem_ctrls.avgRdBW 450.78 +system.mem_ctrls.avgWrBW 454.26 +system.mem_ctrls.avgRdBWSys 959.38 +system.mem_ctrls.avgWrBWSys 956.60 +system.mem_ctrls.peakBW 12800.00 +system.mem_ctrls.busUtil 7.07 +system.mem_ctrls.busUtilRead 3.52 +system.mem_ctrls.busUtilWrite 3.55 +system.mem_ctrls.avgRdQLen 1.00 +system.mem_ctrls.avgWrQLen 25.84 +system.mem_ctrls.readRowHits 435 +system.mem_ctrls.writeRowHits 591 +system.mem_ctrls.readRowHitRate 67.23 +system.mem_ctrls.writeRowHitRate 88.08 +system.mem_ctrls.avgGap 33.37 +system.mem_ctrls.pageHitRate 77.85 +system.mem_ctrls_0.actEnergy 664020 +system.mem_ctrls_0.preEnergy 340032 +system.mem_ctrls_0.readEnergy 3175872 +system.mem_ctrls_0.writeEnergy 2246688 +system.mem_ctrls_0.refreshEnergy 7375680.000000 +system.mem_ctrls_0.actBackEnergy 10273224 +system.mem_ctrls_0.preBackEnergy 269568 +system.mem_ctrls_0.actPowerDownEnergy 25208136 +system.mem_ctrls_0.prePowerDownEnergy 4818816 +system.mem_ctrls_0.selfRefreshEnergy 743760.000000 +system.mem_ctrls_0.totalEnergy 55115796 +system.mem_ctrls_0.averagePower 600.004311 +system.mem_ctrls_0.totalIdleTime 68393 +system.mem_ctrls_0.memoryStateTime::IDLE 346 +system.mem_ctrls_0.memoryStateTime::REF 3126 +system.mem_ctrls_0.memoryStateTime::SREF 798 +system.mem_ctrls_0.memoryStateTime::PRE_PDN 12549 +system.mem_ctrls_0.memoryStateTime::ACT 19759 +system.mem_ctrls_0.memoryStateTime::ACT_PDN 55281 +system.mem_ctrls_1.actEnergy 1285200 +system.mem_ctrls_1.preEnergy 676200 +system.mem_ctrls_1.readEnergy 4215456 +system.mem_ctrls_1.writeEnergy 3198816 +system.mem_ctrls_1.refreshEnergy 6761040.000000 +system.mem_ctrls_1.actBackEnergy 9576912 +system.mem_ctrls_1.preBackEnergy 183552 +system.mem_ctrls_1.actPowerDownEnergy 28147512 +system.mem_ctrls_1.prePowerDownEnergy 3322368 +system.mem_ctrls_1.selfRefreshEnergy 0 +system.mem_ctrls_1.totalEnergy 57367056 +system.mem_ctrls_1.averagePower 624.512089 +system.mem_ctrls_1.totalIdleTime 70328 +system.mem_ctrls_1.memoryStateTime::IDLE 150 +system.mem_ctrls_1.memoryStateTime::REF 2866 +system.mem_ctrls_1.memoryStateTime::SREF 0 +system.mem_ctrls_1.memoryStateTime::PRE_PDN 8652 +system.mem_ctrls_1.memoryStateTime::ACT 18464 +system.mem_ctrls_1.memoryStateTime::ACT_PDN 61727 +system.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.clk_domain.clock 1 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.apic_clk_domain.clock 16 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 91859 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 91859 +system.cpu.numCycles 91859 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 91859 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% +system.cpu.op_class::MemRead 1053 10.80% 90.41% +system.cpu.op_class::MemWrite 935 9.59% 100.00% +system.cpu.op_class::FloatMemRead 0 0.00% 100.00% +system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% +system.cpu.op_class::IprAccess 0 0.00% 100.00% +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% +system.cpu.op_class::total 9748 +system.ruby.clk_domain.clock 1 +system.ruby.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.delayHist::bucket_size 1 +system.ruby.delayHist::max_bucket 9 +system.ruby.delayHist::samples 2750 +system.ruby.delayHist | 2750 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayHist::total 2750 system.ruby.outstanding_req_hist_seqr::bucket_size 1 system.ruby.outstanding_req_hist_seqr::max_bucket 9 -system.ruby.outstanding_req_hist_seqr::samples 8852 +system.ruby.outstanding_req_hist_seqr::samples 8853 system.ruby.outstanding_req_hist_seqr::mean 1 system.ruby.outstanding_req_hist_seqr::gmean 1 -system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8852 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist_seqr::total 8852 +system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 8853 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist_seqr::total 8853 system.ruby.latency_hist_seqr::bucket_size 64 system.ruby.latency_hist_seqr::max_bucket 639 system.ruby.latency_hist_seqr::samples 8852 @@ -388,36 +388,36 @@ system.ruby.miss_latency_hist_seqr::stdev 33.880423 system.ruby.miss_latency_hist_seqr | 751 54.54% 54.54% | 589 42.77% 97.31% | 26 1.89% 99.20% | 4 0.29% 99.49% | 3 0.22% 99.71% | 4 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% system.ruby.miss_latency_hist_seqr::total 1377 system.ruby.Directory.incomplete_times_seqr 1376 -system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 # Average number of cycles messages are stalled in this MB -system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 # Number of cache demand hits -system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 # Number of cache demand misses -system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 # Number of cache demand accesses -system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096364 # Average number of messages in buffer -system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 # Average number of messages in buffer -system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 # Average number of cycles messages are stalled in this MB -system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states -system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks -system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 # Average number of messages in buffer -system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.dir_cntrl0.forwardFromDir.avg_buf_msgs 0.014947 +system.ruby.dir_cntrl0.forwardFromDir.avg_stall_time 0.996691 +system.ruby.dir_cntrl0.requestToDir.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.requestToDir.avg_stall_time 11.743740 +system.ruby.dir_cntrl0.responseFromDir.avg_buf_msgs 0.014990 +system.ruby.dir_cntrl0.responseFromDir.avg_stall_time 0.999249 +system.ruby.dir_cntrl0.responseFromMemory.avg_buf_msgs 0.029937 +system.ruby.dir_cntrl0.responseFromMemory.avg_stall_time 0.999260 +system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.cacheMemory.demand_hits 7475 +system.ruby.l1_cntrl0.cacheMemory.demand_misses 1377 +system.ruby.l1_cntrl0.cacheMemory.demand_accesses 8852 +system.ruby.l1_cntrl0.forwardToCache.avg_buf_msgs 0.014947 +system.ruby.l1_cntrl0.forwardToCache.avg_stall_time 6.976377 +system.ruby.l1_cntrl0.mandatoryQueue.avg_buf_msgs 0.096375 +system.ruby.l1_cntrl0.mandatoryQueue.avg_stall_time 0.999989 +system.ruby.l1_cntrl0.requestFromCache.avg_buf_msgs 0.059874 +system.ruby.l1_cntrl0.requestFromCache.avg_stall_time 1.999935 +system.ruby.l1_cntrl0.responseToCache.avg_buf_msgs 0.014990 +system.ruby.l1_cntrl0.responseToCache.avg_stall_time 6.994285 +system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 91859 +system.ruby.memctrl_clk_domain.clock 3 +system.ruby.network.routers0.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers0.port_buffers03.avg_stall_time 5.979817 +system.ruby.network.routers0.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers0.port_buffers04.avg_stall_time 5.995167 +system.ruby.network.routers0.port_buffers07.avg_buf_msgs 0.089723 +system.ruby.network.routers0.port_buffers07.avg_stall_time 6.744611 +system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.percent_links_utilized 7.484297 system.ruby.network.routers0.msg_count.Control::2 1377 system.ruby.network.routers0.msg_count.Data::2 1373 @@ -427,13 +427,13 @@ system.ruby.network.routers0.msg_bytes.Control::2 11016 system.ruby.network.routers0.msg_bytes.Data::2 98856 system.ruby.network.routers0.msg_bytes.Response_Data::4 99144 system.ruby.network.routers0.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.routers1.port_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.routers1.port_buffers02.avg_stall_time 10.743958 +system.ruby.network.routers1.port_buffers06.avg_buf_msgs 0.014947 +system.ruby.network.routers1.port_buffers06.avg_stall_time 1.993359 +system.ruby.network.routers1.port_buffers07.avg_buf_msgs 0.014990 +system.ruby.network.routers1.port_buffers07.avg_stall_time 1.998476 +system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers1.percent_links_utilized 7.484297 system.ruby.network.routers1.msg_count.Control::2 1377 system.ruby.network.routers1.msg_count.Data::2 1373 @@ -443,25 +443,25 @@ system.ruby.network.routers1.msg_bytes.Control::2 11016 system.ruby.network.routers1.msg_bytes.Data::2 98856 system.ruby.network.routers1.msg_bytes.Response_Data::4 99144 system.ruby.network.routers1.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 # Average number of cycles messages are stalled in this MB -system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 # Average number of messages in buffer -system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 # Average number of cycles messages are stalled in this MB -system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.int_link_buffers02.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers02.avg_stall_time 7.744481 +system.ruby.network.int_link_buffers08.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers08.avg_stall_time 2.990007 +system.ruby.network.int_link_buffers09.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers09.avg_stall_time 2.997681 +system.ruby.network.int_link_buffers13.avg_buf_msgs 0.014947 +system.ruby.network.int_link_buffers13.avg_stall_time 4.983235 +system.ruby.network.int_link_buffers14.avg_buf_msgs 0.014990 +system.ruby.network.int_link_buffers14.avg_stall_time 4.996027 +system.ruby.network.int_link_buffers17.avg_buf_msgs 0.029937 +system.ruby.network.int_link_buffers17.avg_stall_time 9.744154 +system.ruby.network.routers2.port_buffers03.avg_buf_msgs 0.014947 +system.ruby.network.routers2.port_buffers03.avg_stall_time 3.986632 +system.ruby.network.routers2.port_buffers04.avg_buf_msgs 0.014990 +system.ruby.network.routers2.port_buffers04.avg_stall_time 3.996865 +system.ruby.network.routers2.port_buffers07.avg_buf_msgs 0.029937 +system.ruby.network.routers2.port_buffers07.avg_stall_time 8.744328 +system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers2.percent_links_utilized 7.484297 system.ruby.network.routers2.msg_count.Control::2 1377 system.ruby.network.routers2.msg_count.Data::2 1373 @@ -471,7 +471,7 @@ system.ruby.network.routers2.msg_bytes.Control::2 11016 system.ruby.network.routers2.msg_bytes.Data::2 98856 system.ruby.network.routers2.msg_bytes.Response_Data::4 99144 system.ruby.network.routers2.msg_bytes.Writeback_Control::3 10984 -system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.ruby.network.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.msg_count.Control 4131 system.ruby.network.msg_count.Data 4119 system.ruby.network.msg_count.Response_Data 4131 @@ -480,7 +480,7 @@ system.ruby.network.msg_byte.Control 33048 system.ruby.network.msg_byte.Data 296568 system.ruby.network.msg_byte.Response_Data 297432 system.ruby.network.msg_byte.Writeback_Control 32952 -system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 # Cumulative time (in ticks) in various power states +system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 91859 system.ruby.network.routers0.throttle0.link_utilization 7.493006 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1377 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1373 @@ -511,16 +511,16 @@ system.ruby.network.routers2.throttle1.msg_count.Control::2 1377 system.ruby.network.routers2.throttle1.msg_count.Data::2 1373 system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11016 system.ruby.network.routers2.throttle1.msg_bytes.Data::2 98856 -system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 1377 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 1373 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 1373 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_1::bucket_size 1 +system.ruby.delayVCHist.vnet_1::max_bucket 9 +system.ruby.delayVCHist.vnet_1::samples 1377 +system.ruby.delayVCHist.vnet_1 | 1377 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_1::total 1377 +system.ruby.delayVCHist.vnet_2::bucket_size 1 +system.ruby.delayVCHist.vnet_2::max_bucket 9 +system.ruby.delayVCHist.vnet_2::samples 1373 +system.ruby.delayVCHist.vnet_2 | 1373 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.delayVCHist.vnet_2::total 1373 system.ruby.LD.latency_hist_seqr::bucket_size 32 system.ruby.LD.latency_hist_seqr::max_bucket 319 system.ruby.LD.latency_hist_seqr::samples 1045 diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index bc04df7fd..1bbdae21e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -20,6 +20,7 @@ exit_on_work_items=false init_param=0 kernel= kernel_addr_check=true +kvm_vm=Null load_addr_mask=1099511627775 load_offset=0 mem_mode=timing @@ -85,6 +86,7 @@ progress_interval=0 simpoint_start_insts= socket_id=0 switched_out=false +syscallRetryLatency=10000 system=system tracer=system.cpu.tracer workload=system.cpu.workload @@ -100,14 +102,14 @@ eventq_index=0 [system.cpu.dcache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=false max_miss_count=0 mshrs=4 @@ -121,6 +123,7 @@ response_latency=2 sequential_access=false size=262144 system=system +tag_latency=2 tags=system.cpu.dcache.tags tgts_per_mshr=20 write_buffers=8 @@ -133,15 +136,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=262144 +tag_latency=2 [system.cpu.dtb] type=X86TLB @@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=2 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=2 is_read_only=true max_miss_count=0 mshrs=4 @@ -187,6 +191,7 @@ response_latency=2 sequential_access=false size=131072 system=system +tag_latency=2 tags=system.cpu.icache.tags tgts_per_mshr=20 write_buffers=8 @@ -199,15 +204,16 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=2 default_p_state=UNDEFINED eventq_index=0 -hit_latency=2 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=131072 +tag_latency=2 [system.cpu.interrupts] type=X86LocalApic @@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=Cache children=tags -addr_ranges=0:18446744073709551615 +addr_ranges=0:18446744073709551615:0:0:0:0 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +data_latency=20 default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 -hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 @@ -274,6 +280,7 @@ response_latency=20 sequential_access=false size=2097152 system=system +tag_latency=20 tags=system.cpu.l2cache.tags tgts_per_mshr=12 write_buffers=8 @@ -286,15 +293,16 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +data_latency=20 default_p_state=UNDEFINED eventq_index=0 -hit_latency=20 p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null sequential_access=false size=2097152 +tag_latency=20 [system.cpu.toL2Bus] type=CoherentXBar @@ -330,7 +338,7 @@ type=ExeTracer eventq_index=0 [system.cpu.workload] -type=LiveProcess +type=Process cmd=hello cwd= drivers= @@ -339,14 +347,15 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/x86/linux/hello +executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin kvmInSE=false -max_stack_size=67108864 +maxStackSize=67108864 output=cout +pgid=100 pid=100 -ppid=99 +ppid=0 simpoint=0 system=system uid=100 @@ -370,6 +379,7 @@ transition_latency=100000000 [system.membus] type=CoherentXBar +children=snoop_filter clk_domain=system.clk_domain default_p_state=UNDEFINED eventq_index=0 @@ -381,7 +391,7 @@ p_state_clk_gate_min=1000 point_of_coherency=true power_model=Null response_latency=2 -snoop_filter=Null +snoop_filter=system.membus.snoop_filter snoop_response_latency=4 system=system use_default_range=false @@ -389,6 +399,13 @@ width=16 master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master +[system.membus.snoop_filter] +type=SnoopFilter +eventq_index=0 +lookup_latency=1 +max_capacity=8388608 +system=system + [system.physmem] type=SimpleMemory bandwidth=73.000000 @@ -397,6 +414,7 @@ conf_table_reported=true default_p_state=UNDEFINED eventq_index=0 in_addr_map=true +kvm_map=true latency=30000 latency_var=0 null=false @@ -404,7 +422,7 @@ p_state_clk_gate_bins=20 p_state_clk_gate_max=1000000000000 p_state_clk_gate_min=1000 power_model=Null -range=0:134217727 +range=0:134217727:0:0:0:0 port=system.membus.master[0] [system.voltage_domain] diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr index aadc3d011..c0b55d123 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr @@ -1,2 +1,3 @@ warn: Sockets disabled, not accepting gdb connections warn: ClockedObject: More than one power state change request encountered within the same simulation tick +info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 17523a325..30d3fbf05 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -3,12 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 21 2016 14:35:23 -gem5 started Jul 21 2016 14:36:20 -gem5 executing on e108600-lin, pid 18567 -command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing +gem5 compiled Apr 3 2017 19:05:53 +gem5 started Apr 3 2017 19:06:21 +gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87155 +command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 30886500 because target called exit() +Exiting @ tick 31247500 because exiting with last active thread context diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b6ef5972c..e9a5f137e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,501 +1,501 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 31247500 # Number of ticks simulated -final_tick 31247500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377585 # Simulator instruction rate (inst/s) -host_op_rate 682900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2185869298 # Simulator tick rate (ticks/s) -host_mem_usage 268708 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 5381 # Number of instructions simulated -sim_ops 9748 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 23104 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 14528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 14528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 464933195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 274453956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 739387151 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 464933195 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 464933195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 274453956 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 739387151 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.workload.numSyscalls 11 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 31247500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 62495 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 5381 # Number of instructions committed -system.cpu.committedOps 9748 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 9654 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu.num_func_calls 209 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 899 # number of instructions that are conditional controls -system.cpu.num_int_insts 9654 # number of integer instructions -system.cpu.num_fp_insts 0 # number of float instructions -system.cpu.num_int_register_reads 18335 # number of times the integer registers were read -system.cpu.num_int_register_writes 7527 # number of times the integer registers were written -system.cpu.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 6487 # number of times the CC registers were read -system.cpu.num_cc_register_writes 3536 # number of times the CC registers were written -system.cpu.num_mem_refs 1988 # number of memory refs -system.cpu.num_load_insts 1053 # Number of load instructions -system.cpu.num_store_insts 935 # Number of store instructions -system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 62494.998000 # Number of busy cycles -system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1208 # Number of branches fetched -system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction -system.cpu.op_class::IntAlu 7749 79.49% 79.50% # Class of executed instruction -system.cpu.op_class::IntMult 3 0.03% 79.53% # Class of executed instruction -system.cpu.op_class::IntDiv 7 0.07% 79.61% # Class of executed instruction -system.cpu.op_class::FloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 79.61% # Class of executed instruction -system.cpu.op_class::MemRead 1053 10.80% 90.41% # Class of executed instruction -system.cpu.op_class::MemWrite 935 9.59% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 9748 # Class of executed instruction -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.527852 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.527852 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3465000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3465000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4977000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4977000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8442000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8442000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8442000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3410000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4898000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8308000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8308000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.231814 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.231814 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051383 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051383 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.111328 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13956 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13956 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 6636 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 6636 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 6636 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 6636 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 6636 # number of overall hits -system.cpu.icache.overall_hits::total 6636 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses -system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14315500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14315500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14315500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14315500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14315500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6864 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6864 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6864 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.033217 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62787.280702 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 62787.280702 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 62787.280702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 62787.280702 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 62787.280702 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14087500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14087500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14087500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14087500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14087500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61787.280702 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61787.280702 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61787.280702 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 185.792229 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 361 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002770 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.219349 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 80.572880 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003211 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002459 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005670 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011017 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3257 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3257 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 227 # number of ReadCleanReq misses -system.cpu.l2cache.ReadCleanReq_misses::total 227 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 55 # number of ReadSharedReq misses -system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4779500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadCleanReq_miss_latency::total 13734000 # number of ReadCleanReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.ReadSharedReq_miss_latency::total 3327500 # number of ReadSharedReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13734000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8107000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21841000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13734000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8107000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21841000 # number of overall miss cycles -system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 228 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 55 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995614 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997238 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60502.202643 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60502.202643 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 60501.385042 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 227 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 55 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3989500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11464000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11464000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2777500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6767000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18231000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6767000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18231000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995614 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50502.202643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50502.202643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.385042 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 362 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 79 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 228 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 55 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.002762 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.052559 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 361 99.72% 99.72% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1 0.28% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 361 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 282 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1805000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +sim_seconds 0.000031 +sim_ticks 31247500 +final_tick 31247500 +sim_freq 1000000000000 +host_inst_rate 194718 +host_op_rate 352470 +host_tick_rate 1129073998 +host_mem_usage 278812 +host_seconds 0.03 +sim_insts 5381 +sim_ops 9748 +system.voltage_domain.voltage 1 +system.clk_domain.clock 1000 +system.physmem.pwrStateResidencyTicks::UNDEFINED 31247500 +system.physmem.bytes_read::cpu.inst 14528 +system.physmem.bytes_read::cpu.data 8576 +system.physmem.bytes_read::total 23104 +system.physmem.bytes_inst_read::cpu.inst 14528 +system.physmem.bytes_inst_read::total 14528 +system.physmem.num_reads::cpu.inst 227 +system.physmem.num_reads::cpu.data 134 +system.physmem.num_reads::total 361 +system.physmem.bw_read::cpu.inst 464933195 +system.physmem.bw_read::cpu.data 274453956 +system.physmem.bw_read::total 739387151 +system.physmem.bw_inst_read::cpu.inst 464933195 +system.physmem.bw_inst_read::total 464933195 +system.physmem.bw_total::cpu.inst 464933195 +system.physmem.bw_total::cpu.data 274453956 +system.physmem.bw_total::total 739387151 +system.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu_clk_domain.clock 500 +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.apic_clk_domain.clock 8000 +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 31247500 +system.cpu.workload.numSyscalls 11 +system.cpu.pwrStateResidencyTicks::ON 31247500 +system.cpu.numCycles 62495 +system.cpu.numWorkItemsStarted 0 +system.cpu.numWorkItemsCompleted 0 +system.cpu.committedInsts 5381 +system.cpu.committedOps 9748 +system.cpu.num_int_alu_accesses 9654 +system.cpu.num_fp_alu_accesses 0 +system.cpu.num_func_calls 209 +system.cpu.num_conditional_control_insts 899 +system.cpu.num_int_insts 9654 +system.cpu.num_fp_insts 0 +system.cpu.num_int_register_reads 18335 +system.cpu.num_int_register_writes 7527 +system.cpu.num_fp_register_reads 0 +system.cpu.num_fp_register_writes 0 +system.cpu.num_cc_register_reads 6487 +system.cpu.num_cc_register_writes 3536 +system.cpu.num_mem_refs 1988 +system.cpu.num_load_insts 1053 +system.cpu.num_store_insts 935 +system.cpu.num_idle_cycles 0 +system.cpu.num_busy_cycles 62495 +system.cpu.not_idle_fraction 1 +system.cpu.idle_fraction 0 +system.cpu.Branches 1208 +system.cpu.op_class::No_OpClass 1 0.01% 0.01% +system.cpu.op_class::IntAlu 7749 79.49% 79.50% +system.cpu.op_class::IntMult 3 0.03% 79.53% +system.cpu.op_class::IntDiv 7 0.07% 79.61% +system.cpu.op_class::FloatAdd 0 0.00% 79.61% +system.cpu.op_class::FloatCmp 0 0.00% 79.61% +system.cpu.op_class::FloatCvt 0 0.00% 79.61% +system.cpu.op_class::FloatMult 0 0.00% 79.61% +system.cpu.op_class::FloatMultAcc 0 0.00% 79.61% +system.cpu.op_class::FloatDiv 0 0.00% 79.61% +system.cpu.op_class::FloatMisc 0 0.00% 79.61% +system.cpu.op_class::FloatSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdAdd 0 0.00% 79.61% +system.cpu.op_class::SimdAddAcc 0 0.00% 79.61% +system.cpu.op_class::SimdAlu 0 0.00% 79.61% +system.cpu.op_class::SimdCmp 0 0.00% 79.61% +system.cpu.op_class::SimdCvt 0 0.00% 79.61% +system.cpu.op_class::SimdMisc 0 0.00% 79.61% +system.cpu.op_class::SimdMult 0 0.00% 79.61% +system.cpu.op_class::SimdMultAcc 0 0.00% 79.61% +system.cpu.op_class::SimdShift 0 0.00% 79.61% +system.cpu.op_class::SimdShiftAcc 0 0.00% 79.61% +system.cpu.op_class::SimdSqrt 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAdd 0 0.00% 79.61% +system.cpu.op_class::SimdFloatAlu 0 0.00% 79.61% +system.cpu.op_class::SimdFloatCmp 0 0.00% 79.61% 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+system.membus.snoop_filter.hit_multi_requests 0 +system.membus.snoop_filter.tot_snoops 0 +system.membus.snoop_filter.hit_single_snoops 0 +system.membus.snoop_filter.hit_multi_snoops 0 +system.membus.pwrStateResidencyTicks::UNDEFINED 31247500 +system.membus.trans_dist::ReadResp 282 +system.membus.trans_dist::ReadExReq 79 +system.membus.trans_dist::ReadExResp 79 +system.membus.trans_dist::ReadSharedReq 282 +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 +system.membus.pkt_count::total 722 +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 +system.membus.pkt_size::total 23104 +system.membus.snoops 0 +system.membus.snoopTraffic 0 +system.membus.snoop_fanout::samples 361 +system.membus.snoop_fanout::mean 0 +system.membus.snoop_fanout::stdev 0 +system.membus.snoop_fanout::underflows 0 0.00% 0.00% +system.membus.snoop_fanout::0 361 100.00% 100.00% +system.membus.snoop_fanout::1 0 0.00% 100.00% +system.membus.snoop_fanout::overflows 0 0.00% 100.00% +system.membus.snoop_fanout::min_value 0 +system.membus.snoop_fanout::max_value 0 +system.membus.snoop_fanout::total 361 +system.membus.reqLayer0.occupancy 361500 +system.membus.reqLayer0.utilization 1.2 +system.membus.respLayer1.occupancy 1805000 +system.membus.respLayer1.utilization 5.8 ---------- End Simulation Statistics ---------- |