diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref')
43 files changed, 4845 insertions, 4663 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index f7aca5bc7..ab195624f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -62,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -92,22 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -148,6 +149,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -155,24 +159,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +186,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +204,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +226,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index da760535c..05dfd62f0 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:12 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21979500 because target called exit() +Exiting @ tick 18737000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 823f9b4c3..6769b3cad 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18769500 # Number of ticks simulated -final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18737000 # Number of ticks simulated +final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10228 # Simulator instruction rate (inst/s) -host_op_rate 10227 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 30039955 # Simulator tick rate (ticks/s) -host_mem_usage 216300 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host +host_inst_rate 37767 # Simulator instruction rate (inst/s) +host_op_rate 37763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 110721753 # Simulator tick rate (ticks/s) +host_mem_usage 213516 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1024710466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 573837861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1598548327 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1024710466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1024710466 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1024710466 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 573837861 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1598548327 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 18755000 # Total gap between requests +system.physmem.totGap 18722500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -165,26 +165,26 @@ system.physmem.wrQLenPdf::30 0 # Wh system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see system.physmem.totQLat 1862969 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests +system.physmem.totMemAccLat 11648969 # Sum of mem lat for all requests system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7924000 # Total cycles spent in bank access +system.physmem.totBankLat 7910000 # Total cycles spent in bank access system.physmem.avgQLat 3972.22 # Average queueing delay per request -system.physmem.avgBankLat 16895.52 # Average bank access latency per request +system.physmem.avgBankLat 16865.67 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24867.74 # Average memory access latency -system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24837.89 # Average memory access latency +system.physmem.avgRdBW 1598.55 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1598.55 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.97 # Data bus utilization in percentage +system.physmem.busUtil 9.99 # Data bus utilization in percentage system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 401 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 39989.34 # Average gap between requests +system.physmem.avgGap 39920.04 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -201,10 +201,10 @@ system.cpu.dtb.data_hits 2048 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2058 # DTB accesses -system.cpu.itb.fetch_hits 909 # ITB hits +system.cpu.itb.fetch_hits 915 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 926 # ITB accesses +system.cpu.itb.fetch_accesses 932 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 37540 # number of cpu cycles simulated +system.cpu.numCycles 37475 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1605 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits +system.cpu.branch_predictor.lookups 1632 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1160 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 706 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1266 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 352 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 27.804107 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9769 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2181 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4462 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 2948 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2152 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 4448 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11520 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7397 # Number of cycles cpu stages are processed. -system.cpu.activity 19.704315 # Percentage of cycles cpu is active +system.cpu.timesIdled 498 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30101 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7374 # Number of cycles cpu stages are processed. +system.cpu.activity 19.677118 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -265,72 +265,72 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 5.864632 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 5.864632 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170514 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.170514 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32551 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.139426 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33582 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 10.388259 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33313 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4162 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 11.106071 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36170 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.482322 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 32961 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4514 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 12.045364 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use -system.cpu.icache.total_refs 556 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.133594 # Cycle average of tags in use +system.cpu.icache.total_refs 561 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.863787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits -system.cpu.icache.overall_hits::total 556 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses -system.cpu.icache.overall_misses::total 353 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17380500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 909 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 909 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 909 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 909 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.388339 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.388339 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.388339 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.388339 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.388339 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.388339 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49236.543909 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49236.543909 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49236.543909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49236.543909 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.133594 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069889 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069889 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 561 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 561 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 561 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 561 # number of overall hits +system.cpu.icache.overall_hits::total 561 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 354 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 354 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 354 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 354 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 354 # number of overall misses +system.cpu.icache.overall_misses::total 354 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17402500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17402500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17402500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17402500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17402500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17402500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386885 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.386885 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.386885 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.386885 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.386885 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.386885 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49159.604520 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49159.604520 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49159.604520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49159.604520 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49159.604520 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -339,154 +339,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 48 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14765000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14765000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14765000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14765000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332233 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.332233 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.332233 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48890.728477 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48890.728477 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14751500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14751500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14751500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14751500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48846.026490 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48846.026490 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48846.026490 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48846.026490 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.285094 # Cycle average of tags in use -system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.285094 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025460 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025460 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits -system.cpu.dcache.overall_hits::total 1601 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses -system.cpu.dcache.overall_misses::total 447 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5354500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14914000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14914000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20268500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20268500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20268500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20268500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55201.030928 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55201.030928 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42611.428571 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42611.428571 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45343.400447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45343.400447 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3674000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8753000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8753000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8753000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53463.157895 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53463.157895 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50328.767123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50328.767123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 200.317780 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 200.167240 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.356757 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.961023 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004375 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.234891 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.932349 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004371 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006109 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -504,17 +398,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14446500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14446500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8574000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23020500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14446500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8574000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23020500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14433000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4976500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19409500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3596000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14433000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8572500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23005500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14433000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8572500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23005500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -537,17 +431,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49050.505051 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49267.123288 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49267.123288 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49084.221748 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47950.166113 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52384.210526 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49013.888889 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49260.273973 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49260.273973 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49052.238806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47950.166113 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51026.785714 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49052.238806 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,17 +461,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10648000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14440120 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10648000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17114216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10648000 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17114216 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -589,17 +483,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35375.415282 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36464.949495 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35375.415282 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36490.865672 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 104.225653 # Cycle average of tags in use +system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 104.225653 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025446 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits +system.cpu.dcache.overall_hits::total 1601 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses +system.cpu.dcache.overall_misses::total 447 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20267000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20267000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20267000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20267000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55190.721649 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55190.721649 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42610 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42610 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45340.044743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45340.044743 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45340.044743 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3673500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8751500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50321.917808 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50321.917808 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52092.261905 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52092.261905 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 6c764cc38..8465ac1d0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -455,24 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index a77141c3d..9cdc62046 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 16:51:51 -gem5 started Aug 13 2012 17:17:12 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12735500 because target called exit() +Exiting @ tick 15802500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index fb45a6f1f..56f807ea0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 15653000 # Number of ticks simulated -final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15802500 # Number of ticks simulated +final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 11804 # Simulator instruction rate (inst/s) -host_op_rate 11803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 28994780 # Simulator tick rate (ticks/s) -host_mem_usage 217308 # Number of bytes of host memory used -host_seconds 0.54 # Real time elapsed on the host +host_inst_rate 38730 # Simulator instruction rate (inst/s) +host_op_rate 38726 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96032767 # Simulator tick rate (ticks/s) +host_mem_usage 214332 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20032 # Nu system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 487 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady @@ -41,12 +41,12 @@ system.physmem.perBankRdReqs::1 18 # Tr system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15508000 # Total gap between requests +system.physmem.totGap 15655000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -99,9 +99,9 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2668987 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests +system.physmem.totQLat 3073487 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests system.physmem.totBusLat 1948000 # Total cycles spent in databus access system.physmem.totBankLat 7798000 # Total cycles spent in bank access -system.physmem.avgQLat 5480.47 # Average queueing delay per request +system.physmem.avgQLat 6311.06 # Average queueing delay per request system.physmem.avgBankLat 16012.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25492.79 # Average memory access latency -system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26323.38 # Average memory access latency +system.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.44 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.busUtil 12.33 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.81 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 417 # Number of row buffer hits during reads +system.physmem.readRowHits 416 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31843.94 # Average gap between requests +system.physmem.avgGap 32145.79 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2048 # DTB read hits -system.cpu.dtb.read_misses 58 # DTB read misses +system.cpu.dtb.read_hits 2068 # DTB read hits +system.cpu.dtb.read_misses 50 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2106 # DTB read accesses -system.cpu.dtb.write_hits 1074 # DTB write hits -system.cpu.dtb.write_misses 32 # DTB write misses +system.cpu.dtb.read_accesses 2118 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 29 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1106 # DTB write accesses -system.cpu.dtb.data_hits 3122 # DTB hits -system.cpu.dtb.data_misses 90 # DTB misses +system.cpu.dtb.write_accesses 1100 # DTB write accesses +system.cpu.dtb.data_hits 3139 # DTB hits +system.cpu.dtb.data_misses 79 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3212 # DTB accesses -system.cpu.itb.fetch_hits 2395 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3218 # DTB accesses +system.cpu.itb.fetch_hits 2370 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2433 # ITB accesses +system.cpu.itb.fetch_accesses 2409 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,243 +218,244 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 31307 # number of cpu cycles simulated +system.cpu.numCycles 31606 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2894 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits +system.cpu.BPredUnit.lookups 2927 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2370 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2779 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch +system.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2656 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2653 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 811 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10819 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10660 # Type of FU issued -system.cpu.iq.rate 0.340499 # Inst issue rate -system.cpu.iq.fu_busy_cnt 114 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10819 # Type of FU issued +system.cpu.iq.rate 0.342308 # Inst issue rate +system.cpu.iq.fu_busy_cnt 117 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 88 # number of nop insts executed -system.cpu.iew.exec_refs 3225 # number of memory reference insts executed -system.cpu.iew.exec_branches 1609 # Number of branches executed -system.cpu.iew.exec_stores 1108 # Number of stores executed -system.cpu.iew.exec_rate 0.319833 # Inst execution rate -system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9555 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5016 # num instructions producing a value -system.cpu.iew.wb_consumers 6802 # num instructions consuming a value +system.cpu.iew.exec_nop 87 # number of nop insts executed +system.cpu.iew.exec_refs 3231 # number of memory reference insts executed +system.cpu.iew.exec_branches 1614 # Number of branches executed +system.cpu.iew.exec_stores 1102 # Number of stores executed +system.cpu.iew.exec_rate 0.321679 # Inst execution rate +system.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9733 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5145 # num instructions producing a value +system.cpu.iew.wb_consumers 6933 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back +system.cpu.iew.wb_rate 0.307948 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -465,70 +466,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25734 # The number of ROB reads -system.cpu.rob.rob_writes 27303 # The number of ROB writes -system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25881 # The number of ROB reads +system.cpu.rob.rob_writes 27599 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads -system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12695 # number of integer regfile reads -system.cpu.int_regfile_writes 7186 # number of integer regfile writes +system.cpu.cpi 4.960138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads +system.cpu.ipc 0.201607 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12907 # number of integer regfile reads +system.cpu.int_regfile_writes 7365 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use -system.cpu.icache.total_refs 1916 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use +system.cpu.icache.total_refs 1894 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.377030 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078309 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078309 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1916 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1916 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1916 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1916 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1916 # number of overall hits -system.cpu.icache.overall_hits::total 1916 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses -system.cpu.icache.overall_misses::total 479 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21334000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21334000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21334000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21334000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21334000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2395 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2395 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2395 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2395 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2395 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.200000 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.200000 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.200000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44538.622129 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44538.622129 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44538.622129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44538.622129 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits +system.cpu.icache.overall_hits::total 1894 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses +system.cpu.icache.overall_misses::total 476 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -537,154 +538,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15306500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15306500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15306500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15306500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15306500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15306500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131106 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.131106 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.131106 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48746.815287 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48746.815287 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.831538 # Cycle average of tags in use -system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.831538 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026326 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026326 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits -system.cpu.dcache.overall_hits::total 2240 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 160 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 160 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 519 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 519 # number of overall misses -system.cpu.dcache.overall_misses::total 519 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8308500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8308500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15746484 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15746484 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24054984 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24054984 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24054984 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24054984 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084477 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.084477 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188112 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188112 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188112 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188112 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51928.125000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51928.125000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43862.072423 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43862.072423 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46348.716763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46348.716763 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 810 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.928571 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6029500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6029500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3803500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3803500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9833000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9833000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9833000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59698.019802 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59698.019802 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52102.739726 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52102.739726 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.955415 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.525117 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.430298 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004899 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 160.626019 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.276472 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004902 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001839 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006741 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -702,17 +597,17 @@ system.cpu.l2cache.demand_misses::total 487 # nu system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 487 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14981000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5921000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20902000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3727500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3727500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14981000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9648500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24629500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14981000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9648500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24629500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15078000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6210500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21288500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3737500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3737500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15078000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9948000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15078000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9948000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25026000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) @@ -735,17 +630,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997951 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47862.619808 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58623.762376 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50487.922705 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51061.643836 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51061.643836 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50573.921971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50573.921971 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48172.523962 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61490.099010 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51421.497585 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51198.630137 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51198.630137 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51388.090349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51388.090349 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -765,17 +660,17 @@ system.cpu.l2cache.demand_mshr_misses::total 487 system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11042494 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4678584 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15721078 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2834058 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2834058 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11042494 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7512642 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18555136 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11042494 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7512642 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18555136 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11136994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4966088 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16103082 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2842064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2842064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11136994 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7808152 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18945146 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11136994 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7808152 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18945146 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses @@ -787,17 +682,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35279.533546 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46322.613861 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37973.618357 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38822.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38822.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35581.450479 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49169.188119 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38896.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38932.383562 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38932.383562 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use +system.cpu.dcache.total_refs 2264 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits +system.cpu.dcache.overall_hits::total 2264 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses +system.cpu.dcache.overall_misses::total 528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 35d1c924c..4d782f4dd 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -455,24 +459,24 @@ size=48 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +486,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +504,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/alpha/tru64/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +526,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 07442c5d8..8f40149c5 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:08:29 -gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing +gem5 compiled Oct 30 2012 11:02:14 +gem5 started Oct 30 2012 11:20:24 +gem5 executing on u200540-lin +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7252000 because target called exit() +Exiting @ tick 9059000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 9eea9fb92..f9cbb8511 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000009 # Number of seconds simulated -sim_ticks 9061000 # Number of ticks simulated -final_tick 9061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 9059000 # Number of ticks simulated +final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62320 # Simulator instruction rate (inst/s) -host_op_rate 62299 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 236406021 # Simulator tick rate (ticks/s) -host_mem_usage 216020 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 28083 # Simulator instruction rate (inst/s) +host_op_rate 28078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 106544733 # Simulator tick rate (ticks/s) +host_mem_usage 213348 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1320825516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 600375235 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1921200750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1320825516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1320825516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1320825516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 600375235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1921200750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1321117121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 600507782 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1921624903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1321117121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1321117121 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1321117121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 600507782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1921624903 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady @@ -36,7 +36,7 @@ system.physmem.bytesConsumedRd 17408 # by system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 38 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 2 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 1 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 27 # Tr system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 16 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 8992500 # Total gap between requests +system.physmem.totGap 8990500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -100,8 +100,8 @@ system.physmem.neitherpktsize::7 0 # ca system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1105772 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 6813772 # Sum of mem lat for all requests +system.physmem.totQLat 1180771 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6930771 # Sum of mem lat for all requests system.physmem.totBusLat 1088000 # Total cycles spent in databus access -system.physmem.totBankLat 4620000 # Total cycles spent in bank access -system.physmem.avgQLat 4065.34 # Average queueing delay per request -system.physmem.avgBankLat 16985.29 # Average bank access latency per request +system.physmem.totBankLat 4662000 # Total cycles spent in bank access +system.physmem.avgQLat 4341.07 # Average queueing delay per request +system.physmem.avgBankLat 17139.71 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25050.63 # Average memory access latency -system.physmem.avgRdBW 1921.20 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25480.78 # Average memory access latency +system.physmem.avgRdBW 1921.62 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1921.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1921.62 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 12.01 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.75 # Average read queue length over time +system.physmem.avgRdQLen 0.77 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 228 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33060.66 # Average gap between requests +system.physmem.avgGap 33053.31 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 743 # DTB read hits -system.cpu.dtb.read_misses 38 # DTB read misses +system.cpu.dtb.read_hits 717 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 781 # DTB read accesses -system.cpu.dtb.write_hits 387 # DTB write hits -system.cpu.dtb.write_misses 24 # DTB write misses +system.cpu.dtb.read_accesses 742 # DTB read accesses +system.cpu.dtb.write_hits 359 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 411 # DTB write accesses -system.cpu.dtb.data_hits 1130 # DTB hits -system.cpu.dtb.data_misses 62 # DTB misses +system.cpu.dtb.write_accesses 378 # DTB write accesses +system.cpu.dtb.data_hits 1076 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1192 # DTB accesses -system.cpu.itb.fetch_hits 1097 # ITB hits +system.cpu.dtb.data_accesses 1120 # DTB accesses +system.cpu.itb.fetch_hits 1063 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1127 # ITB accesses +system.cpu.itb.fetch_accesses 1093 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,245 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 18123 # number of cpu cycles simulated +system.cpu.numCycles 18119 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1200 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 612 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 260 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 849 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 266 # Number of BTB hits +system.cpu.BPredUnit.lookups 1180 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 594 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 261 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 806 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 235 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 229 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 227 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4258 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7288 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1200 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 495 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1268 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 917 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 438 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 462 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1219 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 881 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 344 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 961 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 959 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1097 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.961604 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.365122 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 190 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961769 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.375037 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6311 83.27% 83.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 53 0.70% 83.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 134 1.77% 85.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 102 1.35% 87.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 181 2.39% 89.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 82 1.08% 90.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 68 0.90% 91.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 65 0.86% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 583 7.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6131 83.41% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 57 0.78% 84.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 120 1.63% 85.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 95 1.29% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.29% 89.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 0.99% 90.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 67 0.91% 91.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.87% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 575 7.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7579 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.066214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.402141 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5340 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 471 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1207 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 14 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 547 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 173 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6471 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7350 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065125 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.390143 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5296 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 369 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1168 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 510 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 170 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6269 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 547 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5441 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 165 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 510 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5398 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 91 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1119 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 57 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6174 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6979 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6967 # Number of integer rename lookups +system.cpu.rename.RunCycles 1075 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 26 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5981 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4351 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6729 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6717 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2706 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2583 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 508 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5283 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 121 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 979 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 463 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5055 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4254 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2663 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1563 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4086 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2501 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1445 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7579 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.561288 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.273203 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7350 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555918 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.264810 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5858 77.29% 77.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 621 8.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 415 5.48% 90.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.44% 94.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 216 2.85% 97.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 132 1.74% 99.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 51 0.67% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.13% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5719 77.81% 77.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 555 7.55% 85.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 404 5.50% 90.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.55% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 214 2.91% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 126 1.71% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 50 0.68% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.19% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7350 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.13% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.13% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 46.81% 48.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 24 51.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 6.82% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 43.18% 50.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 50.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2999 70.50% 70.50% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 829 19.49% 90.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 425 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2910 71.22% 71.22% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 789 19.31% 90.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 386 9.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4254 # Type of FU issued -system.cpu.iq.rate 0.234729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 47 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011048 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 16186 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7949 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3830 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4086 # Type of FU issued +system.cpu.iq.rate 0.225509 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010768 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15607 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7560 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3685 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4294 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4123 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 36 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 591 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 564 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 214 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 169 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 547 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5652 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 508 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 510 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 82 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5405 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 979 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 463 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 155 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 217 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4043 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 782 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 211 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 218 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3887 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 743 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 363 # number of nop insts executed -system.cpu.iew.exec_refs 1193 # number of memory reference insts executed -system.cpu.iew.exec_branches 672 # Number of branches executed -system.cpu.iew.exec_stores 411 # Number of stores executed -system.cpu.iew.exec_rate 0.223087 # Inst execution rate -system.cpu.iew.wb_sent 3934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3836 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1789 # num instructions producing a value -system.cpu.iew.wb_consumers 2358 # num instructions consuming a value +system.cpu.iew.exec_nop 344 # number of nop insts executed +system.cpu.iew.exec_refs 1121 # number of memory reference insts executed +system.cpu.iew.exec_branches 656 # Number of branches executed +system.cpu.iew.exec_stores 378 # Number of stores executed +system.cpu.iew.exec_rate 0.214526 # Inst execution rate +system.cpu.iew.wb_sent 3770 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3691 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1735 # num instructions producing a value +system.cpu.iew.wb_consumers 2218 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.211665 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.758694 # average fanout of values written-back +system.cpu.iew.wb_rate 0.203709 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.782236 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3067 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2808 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 182 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 7032 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.366325 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.202351 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 183 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.234221 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 6145 87.39% 87.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 219 3.11% 90.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 312 4.44% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.71% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 65 0.92% 97.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.80% 98.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.47% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 21 0.30% 99.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 0.87% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5975 87.35% 87.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 201 2.94% 90.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 309 4.52% 94.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.68% 96.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 68 0.99% 97.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 49 0.72% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23 0.34% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 7032 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -467,69 +467,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 12367 # The number of ROB reads -system.cpu.rob.rob_writes 11843 # The number of ROB writes +system.cpu.rob.rob_reads 11910 # The number of ROB reads +system.cpu.rob.rob_writes 11291 # The number of ROB writes system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 10769 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 7.592375 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.592375 # CPI: Total CPI of All Threads -system.cpu.ipc 0.131711 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.131711 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4904 # number of integer regfile reads -system.cpu.int_regfile_writes 2974 # number of integer regfile writes +system.cpu.cpi 7.590700 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.590700 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131740 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4685 # number of integer regfile reads +system.cpu.int_regfile_writes 2864 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.415859 # Cycle average of tags in use -system.cpu.icache.total_refs 849 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 92.986102 # Cycle average of tags in use +system.cpu.icache.total_refs 813 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.540107 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.347594 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.415859 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045125 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045125 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 849 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 849 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 849 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 849 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 849 # number of overall hits -system.cpu.icache.overall_hits::total 849 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses -system.cpu.icache.overall_misses::total 248 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11771499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11771499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11771499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11771499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11771499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11771499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1097 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1097 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1097 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1097 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1097 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.226071 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.226071 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.226071 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.226071 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.226071 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.226071 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47465.721774 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47465.721774 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47465.721774 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47465.721774 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 92.986102 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045403 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045403 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 813 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 813 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 813 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 813 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 813 # number of overall hits +system.cpu.icache.overall_hits::total 813 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11955999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11955999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11955999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11955999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11955999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11955999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1063 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1063 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1063 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1063 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235183 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.235183 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.235183 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.235183 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.235183 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.235183 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47823.996000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47823.996000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47823.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47823.996000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47823.996000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -538,154 +538,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 34 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9118999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9118999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9118999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9118999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9118999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9118999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170465 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.170465 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.170465 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48764.700535 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48764.700535 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9236999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9236999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9236999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9236999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175917 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175917 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175917 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175917 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49395.716578 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49395.716578 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49395.716578 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49395.716578 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.370052 # Cycle average of tags in use -system.cpu.dcache.total_refs 789 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.282353 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.370052 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011077 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011077 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 789 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 789 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 789 # number of overall hits -system.cpu.dcache.overall_hits::total 789 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204 # number of overall misses -system.cpu.dcache.overall_misses::total 204 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5446500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5446500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4115000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9561500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9561500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9561500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9561500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 699 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 699 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 993 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 993 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 993 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 993 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.175966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.205438 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.205438 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.205438 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.205438 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44280.487805 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 44280.487805 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50802.469136 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50802.469136 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46870.098039 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46870.098039 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.333333 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 119 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 119 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 119 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3349500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3349500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4698500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4698500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.087268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.087268 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.085599 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.085599 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54909.836066 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54909.836066 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56208.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56208.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 121.264296 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 121.901566 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 92.675015 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.589281 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002828 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000872 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003701 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 93.245260 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.656305 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002846 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000875 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003720 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses @@ -697,17 +591,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8931000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3288500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12219500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1323500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1323500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8931000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4612000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13543000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8931000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4612000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13543000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9049000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3265500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12314500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1324000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1324000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9049000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4589500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13638500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9049000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4589500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13638500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -730,17 +624,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47759.358289 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53909.836066 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49272.177419 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55145.833333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55145.833333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49790.441176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49790.441176 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48390.374332 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53532.786885 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49655.241935 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55166.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55166.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50141.544118 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48390.374332 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53994.117647 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50141.544118 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -760,17 +654,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6582780 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2536058 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9118838 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6701279 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2512062 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9213341 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1027024 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1027024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6582780 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3563082 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10145862 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6582780 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3563082 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10145862 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6701279 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3539086 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10240365 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6701279 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3539086 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10240365 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -782,17 +676,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35202.032086 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41574.721311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36769.508065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35835.716578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41181.344262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37150.568548 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35835.716578 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41636.305882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37648.400735 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 45.425217 # Cycle average of tags in use +system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 45.425217 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011090 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011090 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits +system.cpu.dcache.overall_hits::total 774 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 192 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 192 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 192 # number of overall misses +system.cpu.dcache.overall_misses::total 192 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5152500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5152500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4115500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9268000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9268000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9268000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9268000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 966 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 966 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 966 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 966 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.165179 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.198758 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.198758 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.198758 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.198758 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 46418.918919 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 46418.918919 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50808.641975 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50808.641975 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48270.833333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48270.833333 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48270.833333 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 23 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 107 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 107 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 107 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3326500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4676000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4676000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4676000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4676000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090774 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087992 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087992 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087992 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54532.786885 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54532.786885 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56229.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56229.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55011.764706 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55011.764706 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 6e3934424..6a6ed7d49 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -128,7 +128,7 @@ icache_port=system.cpu.icache.cpu_side type=O3Checker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true @@ -161,7 +161,7 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] @@ -174,7 +174,7 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] @@ -187,18 +187,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -217,7 +217,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -490,18 +490,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -523,7 +523,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -531,24 +531,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -558,10 +558,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port @@ -598,15 +598,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 425371c96..edb619587 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:20:03 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 1 2012 22:40:56 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10738000 because target called exit() +Exiting @ tick 13371000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ccb8279d9..0b4c661be 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13414500 # Number of ticks simulated -final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13371000 # Number of ticks simulated +final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 59216 # Simulator instruction rate (inst/s) -host_op_rate 73866 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172781643 # Simulator tick rate (ticks/s) -host_mem_usage 231444 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 32660 # Simulator instruction rate (inst/s) +host_op_rate 40743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94998008 # Simulator tick rate (ticks/s) +host_mem_usage 228356 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401 # Total number of read requests seen +system.physmem.num_reads::total 394 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25600 # Total number of bytes read from memory +system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25216 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13356500 # Total gap between requests +system.physmem.totGap 13312500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 401 # Categorize read packet sizes +system.physmem.readPktSize::6 394 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2497399 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests -system.physmem.totBusLat 1604000 # Total cycles spent in databus access -system.physmem.totBankLat 6636000 # Total cycles spent in bank access -system.physmem.avgQLat 6227.93 # Average queueing delay per request -system.physmem.avgBankLat 16548.63 # Average bank access latency per request +system.physmem.totQLat 2460894 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests +system.physmem.totBusLat 1576000 # Total cycles spent in databus access +system.physmem.totBankLat 6524000 # Total cycles spent in bank access +system.physmem.avgQLat 6245.92 # Average queueing delay per request +system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26776.56 # Average memory access latency -system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26804.30 # Average memory access latency +system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.93 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.busUtil 11.79 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 319 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33307.98 # Average gap between requests +system.physmem.avgGap 33788.07 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -273,245 +273,244 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26830 # number of cpu cycles simulated +system.cpu.numCycles 26743 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2508 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect +system.cpu.BPredUnit.lookups 2505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits +system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2440 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8896 # Type of FU issued -system.cpu.iq.rate 0.331569 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8988 # Type of FU issued +system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.fu_busy_cnt 228 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3284 # number of memory reference insts executed -system.cpu.iew.exec_branches 1437 # Number of branches executed -system.cpu.iew.exec_stores 1174 # Number of stores executed -system.cpu.iew.exec_rate 0.316996 # Inst execution rate -system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8071 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3897 # num instructions producing a value -system.cpu.iew.wb_consumers 7827 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed +system.cpu.iew.exec_branches 1446 # Number of branches executed +system.cpu.iew.exec_stores 1164 # Number of stores executed +system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8109 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3899 # num instructions producing a value +system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back +system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -522,69 +521,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23385 # The number of ROB reads -system.cpu.rob.rob_writes 23680 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22988 # The number of ROB reads +system.cpu.rob.rob_writes 23599 # The number of ROB writes +system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39120 # number of integer regfile reads -system.cpu.int_regfile_writes 7969 # number of integer regfile writes +system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39369 # number of integer regfile reads +system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15172 # number of misc regfile reads +system.cpu.misc_regfile_reads 15007 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use -system.cpu.icache.total_refs 1570 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits -system.cpu.icache.overall_hits::total 1570 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits +system.cpu.icache.overall_hits::total 1601 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -593,236 +592,236 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use -system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits -system.cpu.dcache.overall_hits::total 2324 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits +system.cpu.dcache.overall_hits::total 2371 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses -system.cpu.dcache.overall_misses::total 518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 41 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses +system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 399 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -831,56 +830,56 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index f5b7d940d..c182ad17a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -432,18 +433,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -457,6 +458,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -465,7 +483,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -473,24 +491,24 @@ port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -500,10 +518,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -540,15 +558,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index dc9a7546c..116fbeb57 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:07 +gem5 compiled Oct 30 2012 11:20:14 +gem5 started Oct 30 2012 18:52:17 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10738000 because target called exit() +Exiting @ tick 13371000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 62de1d1aa..76131bc35 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13414500 # Number of ticks simulated -final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13371000 # Number of ticks simulated +final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64991 # Simulator instruction rate (inst/s) -host_op_rate 81070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 189628588 # Simulator tick rate (ticks/s) -host_mem_usage 230428 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 37264 # Simulator instruction rate (inst/s) +host_op_rate 46486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108387516 # Simulator tick rate (ticks/s) +host_mem_usage 228452 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 400 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401 # Total number of read requests seen +system.physmem.num_reads::total 394 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25600 # Total number of bytes read from memory +system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25216 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 42 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 43 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13356500 # Total gap between requests +system.physmem.totGap 13312500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 401 # Categorize read packet sizes +system.physmem.readPktSize::6 394 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 197 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2497399 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests -system.physmem.totBusLat 1604000 # Total cycles spent in databus access -system.physmem.totBankLat 6636000 # Total cycles spent in bank access -system.physmem.avgQLat 6227.93 # Average queueing delay per request -system.physmem.avgBankLat 16548.63 # Average bank access latency per request +system.physmem.totQLat 2460894 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests +system.physmem.totBusLat 1576000 # Total cycles spent in databus access +system.physmem.totBankLat 6524000 # Total cycles spent in bank access +system.physmem.avgQLat 6245.92 # Average queueing delay per request +system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26776.56 # Average memory access latency -system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26804.30 # Average memory access latency +system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.93 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.busUtil 11.79 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 326 # Number of row buffer hits during reads +system.physmem.readRowHits 319 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33307.98 # Average gap between requests +system.physmem.avgGap 33788.07 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,245 +228,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26830 # number of cpu cycles simulated +system.cpu.numCycles 26743 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2508 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect +system.cpu.BPredUnit.lookups 2505 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits +system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2440 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2446 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2247 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 49 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5409 60.18% 60.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8896 # Type of FU issued -system.cpu.iq.rate 0.331569 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8988 # Type of FU issued +system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.fu_busy_cnt 228 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 647 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3284 # number of memory reference insts executed -system.cpu.iew.exec_branches 1437 # Number of branches executed -system.cpu.iew.exec_stores 1174 # Number of stores executed -system.cpu.iew.exec_rate 0.316996 # Inst execution rate -system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8071 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3897 # num instructions producing a value -system.cpu.iew.wb_consumers 7827 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3300 # number of memory reference insts executed +system.cpu.iew.exec_branches 1446 # Number of branches executed +system.cpu.iew.exec_stores 1164 # Number of stores executed +system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8109 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3899 # num instructions producing a value +system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back +system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9663 80.84% 80.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1075 8.99% 89.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.33% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 258 2.16% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.53% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 172 1.44% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.42% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 119 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -477,69 +476,69 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23385 # The number of ROB reads -system.cpu.rob.rob_writes 23680 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22988 # The number of ROB reads +system.cpu.rob.rob_writes 23599 # The number of ROB writes +system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39120 # number of integer regfile reads -system.cpu.int_regfile_writes 7969 # number of integer regfile writes +system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39369 # number of integer regfile reads +system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15172 # number of misc regfile reads +system.cpu.misc_regfile_reads 15007 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use -system.cpu.icache.total_refs 1570 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits -system.cpu.icache.overall_hits::total 1570 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses -system.cpu.icache.overall_misses::total 373 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits +system.cpu.icache.overall_hits::total 1601 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -548,294 +547,294 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 399 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.fast_writes 0 # number of fast writes performed +system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use -system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits -system.cpu.dcache.overall_hits::total 2324 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2371 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2371 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2371 # number of overall hits +system.cpu.dcache.overall_hits::total 2371 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses -system.cpu.dcache.overall_misses::total 518 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses +system.cpu.dcache.overall_misses::total 498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.097648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 351 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits -system.cpu.l2cache.overall_hits::total 41 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index 1ce31c334..bda1e98df 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -64,7 +64,7 @@ icache_port=system.membus.slave[1] type=DummyChecker children=dtb itb tracer checker=Null -clock=1 +clock=500 cpu_id=-1 defer_registration=false do_checkpoint_insts=true @@ -94,7 +94,7 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system @@ -106,7 +106,7 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system @@ -121,7 +121,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -137,7 +137,7 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -177,7 +177,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index 21ae26652..57c2a5d84 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:07 +gem5 compiled Nov 1 2012 15:18:10 +gem5 started Nov 1 2012 22:41:17 gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 592f491b0..147a664f0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92985 # Simulator instruction rate (inst/s) -host_op_rate 115998 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 58104040 # Simulator tick rate (ticks/s) -host_mem_usage 217212 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 135088 # Simulator instruction rate (inst/s) +host_op_rate 168502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 84394877 # Simulator tick rate (ticks/s) +host_mem_usage 218472 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index a81f3fb10..df7d00601 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -62,6 +62,7 @@ globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -92,22 +93,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +124,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -148,6 +149,11 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts +[system.cpu.isa] +type=MipsISA +num_threads=1 +num_vpes=1 + [system.cpu.itb] type=MipsTLB size=64 @@ -155,24 +161,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +188,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +206,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +228,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 893f17599..75053b5ab 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:00:38 -gem5 started Aug 13 2012 18:11:29 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:08:52 +gem5 started Oct 30 2012 13:57:29 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 20518000 because target called exit() +Exiting @ tick 18578000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 02dd2c613..5bb87ba63 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18578000 # Number of ticks simulated final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97793 # Simulator instruction rate (inst/s) -host_op_rate 97754 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 312246493 # Simulator tick rate (ticks/s) -host_mem_usage 216964 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 59954 # Simulator instruction rate (inst/s) +host_op_rate 59945 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 191522194 # Simulator tick rate (ticks/s) +host_mem_usage 214528 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2353954 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests +system.physmem.totQLat 2354454 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12658454 # Sum of mem lat for all requests system.physmem.totBusLat 1820000 # Total cycles spent in databus access system.physmem.totBankLat 8484000 # Total cycles spent in bank access -system.physmem.avgQLat 5173.53 # Average queueing delay per request +system.physmem.avgQLat 5174.62 # Average queueing delay per request system.physmem.avgBankLat 18646.15 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27819.68 # Average memory access latency +system.physmem.avgMemAccLat 27820.78 # Average memory access latency system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s @@ -207,34 +207,34 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 37157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1146 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 844 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 861 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 300 # Number of BTB hits +system.cpu.branch_predictor.lookups 1154 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 858 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 603 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 877 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 336 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.BTBHitPct 38.312429 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2235 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 319 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.136612 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3144 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2229 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 274 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 594 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 321 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 64.918033 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3135 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9462 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed @@ -257,66 +257,66 @@ system.cpu.cpi_total 6.390953 # CP system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 33508 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3649 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.820491 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34341 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2816 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.578653 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34392 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2765 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.441397 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34255 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2902 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.810103 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use -system.cpu.icache.total_refs 410 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 149.849185 # Cycle average of tags in use +system.cpu.icache.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits -system.cpu.icache.overall_hits::total 410 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 149.849185 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073169 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073169 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits +system.cpu.icache.overall_hits::total 428 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses system.cpu.icache.overall_misses::total 346 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 756 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 756 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.457672 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.457672 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.457672 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.457672 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.457672 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.457672 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52212.427746 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52212.427746 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52212.427746 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52212.427746 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18063500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18063500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18063500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18063500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18063500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18063500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 774 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 774 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.447028 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.447028 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52206.647399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52206.647399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52206.647399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52206.647399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52206.647399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -337,140 +337,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16466000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16466000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16466000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16466000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16466000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16466000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.421958 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.421958 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.421958 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51617.554859 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51617.554859 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16468000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51623.824451 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51623.824451 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51623.824451 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51623.824451 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.860913 # Cycle average of tags in use -system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.860913 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021939 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021939 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits -system.cpu.dcache.overall_hits::total 1644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses -system.cpu.dcache.overall_misses::total 444 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5589000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14658500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14658500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20247500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20247500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20247500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20247500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60096.774194 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60096.774194 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41762.108262 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41762.108262 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45602.477477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45602.477477 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7773500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7773500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7773500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59252.873563 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59252.873563 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 207.484772 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.598539 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.886233 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004626 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits @@ -490,17 +384,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16122500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5062000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21184500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16120500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7626000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23746500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16120500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7626000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23746500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16122500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7626500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23749000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16122500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7626500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23749000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -523,17 +417,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50859.621451 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58183.908046 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52436.881188 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52195.604396 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50859.621451 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55264.492754 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52195.604396 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,17 +447,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16099111 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12118017 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982594 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16100611 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12117017 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5911666 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18028683 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12117017 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12118017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5912166 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18030183 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12118017 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5912166 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18030183 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -575,17 +469,123 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38227.182965 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45776.942529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39852.997525 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38227.182965 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42841.782609 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39626.775824 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 89.859083 # Cycle average of tags in use +system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 89.859083 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021938 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits +system.cpu.dcache.overall_hits::total 1644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses +system.cpu.dcache.overall_misses::total 444 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5589500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14659500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14659500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20249000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20249000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20249000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20249000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60102.150538 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60102.150538 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41764.957265 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41764.957265 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45605.855856 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45605.855856 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7774000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7774000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7774000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59258.620690 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59258.620690 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56333.333333 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56333.333333 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 453ce4d95..6eeed9c1d 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -423,18 +424,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -448,6 +449,11 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=MipsInterrupts +[system.cpu.isa] +type=MipsISA +num_threads=1 +num_vpes=1 + [system.cpu.itb] type=MipsTLB size=64 @@ -455,24 +461,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -482,10 +488,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -500,7 +506,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/mips/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,15 +528,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 56b18a79d..5f05c3882 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:00:38 -gem5 started Aug 13 2012 18:11:40 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:08:52 +gem5 started Oct 30 2012 13:57:41 +gem5 executing on u200540-lin command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12925500 because target called exit() +Exiting @ tick 16532500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7222464d9..d0a749f15 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16437500 # Number of ticks simulated -final_tick 16437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 16532500 # Number of ticks simulated +final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79981 # Simulator instruction rate (inst/s) -host_op_rate 79951 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 254800448 # Simulator tick rate (ticks/s) -host_mem_usage 217976 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 48770 # Simulator instruction rate (inst/s) +host_op_rate 48763 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 156337427 # Simulator tick rate (ticks/s) +host_mem_usage 215260 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory -system.physmem.bytes_read::total 30720 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory -system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1319908745 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 548988593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1868897338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1319908745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1319908745 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1319908745 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 548988593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1868897338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 480 # Total number of read requests seen +system.physmem.num_reads::total 476 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 476 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30720 # Total number of bytes read from memory +system.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30464 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -41,7 +41,7 @@ system.physmem.perBankRdReqs::1 30 # Tr system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis @@ -49,9 +49,9 @@ system.physmem.perBankRdReqs::9 18 # Tr system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16357500 # Total gap between requests +system.physmem.totGap 16452500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 480 # Categorize read packet sizes +system.physmem.readPktSize::6 476 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2266480 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12950480 # Sum of mem lat for all requests -system.physmem.totBusLat 1920000 # Total cycles spent in databus access -system.physmem.totBankLat 8764000 # Total cycles spent in bank access -system.physmem.avgQLat 4721.83 # Average queueing delay per request -system.physmem.avgBankLat 18258.33 # Average bank access latency per request +system.physmem.totQLat 2527972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests +system.physmem.totBusLat 1904000 # Total cycles spent in databus access +system.physmem.totBankLat 8652000 # Total cycles spent in bank access +system.physmem.avgQLat 5310.87 # Average queueing delay per request +system.physmem.avgBankLat 18176.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26980.17 # Average memory access latency -system.physmem.avgRdBW 1868.90 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27487.34 # Average memory access latency +system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1868.90 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.busUtil 11.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 378 # Number of row buffer hits during reads +system.physmem.readRowHits 376 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.75 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34078.12 # Average gap between requests +system.physmem.avgGap 34564.08 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,243 +204,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 32876 # number of cpu cycles simulated +system.cpu.numCycles 33066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2145 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1420 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 444 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1692 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 498 # Number of BTB hits +system.cpu.BPredUnit.lookups 2120 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1453 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1651 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 517 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8858 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13016 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2145 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 768 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3241 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 897 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2015 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.926867 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.227706 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10802 76.92% 76.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1358 9.67% 86.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113 0.80% 87.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 147 1.05% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.17% 90.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 111 0.79% 91.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 157 1.12% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 126 0.90% 93.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 924 6.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065245 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.395912 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8962 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1117 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3062 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 858 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction +system.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3037 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 858 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9149 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking +system.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2921 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11564 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 95 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13727 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13723 # Number of integer rename lookups +system.cpu.rename.RunCycles 2904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3628 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 17 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 273 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 265 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9022 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3390 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8209 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14043 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.584063 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.245002 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10483 74.65% 74.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1421 10.12% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 877 6.25% 91.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 557 3.97% 94.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 353 2.51% 97.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 225 1.60% 99.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 84 0.60% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.96% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.40% 65.36% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 53 34.64% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4842 59.03% 59.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.10% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2249 27.42% 86.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1102 13.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8202 # Type of FU issued -system.cpu.iq.rate 0.249483 # Inst issue rate -system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018654 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30641 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12433 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7364 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8209 # Type of FU issued +system.cpu.iq.rate 0.248261 # Inst issue rate +system.cpu.iq.fu_busy_cnt 161 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8353 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1275 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 858 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 190 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10500 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 363 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 471 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7830 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2115 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 372 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1465 # number of nop insts executed -system.cpu.iew.exec_refs 3191 # number of memory reference insts executed -system.cpu.iew.exec_branches 1342 # Number of branches executed -system.cpu.iew.exec_stores 1076 # Number of stores executed -system.cpu.iew.exec_rate 0.238168 # Inst execution rate -system.cpu.iew.wb_sent 7455 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7366 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2870 # num instructions producing a value -system.cpu.iew.wb_consumers 4099 # num instructions consuming a value +system.cpu.iew.exec_nop 1512 # number of nop insts executed +system.cpu.iew.exec_refs 3196 # number of memory reference insts executed +system.cpu.iew.exec_branches 1341 # Number of branches executed +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.237374 # Inst execution rate +system.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7404 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2925 # num instructions producing a value +system.cpu.iew.wb_consumers 4228 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.224054 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.700171 # average fanout of values written-back +system.cpu.iew.wb_rate 0.223916 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4679 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 399 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13185 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.440880 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.228954 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10802 81.93% 81.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 977 7.41% 89.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 629 4.77% 94.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 318 2.41% 96.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 150 1.14% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 86 0.65% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 74 0.56% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.32% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13185 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,286 +452,180 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23557 # The number of ROB reads -system.cpu.rob.rob_writes 21850 # The number of ROB writes +system.cpu.rob.rob_reads 23666 # The number of ROB reads +system.cpu.rob.rob_writes 22238 # The number of ROB writes system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18833 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 6.376261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.376261 # CPI: Total CPI of All Threads -system.cpu.ipc 0.156832 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.156832 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10643 # number of integer regfile reads -system.cpu.int_regfile_writes 5150 # number of integer regfile writes +system.cpu.cpi 6.413111 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads +system.cpu.ipc 0.155931 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10670 # number of integer regfile reads +system.cpu.int_regfile_writes 5185 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 154 # number of misc regfile reads +system.cpu.misc_regfile_reads 147 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 164.359097 # Cycle average of tags in use -system.cpu.icache.total_refs 1560 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.561404 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use +system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 164.359097 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080253 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080253 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1560 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1560 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1560 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1560 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1560 # number of overall hits -system.cpu.icache.overall_hits::total 1560 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses -system.cpu.icache.overall_misses::total 455 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21541500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21541500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21541500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21541500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21541500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21541500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2015 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2015 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2015 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2015 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2015 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225806 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.225806 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.225806 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.225806 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.225806 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.225806 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47343.956044 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47343.956044 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47343.956044 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47343.956044 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits +system.cpu.icache.overall_hits::total 1502 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses +system.cpu.icache.overall_misses::total 446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17063000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17063000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17063000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17063000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17063000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17063000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.169727 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.169727 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.169727 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49891.812865 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49891.812865 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.173511 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.173511 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50161.242604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50161.242604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.458224 # Cycle average of tags in use -system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.148936 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.458224 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022329 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022329 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1846 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1846 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits -system.cpu.dcache.overall_hits::total 2418 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses -system.cpu.dcache.overall_misses::total 502 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8305500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8305500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15423499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15423499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23728999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23728999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23728999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23728999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2920 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2920 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2920 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2920 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074687 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.074687 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.171918 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.171918 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.171918 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.171918 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55741.610738 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55741.610738 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43692.631728 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43692.631728 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47268.922311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47268.922311 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 489 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.454545 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 361 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 361 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2754499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2754499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8174499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8174499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045113 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045113 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048288 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048288 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54009.784314 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54009.784314 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.543944 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 223.784369 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 166.808951 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.734994 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005091 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001762 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006853 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses +system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses -system.cpu.l2cache.overall_misses::total 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16691000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5327000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22018000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2702500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16691000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8029500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24720500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16691000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8029500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24720500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 476 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49235.988201 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59188.888889 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51324.009324 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52990.196078 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52990.196078 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51501.041667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51501.041667 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51849.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52980.392157 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52980.392157 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51970.588235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51970.588235 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,50 +634,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12421544 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4218076 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16639620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12421544 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6289130 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18710674 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12421544 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6289130 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18710674 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36641.722714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46867.511111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38786.993007 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use +system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2420 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2420 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2420 # number of overall hits +system.cpu.dcache.overall_hits::total 2420 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 151 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 151 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 504 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses +system.cpu.dcache.overall_misses::total 504 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2924 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2924 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2924 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2924 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075538 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075538 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.636364 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 7e4ac0c88..71523c506 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -79,6 +79,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -130,18 +131,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -424,18 +425,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -449,6 +450,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=PowerInterrupts +[system.cpu.isa] +type=PowerISA + [system.cpu.itb] type=PowerTLB size=64 @@ -456,24 +460,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -483,10 +487,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -501,7 +505,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/power/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -523,15 +527,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 4f1d93bdf..71a23fbd5 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:02:09 -gem5 started Aug 13 2012 18:12:24 -gem5 executing on zizzer +gem5 compiled Oct 30 2012 11:09:52 +gem5 started Oct 30 2012 13:58:22 +gem5 executing on u200540-lin command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11763500 because target called exit() +Exiting @ tick 14065500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 5e0f9ad46..b47dafade 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 14081500 # Number of ticks simulated -final_tick 14081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 14065500 # Number of ticks simulated +final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87308 # Simulator instruction rate (inst/s) -host_op_rate 87279 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 212126284 # Simulator tick rate (ticks/s) -host_mem_usage 214180 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 60799 # Simulator instruction rate (inst/s) +host_op_rate 60790 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 147601989 # Simulator tick rate (ticks/s) +host_mem_usage 210652 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 28992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 453 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1595284593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 463586976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2058871569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1595284593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1595284593 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1595284593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 463586976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2058871569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 453 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22080 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22080 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 345 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1569798443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 459564182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2029362625 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1569798443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1569798443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1569798443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 459564182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2029362625 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 446 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 453 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28992 # Total number of bytes read from memory +system.physmem.cpureqs 446 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28544 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28992 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28544 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -40,16 +40,16 @@ system.physmem.perBankRdReqs::0 64 # Tr system.physmem.perBankRdReqs::1 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 49 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 42 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 39 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 29 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 28 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13946000 # Total gap between requests +system.physmem.totGap 13957000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 453 # Categorize read packet sizes +system.physmem.readPktSize::6 446 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 236 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1940453 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11214453 # Sum of mem lat for all requests -system.physmem.totBusLat 1812000 # Total cycles spent in databus access -system.physmem.totBankLat 7462000 # Total cycles spent in bank access -system.physmem.avgQLat 4283.56 # Average queueing delay per request -system.physmem.avgBankLat 16472.41 # Average bank access latency per request +system.physmem.totQLat 1923444 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11085444 # Sum of mem lat for all requests +system.physmem.totBusLat 1784000 # Total cycles spent in databus access +system.physmem.totBankLat 7378000 # Total cycles spent in bank access +system.physmem.avgQLat 4312.65 # Average queueing delay per request +system.physmem.avgBankLat 16542.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24755.97 # Average memory access latency -system.physmem.avgRdBW 2058.87 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24855.26 # Average memory access latency +system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2058.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 12.87 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.80 # Average read queue length over time +system.physmem.busUtil 12.68 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 376 # Number of row buffer hits during reads +system.physmem.readRowHits 369 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.00 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 30785.87 # Average gap between requests +system.physmem.avgGap 31293.72 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,244 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 28164 # number of cpu cycles simulated +system.cpu.numCycles 28132 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2468 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2024 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2049 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits +system.cpu.BPredUnit.lookups 2247 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1810 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1863 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 602 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 159 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7429 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2468 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 783 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2394 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1429 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 964 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1877 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.222760 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.655950 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1812 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 306 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9372 79.65% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 173 1.47% 81.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 165 1.40% 82.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 142 1.21% 83.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 200 1.70% 85.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 147 1.25% 86.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 252 2.14% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.93% 89.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1206 10.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9396 80.56% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 175 1.50% 82.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 176 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.22% 84.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 227 1.95% 86.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.13% 87.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.20% 90.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 109 0.93% 91.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1049 8.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11766 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.087630 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.510829 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7522 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1142 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2216 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 806 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 353 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12752 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 806 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7732 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 454 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 444 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2079 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 251 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12099 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 210 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10388 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19762 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19707 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 11663 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.079873 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.469856 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7468 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1305 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2099 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 709 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 342 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 156 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11753 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 709 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7658 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 585 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 451 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1983 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 277 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11310 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 233 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 9699 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18197 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18142 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5390 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4701 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1942 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10942 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9281 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4902 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4209 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11766 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.788798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.528040 # Number of insts issued each cycle +system.cpu.rename.skidInsts 580 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 57 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8959 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 188 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4243 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3419 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11663 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.768156 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.499073 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8334 70.83% 70.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1092 9.28% 80.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.71% 86.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 514 4.37% 91.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 473 4.02% 95.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 331 2.81% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 146 1.24% 99.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 50 0.42% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 37 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8296 71.13% 71.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1090 9.35% 80.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 795 6.82% 87.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 496 4.25% 91.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.00% 95.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 308 2.64% 98.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 133 1.14% 99.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 43 0.37% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 36 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11766 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11663 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.26% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 77 43.50% 45.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 96 54.24% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 4.60% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 71 40.80% 45.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 95 54.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5705 61.47% 61.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.47% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.47% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1860 20.04% 81.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1714 18.47% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5501 61.40% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.40% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1805 20.15% 81.57% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1651 18.43% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9281 # Type of FU issued -system.cpu.iq.rate 0.329534 # Inst issue rate -system.cpu.iq.fu_busy_cnt 177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019071 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30620 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15880 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8398 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8959 # Type of FU issued +system.cpu.iq.rate 0.318463 # Inst issue rate +system.cpu.iq.fu_busy_cnt 174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019422 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29881 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14574 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8164 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9424 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9099 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 896 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 783 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 806 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 266 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11006 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1942 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 383 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8796 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 709 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 370 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10360 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 55 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 48 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 264 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 330 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8539 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1683 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 420 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3302 # number of memory reference insts executed -system.cpu.iew.exec_branches 1388 # Number of branches executed -system.cpu.iew.exec_stores 1577 # Number of stores executed -system.cpu.iew.exec_rate 0.312314 # Inst execution rate -system.cpu.iew.wb_sent 8586 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8425 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4372 # num instructions producing a value -system.cpu.iew.wb_consumers 7073 # num instructions consuming a value +system.cpu.iew.exec_refs 3224 # number of memory reference insts executed +system.cpu.iew.exec_branches 1354 # Number of branches executed +system.cpu.iew.exec_stores 1541 # Number of stores executed +system.cpu.iew.exec_rate 0.303533 # Inst execution rate +system.cpu.iew.wb_sent 8307 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8191 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4222 # num instructions producing a value +system.cpu.iew.wb_consumers 6683 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.299141 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.618125 # average fanout of values written-back +system.cpu.iew.wb_rate 0.291163 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.631752 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4574 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.528467 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.329717 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.330367 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8573 78.22% 78.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1014 9.25% 87.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 623 5.68% 93.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 252 2.30% 95.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 177 1.61% 97.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 1.00% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.58% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.38% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 105 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8576 78.29% 78.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1000 9.13% 87.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 620 5.66% 93.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 265 2.42% 95.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 172 1.57% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 106 0.97% 98.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 68 0.62% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.41% 99.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -452,285 +451,182 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21870 # The number of ROB reads -system.cpu.rob.rob_writes 22837 # The number of ROB writes -system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16398 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21218 # The number of ROB reads +system.cpu.rob.rob_writes 21442 # The number of ROB writes +system.cpu.timesIdled 246 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16469 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 4.862569 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.862569 # CPI: Total CPI of All Threads -system.cpu.ipc 0.205653 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.205653 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13961 # number of integer regfile reads -system.cpu.int_regfile_writes 7286 # number of integer regfile writes +system.cpu.cpi 4.857044 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.857044 # CPI: Total CPI of All Threads +system.cpu.ipc 0.205887 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.205887 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13537 # number of integer regfile reads +system.cpu.int_regfile_writes 7068 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 171.601938 # Cycle average of tags in use -system.cpu.icache.total_refs 1437 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.036517 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 168.326699 # Cycle average of tags in use +system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 171.601938 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.083790 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.083790 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1437 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1437 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1437 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1437 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1437 # number of overall hits -system.cpu.icache.overall_hits::total 1437 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 440 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 440 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 440 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 440 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 440 # number of overall misses -system.cpu.icache.overall_misses::total 440 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20404500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20404500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20404500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20404500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20404500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20404500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1877 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1877 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1877 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1877 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1877 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234417 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234417 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234417 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234417 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234417 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234417 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46373.863636 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46373.863636 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46373.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46373.863636 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 338 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 168.326699 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1375 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1375 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits +system.cpu.icache.overall_hits::total 1375 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20187000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20187000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20187000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20187000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20187000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20187000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1812 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1812 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1812 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1812 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1812 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241170 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241170 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241170 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241170 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241170 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241170 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46194.508009 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46194.508009 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46194.508009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46194.508009 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 56.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 52 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17051500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17051500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189664 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.189664 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.189664 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47897.471910 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47897.471910 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16769000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16769000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16769000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16769000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193709 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193709 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193709 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47774.928775 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47774.928775 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.108123 # Cycle average of tags in use -system.cpu.dcache.total_refs 2206 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.627451 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.108123 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015407 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015407 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1490 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1490 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 716 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 716 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits -system.cpu.dcache.overall_hits::total 2206 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 330 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 330 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 427 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 427 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 427 # number of overall misses -system.cpu.dcache.overall_misses::total 427 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4870000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4870000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14038497 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14038497 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18908497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18908497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18908497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18908497 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1587 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2633 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2633 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2633 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2633 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061122 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.061122 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315488 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.315488 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162172 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162172 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.162172 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.162172 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.185567 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.185567 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42540.900000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42540.900000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44282.194379 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44282.194379 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 416 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.200000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3072500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2817999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2817999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5890499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5890499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5890499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5890499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034657 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034657 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038739 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038739 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55863.636364 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55863.636364 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59957.425532 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59957.425532 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 202.387362 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 406 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012315 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 198.645490 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 170.963901 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.423461 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005217 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006176 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits -system.cpu.l2cache.overall_hits::total 5 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 406 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 167.286066 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006062 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 7 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 345 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 453 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 351 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses -system.cpu.l2cache.overall_misses::total 453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16645000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3017000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19662000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2768500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2768500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16645000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5785500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22430500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16645000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5785500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22430500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 345 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses +system.cpu.l2cache.overall_misses::total 446 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16357500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19338000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2765500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2765500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16357500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5746000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22103500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16357500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5746000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22103500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 458 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 458 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987835 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982906 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.982759 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989083 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989083 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47421.652422 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54854.545455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48428.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58904.255319 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58904.255319 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49515.452539 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49515.452539 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982906 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.984547 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47413.043478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55194.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48466.165414 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58840.425532 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58840.425532 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49559.417040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49559.417040 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,50 +635,156 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 345 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12250512 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2337054 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14587566 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2189544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2189544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12250512 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4526598 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16777110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12250512 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4526598 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16777110 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 345 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035015 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2314548 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14349563 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2186544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2186544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035015 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4501092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16536107 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035015 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4501092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16536107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34901.743590 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42491.890909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35929.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46586.042553 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46586.042553 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34884.101449 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42862 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35963.817043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46522.212766 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46522.212766 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use +system.cpu.dcache.total_refs 2190 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.470588 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 63.407702 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015480 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015480 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1475 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2190 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2190 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2190 # number of overall hits +system.cpu.dcache.overall_hits::total 2190 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 104 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 331 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 331 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 435 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses +system.cpu.dcache.overall_misses::total 435 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5221500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5221500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14127997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14127997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19349497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19349497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19349497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19349497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2625 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2625 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2625 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2625 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065864 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065864 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.316444 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.730769 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.730769 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42682.770393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42682.770393 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44481.602299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44481.602299 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.800000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 333 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 333 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 333 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2814999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2814999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5860999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5860999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5860999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5860999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55381.818182 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55381.818182 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59893.595745 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59893.595745 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 2fea3a81f..505121624 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -123,22 +123,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -155,24 +155,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -182,10 +182,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -200,7 +200,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -222,15 +222,28 @@ master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index c486c847c..ff91b8c31 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:12:48 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18878500 because target called exit() +Hello World!Exiting @ tick 16286500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 0f666ffe1..f975c5003 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16282500 # Number of ticks simulated -final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16286500 # Number of ticks simulated +final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46082 # Simulator instruction rate (inst/s) -host_op_rate 46072 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140796560 # Simulator tick rate (ticks/s) -host_mem_usage 222960 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 32524 # Simulator instruction rate (inst/s) +host_op_rate 32520 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 99417983 # Simulator tick rate (ticks/s) +host_mem_usage 221588 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1135664507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 526571086 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1662235594 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1135664507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1135664507 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1135664507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 526571086 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1662235594 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16231000 # Total gap between requests +system.physmem.totGap 16235000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,17 +164,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2301921 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests +system.physmem.totQLat 2302422 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11302422 # Sum of mem lat for all requests system.physmem.totBusLat 1692000 # Total cycles spent in databus access system.physmem.totBankLat 7308000 # Total cycles spent in bank access -system.physmem.avgQLat 5441.89 # Average queueing delay per request +system.physmem.avgQLat 5443.08 # Average queueing delay per request system.physmem.avgBankLat 17276.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26718.49 # Average memory access latency -system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26719.67 # Average memory access latency +system.physmem.avgRdBW 1662.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1662.24 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 10.39 # Data bus utilization in percentage @@ -184,44 +184,44 @@ system.physmem.readRowHits 336 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 38371.16 # Average gap between requests +system.physmem.avgGap 38380.61 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 32566 # number of cpu cycles simulated +system.cpu.numCycles 32574 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1630 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits +system.cpu.branch_predictor.lookups 1636 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1090 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 897 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 1343 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 584 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 43.484736 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9600 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1483 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 838 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 277 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 75.156951 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3966 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 1472 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3957 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9655 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6202 # Number of cycles cpu stages are processed. -system.cpu.activity 19.044402 # Percentage of cycles cpu is active +system.cpu.idleCycles 26327 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6247 # Number of cycles cpu stages are processed. +system.cpu.activity 19.177872 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -233,72 +233,72 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.114886 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads -system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.114886 # CPI: Total CPI of All Threads +system.cpu.ipc 0.163535 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.163535 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 27935 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 14.241420 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.814576 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 29541 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.311107 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 31599 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.993185 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29417 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use -system.cpu.icache.total_refs 814 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use +system.cpu.icache.total_refs 896 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits -system.cpu.icache.overall_hits::total 814 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.308998 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.308998 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.308998 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.308998 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.308998 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.308998 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50600.274725 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50600.274725 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50600.274725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50600.274725 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits +system.cpu.icache.overall_hits::total 896 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses +system.cpu.icache.overall_misses::total 362 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18347500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18347500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18347500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50683.701657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50683.701657 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -307,12 +307,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses @@ -325,12 +325,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency @@ -339,14 +339,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 85.214129 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 85.214129 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020804 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020804 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits @@ -363,14 +363,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3347500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19185000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19185000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22532500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22532500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22532500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22532500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54877.049180 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54877.049180 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46452.784504 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46452.784504 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47536.919831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47536.919831 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked @@ -421,12 +421,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 135 system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4153500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4153500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7092500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7092500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7092500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7092500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -437,22 +437,22 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51277.777778 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 169.991473 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.874602 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.116871 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004360 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.886606 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.119790 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits @@ -478,14 +478,14 @@ system.cpu.l2cache.overall_misses::total 423 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4070000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4070000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4069000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4069000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6942500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6941500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21817000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6942500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6941500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21817000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -511,14 +511,14 @@ system.cpu.l2cache.overall_miss_rate::total 0.992958 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50246.913580 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50246.913580 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50234.567901 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50234.567901 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51579.196217 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51576.832151 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51579.196217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51802.238806 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51576.832151 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11235436 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11236437 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13444009 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066068 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066068 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11236437 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5273640 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16510077 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11236437 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5273640 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16510077 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38880.404844 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.967836 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37852.691358 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37852.691358 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38880.404844 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index a6a41648e..5620e85e4 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -82,7 +82,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -106,7 +106,7 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 3e672ef03..3359de27e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:12:59 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:02 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 9a9c3bf56..a4c6ca2b7 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 126208 # Simulator instruction rate (inst/s) -host_op_rate 126157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63788253 # Simulator tick rate (ticks/s) -host_mem_usage 221040 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 63026 # Simulator instruction rate (inst/s) +host_op_rate 63015 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 31868954 # Simulator tick rate (ticks/s) +host_mem_usage 212680 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index 61c642df2..ab18e451d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -106,7 +106,7 @@ version=0 [system.dir_cntrl0.directory] type=RubyDirectoryMemory map_levels=4 -numa_high_bit=6 +numa_high_bit=5 size=134217728 use_map=false version=0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr index e45cd058f..5da3f0737 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr @@ -1,2 +1,6 @@ +Warning: rounding error > tolerance + 0.072760 rounded to 0 +Warning: rounding error > tolerance + 0.072760 rounded to 0 warn: Sockets disabled, not accepting gdb connections hack: be nice to actually delete the event here diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index d65bb97a2..18fb5a397 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout -Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 9 2012 13:47:14 -gem5 started Sep 9 2012 13:47:33 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:45:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 59ceed6d6..0ee67c488 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000108 # Nu sim_ticks 107952 # Number of ticks simulated final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 10153 # Simulator instruction rate (inst/s) -host_op_rate 10153 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 205737 # Simulator tick rate (ticks/s) -host_mem_usage 240612 # Number of bytes of host memory used -host_seconds 0.52 # Real time elapsed on the host +host_inst_rate 33106 # Simulator instruction rate (inst/s) +host_op_rate 33103 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 670773 # Simulator tick rate (ticks/s) +host_mem_usage 232832 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 135ea172c..bf88dfd5e 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -61,22 +61,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -92,22 +92,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=20 trace_addr=0 two_queue=false write_buffers=8 @@ -124,24 +124,24 @@ size=64 [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=10000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -151,10 +151,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -169,7 +169,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/sparc/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -193,7 +193,7 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index 2fc16fb0f..ff092cd6d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 13 2012 17:04:37 -gem5 started Aug 13 2012 18:13:07 -gem5 executing on zizzer +gem5 compiled Nov 2 2012 11:45:16 +gem5 started Nov 2 2012 11:46:02 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 29527000 because target called exit() +Hello World!Exiting @ tick 27800000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 37ab13bca..df9fd5f9b 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 251441 # Simulator instruction rate (inst/s) -host_op_rate 251244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1310200039 # Simulator tick rate (ticks/s) -host_mem_usage 220428 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 85623 # Simulator instruction rate (inst/s) +host_op_rate 85602 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 446634768 # Simulator tick rate (ticks/s) +host_mem_usage 221096 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 98b722b0c..85178b3d5 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a -clock=1 +clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 @@ -30,7 +30,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -129,18 +130,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=262144 subblock_size=0 system=system @@ -159,7 +160,7 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[3] @@ -431,18 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=10 +mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=2 size=131072 subblock_size=0 system=system @@ -455,7 +456,7 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=X86LocalApic -clock=1 +clock=500 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -464,6 +465,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -472,31 +476,31 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker -clock=1 +clock=500 system=system port=system.cpu.toL2Bus.slave[2] [system.cpu.l2cache] type=BaseCache addr_ranges=0:18446744073709551615 -assoc=2 +assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true hash_delay=1 -hit_latency=1000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=10 +mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null -response_latency=1000 +response_latency=20 size=2097152 subblock_size=0 system=system -tgts_per_mshr=5 +tgts_per_mshr=12 trace_addr=0 two_queue=false write_buffers=8 @@ -506,10 +510,10 @@ mem_side=system.membus.slave[1] [system.cpu.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false -width=8 +width=32 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -524,7 +528,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -546,15 +550,28 @@ master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_s slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[0] diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 1bec04837..c8ef0214a 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,13 +1,11 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 10 2012 21:50:34 -gem5 started Sep 10 2012 21:50:39 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Oct 30 2012 11:14:29 +gem5 started Oct 30 2012 16:15:47 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12607000 because target called exit() +Exiting @ tick 15014000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 272509d41..e6a1ad3f3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,53 +1,53 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15249000 # Number of ticks simulated -final_tick 15249000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15014000 # Number of ticks simulated +final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41998 # Simulator instruction rate (inst/s) -host_op_rate 76065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119014725 # Simulator tick rate (ticks/s) -host_mem_usage 225728 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 32657 # Simulator instruction rate (inst/s) +host_op_rate 59148 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91121721 # Simulator tick rate (ticks/s) +host_mem_usage 223384 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory -system.physmem.bytes_read::total 28800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1280083940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 608564496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1888648436 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1280083940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1280083940 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1280083940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 608564496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1888648436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 451 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory +system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19392 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory +system.physmem.num_reads::total 449 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1291594512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 622352471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1913946983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1291594512 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1291594512 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1291594512 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 622352471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1913946983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 450 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 28800 # Total number of bytes read from memory +system.physmem.cpureqs 450 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28736 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 28800 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28736 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::0 41 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 55 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 23 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 52 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 23 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 29 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15226500 # Total gap between requests +system.physmem.totGap 14992500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 451 # Categorize read packet sizes +system.physmem.readPktSize::6 450 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -99,8 +99,8 @@ system.physmem.neitherpktsize::6 0 # ca system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -164,265 +164,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1663951 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11993951 # Sum of mem lat for all requests -system.physmem.totBusLat 1804000 # Total cycles spent in databus access -system.physmem.totBankLat 8526000 # Total cycles spent in bank access -system.physmem.avgQLat 3689.47 # Average queueing delay per request -system.physmem.avgBankLat 18904.66 # Average bank access latency per request +system.physmem.totQLat 1656450 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12024450 # Sum of mem lat for all requests +system.physmem.totBusLat 1800000 # Total cycles spent in databus access +system.physmem.totBankLat 8568000 # Total cycles spent in bank access +system.physmem.avgQLat 3681.00 # Average queueing delay per request +system.physmem.avgBankLat 19040.00 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26594.13 # Average memory access latency -system.physmem.avgRdBW 1888.65 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26721.00 # Average memory access latency +system.physmem.avgRdBW 1913.95 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1888.65 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1913.95 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 11.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.79 # Average read queue length over time +system.physmem.busUtil 11.96 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.80 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 354 # Number of row buffer hits during reads +system.physmem.readRowHits 352 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.49 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33761.64 # Average gap between requests +system.physmem.avgGap 33316.67 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30499 # number of cpu cycles simulated +system.cpu.numCycles 30029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3124 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3124 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 575 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2554 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits +system.cpu.BPredUnit.lookups 3018 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 9097 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15002 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3124 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4073 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2573 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3671 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1972 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 19065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.398846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.899430 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.378572 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.879282 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 15096 79.18% 79.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 179 0.94% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 149 0.78% 80.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 207 1.09% 81.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 0.94% 82.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 177 0.93% 83.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 231 1.21% 85.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 192 1.01% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2655 13.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14745 79.35% 79.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.02% 80.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 157 0.84% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 193 1.04% 82.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 162 0.87% 83.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 175 0.94% 84.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 261 1.40% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 0.87% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2540 13.67% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 19065 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.102430 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.491885 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9663 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3644 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1953 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25430 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10013 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2382 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 508 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3439 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 770 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 23869 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 648 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26126 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57405 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 57389 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 18583 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.100503 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.483266 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9455 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3616 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3547 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1830 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24449 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1830 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9798 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2386 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 485 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3325 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 759 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 22967 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 640 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 25104 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 55188 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 55172 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15066 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 14044 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 31 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2094 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1772 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21302 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 2021 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2205 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1755 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 20454 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17998 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10762 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14777 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17349 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 213 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9974 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13873 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 19065 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.944034 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.806602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18583 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.933595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.794406 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13533 70.98% 70.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1394 7.31% 78.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1058 5.55% 83.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 719 3.77% 87.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 757 3.97% 91.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 676 3.55% 95.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 613 3.22% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 275 1.44% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 40 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13202 71.04% 71.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1386 7.46% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1042 5.61% 84.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 691 3.72% 87.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 742 3.99% 91.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 3.35% 95.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 598 3.22% 98.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 257 1.38% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 19065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18583 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 132 74.58% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.58% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 23 12.99% 87.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 22 12.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 138 77.53% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19 10.67% 88.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 11.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14399 80.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2084 11.58% 91.60% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1511 8.40% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13962 80.48% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.51% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1900 10.95% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1482 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17998 # Type of FU issued -system.cpu.iq.rate 0.590118 # Inst issue rate -system.cpu.iq.fu_busy_cnt 177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.009834 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 55439 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32107 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16514 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17349 # Type of FU issued +system.cpu.iq.rate 0.577742 # Inst issue rate +system.cpu.iq.fu_busy_cnt 178 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010260 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53664 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30472 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16003 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18167 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17518 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 180 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 157 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 838 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1153 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 821 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 30 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21339 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1772 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 1830 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1703 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 20491 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2205 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1755 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 717 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17023 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1944 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 975 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 601 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 657 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16425 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1777 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 924 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3334 # number of memory reference insts executed -system.cpu.iew.exec_branches 1674 # Number of branches executed -system.cpu.iew.exec_stores 1390 # Number of stores executed -system.cpu.iew.exec_rate 0.558149 # Inst execution rate -system.cpu.iew.wb_sent 16747 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16518 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10593 # num instructions producing a value -system.cpu.iew.wb_consumers 16382 # num instructions consuming a value +system.cpu.iew.exec_refs 3140 # number of memory reference insts executed +system.cpu.iew.exec_branches 1630 # Number of branches executed +system.cpu.iew.exec_stores 1363 # Number of stores executed +system.cpu.iew.exec_rate 0.546971 # Inst execution rate +system.cpu.iew.wb_sent 16197 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16007 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10178 # num instructions producing a value +system.cpu.iew.wb_consumers 15727 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.541592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.646624 # average fanout of values written-back +system.cpu.iew.wb_rate 0.533051 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11593 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10745 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 17112 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.569483 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.430880 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 566 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.581687 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.458321 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13541 79.13% 79.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1338 7.82% 86.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 619 3.62% 90.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 703 4.11% 94.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 373 2.18% 96.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 140 0.82% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 121 0.71% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 74 0.43% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 203 1.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13226 78.95% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1316 7.86% 86.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 596 3.56% 90.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 710 4.24% 94.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 351 2.10% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 138 0.82% 97.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 120 0.72% 98.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 75 0.45% 98.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 17112 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16753 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -433,283 +433,179 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 38247 # The number of ROB reads -system.cpu.rob.rob_writes 44659 # The number of ROB writes -system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11434 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 37022 # The number of ROB reads +system.cpu.rob.rob_writes 42839 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11446 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.668959 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.668959 # CPI: Total CPI of All Threads -system.cpu.ipc 0.176399 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.176399 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 29908 # number of integer regfile reads -system.cpu.int_regfile_writes 17845 # number of integer regfile writes +system.cpu.cpi 5.581599 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.581599 # CPI: Total CPI of All Threads +system.cpu.ipc 0.179160 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.179160 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28874 # number of integer regfile reads +system.cpu.int_regfile_writes 17232 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7467 # number of misc regfile reads +system.cpu.misc_regfile_reads 7155 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.993781 # Cycle average of tags in use -system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 306 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.117647 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use +system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.993781 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071286 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071286 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits -system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 406 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 406 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 406 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 406 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 406 # number of overall misses -system.cpu.icache.overall_misses::total 406 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19356000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19356000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19356000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19356000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19356000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19356000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1972 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1972 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1972 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1972 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1972 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205882 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.205882 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.205882 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.205882 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.205882 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.205882 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47674.876847 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47674.876847 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47674.876847 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47674.876847 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 302 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1482 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1482 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits +system.cpu.icache.overall_hits::total 1482 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses +system.cpu.icache.overall_misses::total 398 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 43.142857 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15469000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15469000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15469000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15469000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15469000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15469000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155172 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155172 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.155172 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50552.287582 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50552.287582 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15461500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15461500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.489938 # Cycle average of tags in use -system.cpu.dcache.total_refs 2406 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.825175 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.489938 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020383 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020383 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1548 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1548 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2406 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2406 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2406 # number of overall hits -system.cpu.dcache.overall_hits::total 2406 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 208 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses -system.cpu.dcache.overall_misses::total 208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6548500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6548500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4231000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4231000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 10779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 10779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 10779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 10779500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1680 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1680 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078571 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078571 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.079572 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.079572 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.079572 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.079572 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49609.848485 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49609.848485 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55671.052632 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51824.519231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51824.519231 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 108 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 62 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3696500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3696500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4079000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4079000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7775500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7775500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7775500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7775500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041667 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055853 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055853 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52807.142857 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52807.142857 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53671.052632 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53671.052632 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 179.176449 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002674 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 146.139957 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.036492 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004460 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005468 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 305 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 70 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 375 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 71 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 374 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 76 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 76 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 305 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15152000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3773500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18925500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4003000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4003000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15152000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7776500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15152000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7776500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22928500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 303 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses +system.cpu.l2cache.overall_misses::total 450 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 306 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 306 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996732 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996711 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997340 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997333 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996732 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996711 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997788 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997783 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49678.688525 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53907.142857 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50468 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52671.052632 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52671.052632 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50839.246120 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50839.246120 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -718,50 +614,154 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 305 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 375 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 374 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 305 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11317954 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2918074 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14236028 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3040610 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3040610 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11317954 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5958684 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17276638 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11317954 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5958684 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17276638 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17309634 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11336452 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5973182 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17309634 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997333 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37108.045902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41686.771429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37962.741333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.026316 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40008.026316 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use +system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits +system.cpu.dcache.overall_hits::total 2284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses +system.cpu.dcache.overall_misses::total 202 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6336000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10556500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10556500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10556500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10556500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1552 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081186 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081186 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50285.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50285.714286 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7803500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7803500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7803500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7803500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045747 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |