diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref')
107 files changed, 4517 insertions, 2942 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index b17544f09..afc8aa811 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index ba10334c5..ff8d4bf12 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 4ce82e64f..fc30a21c8 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000021 # Nu sim_ticks 21216000 # Number of ticks simulated final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36015 # Simulator instruction rate (inst/s) -host_tick_rate 119302866 # Simulator tick rate (ticks/s) -host_mem_usage 207132 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 38129 # Simulator instruction rate (inst/s) +host_op_rate 38124 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 126288909 # Simulator tick rate (ticks/s) +host_mem_usage 209388 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30016 # Number of bytes read from this memory system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -68,9 +70,10 @@ system.cpu.comNops 17 # Nu system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed -system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads @@ -124,26 +127,39 @@ system.cpu.icache.total_refs 581 # To system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits -system.cpu.icache.demand_hits 581 # number of demand (read+write) hits -system.cpu.icache.overall_hits 581 # number of overall hits -system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses -system.cpu.icache.demand_misses 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits +system.cpu.icache.overall_hits::total 581 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses +system.cpu.icache.overall_misses::total 348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 46 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 46 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 46 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 302 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 302 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 302 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.325081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.325081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.325081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use @@ -180,32 +199,49 @@ system.cpu.dcache.total_refs 1703 # To system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 102.671807 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025066 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 615 # number of WriteReq hits -system.cpu.dcache.demand_hits 1703 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1703 # number of overall hits -system.cpu.dcache.ReadReq_misses 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 250 # number of WriteReq misses -system.cpu.dcache.demand_misses 347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 13555500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 19064000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.081857 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.169268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 54222 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 54939.481268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 54939.481268 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits +system.cpu.dcache.overall_hits::total 1703 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses +system.cpu.dcache.overall_misses::total 347 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -214,32 +250,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 177 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 179 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 9024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use @@ -247,31 +289,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 396 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997481 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # 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number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.l2cache.overall_misses::total 469 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -280,30 +355,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 396 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index db5baf5c5..79efc9749 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 6e993ab1c..684d7e9b2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 3b3d572bb..49671266a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu sim_ticks 12004500 # Number of ticks simulated final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38695 # Simulator instruction rate (inst/s) -host_tick_rate 72731813 # Simulator tick rate (ticks/s) -host_mem_usage 208040 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 42281 # Simulator instruction rate (inst/s) +host_op_rate 42276 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79460110 # Simulator tick rate (ticks/s) +host_mem_usage 210060 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated +sim_ops 6386 # Number of ops (including micro ops) simulated system.physmem.bytes_read 31040 # Number of bytes read from this memory system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -270,6 +272,7 @@ system.cpu.iew.wb_rate 0.374511 # in system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions +system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted @@ -290,7 +293,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle -system.cpu.commit.count 6403 # Number of instructions committed +system.cpu.commit.committedInsts 6403 # Number of instructions committed +system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2050 # Number of memory references committed system.cpu.commit.loads 1185 # Number of loads committed @@ -306,6 +310,7 @@ system.cpu.rob.rob_writes 24313 # Th system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated +system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads @@ -323,26 +328,39 @@ system.cpu.icache.total_refs 1606 # To system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 160.112304 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1606 # number of ReadReq hits -system.cpu.icache.demand_hits 1606 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1606 # number of overall hits -system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses -system.cpu.icache.demand_misses 433 # number of demand (read+write) misses -system.cpu.icache.overall_misses 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15431000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15431000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.212359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.212359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.212359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35637.413395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35637.413395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35637.413395 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.112304 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078180 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078180 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1606 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1606 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1606 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1606 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1606 # number of overall hits +system.cpu.icache.overall_hits::total 1606 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses +system.cpu.icache.overall_misses::total 433 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15431000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15431000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15431000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15431000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15431000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212359 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212359 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212359 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,27 +369,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.153016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.153016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.153016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.717949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 121 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 121 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 121 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 121 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11021000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11021000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use @@ -379,32 +400,49 @@ system.cpu.dcache.total_refs 2154 # To system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 109.290272 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits -system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2154 # number of overall hits -system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses -system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 17965000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35698.051948 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 35225.490196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 35225.490196 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 109.290272 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026682 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1645 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1645 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2154 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2154 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2154 # number of overall hits +system.cpu.dcache.overall_hits::total 2154 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 154 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12467500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12467500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17965000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17965000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17965000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17965000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1799 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2664 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2664 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.191441 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.191441 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +451,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36183.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2611500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6266000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6266000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6266000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056142 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use @@ -446,31 +490,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.643066 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006764 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 485 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 16676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 16676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 413 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997579 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997942 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34376.213592 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34384.536082 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34384.536082 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 160.084939 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 61.558127 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004885 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001879 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -479,30 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12850000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15136000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997579 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997942 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini index df86e7077..f91bbd9dc 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout index 9f50fe960..2f9b31423 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 7ceb6a8be..97b8faa6b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 3215000 # Number of ticks simulated final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76916 # Simulator instruction rate (inst/s) -host_tick_rate 38606134 # Simulator tick rate (ticks/s) -host_mem_usage 198176 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 35037 # Simulator instruction rate (inst/s) +host_op_rate 35032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17585099 # Simulator tick rate (ticks/s) +host_mem_usage 199940 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 6431 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index b9fd9c5f2..dd4aa648f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -66,7 +79,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -134,6 +147,7 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer to_l2_latency=1 transitions_per_cycle=32 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats index c2d3c97af..d2cdb9ada 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,26 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/23/2012 04:21:55 +Real time: Feb/12/2012 15:33:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.38 -Virtual_time_in_minutes: 0.00633333 -Virtual_time_in_hours: 0.000105556 -Virtual_time_in_days: 4.39815e-06 +Virtual_time_in_seconds: 1.01 +Virtual_time_in_minutes: 0.0168333 +Virtual_time_in_hours: 0.000280556 +Virtual_time_in_days: 1.16898e-05 Ruby_current_time: 279353 Ruby_start_time: 0 Ruby_cycles: 279353 -mbytes_resident: 45.5547 -mbytes_total: 214.371 -resident_ratio: 0.212504 +mbytes_resident: 0 +mbytes_total: 0 ruby_cycles_executed: [ 279354 ] @@ -101,9 +100,9 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 20 count: 9645 average: 0.064282 | standard deviation: 0.540462 | 9495 0 1 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] +Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 2725 average: 0.226789 | standard deviation: 0.997795 | 2576 0 0 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ] virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ] @@ -119,11 +118,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11862 -page_faults: 127 +page_reclaims: 13214 +page_faults: 148 swaps: 0 -block_inputs: 22816 -block_outputs: 96 +block_inputs: 2 +block_outputs: 4 Network Stats ------------- @@ -320,11 +319,6 @@ M_I Fwd_GETS [0 ] 0 M_I Fwd_GET_INSTR [0 ] 0 M_I WB_Ack [436 ] 436 -E_I Load [0 ] 0 -E_I Ifetch [0 ] 0 -E_I Store [0 ] 0 -E_I L1_Replacement [0 ] 0 - SINK_WB_ACK Load [0 ] 0 SINK_WB_ACK Ifetch [0 ] 0 SINK_WB_ACK Store [0 ] 0 @@ -348,7 +342,7 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - L1_GET_INSTR [691 ] 691 -L1_GETS [586 ] 586 +L1_GETS [585 ] 585 L1_GETX [216 ] 216 L1_UPGRADE [0 ] 0 L1_PUTX [436 ] 436 @@ -405,7 +399,7 @@ MT L2_Replacement_clean [352 ] 352 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [3 ] 3 +M_I L1_GETS [2 ] 2 M_I L1_GETX [0 ] 0 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index c93c8f8af..a25a5c879 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:44:57 -gem5 started Jan 23 2012 04:21:53 -gem5 executing on zizzer -command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory +gem5 compiled Feb 12 2012 15:33:08 +gem5 started Feb 12 2012 15:33:21 +gem5 executing on Alis-MacBook-Pro.local +command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index 3bba58631..de3976298 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000279 # Nu sim_ticks 279353 # Number of ticks simulated final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 2836 # Simulator instruction rate (inst/s) -host_tick_rate 123728 # Simulator tick rate (ticks/s) -host_mem_usage 219520 # Number of bytes of host memory used -host_seconds 2.26 # Real time elapsed on the host +host_inst_rate 12170 # Simulator instruction rate (inst/s) +host_op_rate 12169 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 530781 # Simulator tick rate (ticks/s) +host_mem_usage 270088 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 279353 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 607ab419c..38b836011 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -132,6 +145,7 @@ number_of_TBEs=256 recycle_latency=10 request_latency=2 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index ed47704f6..aa46612d8 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:47:36 -gem5 started Jan 23 2012 04:22:12 +gem5 compiled Feb 11 2012 13:06:37 +gem5 started Feb 11 2012 13:53:23 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory +command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 44a6426b2..02467cae9 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000224 # Nu sim_ticks 223694 # Number of ticks simulated final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 19611 # Simulator instruction rate (inst/s) -host_tick_rate 684980 # Simulator tick rate (ticks/s) -host_mem_usage 219636 # Number of bytes of host memory used -host_seconds 0.33 # Real time elapsed on the host +host_inst_rate 37589 # Simulator instruction rate (inst/s) +host_op_rate 37585 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1312743 # Simulator tick rate (ticks/s) +host_mem_usage 221408 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 223694 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index e664ed4cf..0617e8d38 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -141,6 +154,7 @@ number_of_TBEs=256 recycle_latency=10 retry_threshold=1 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index 6ef144b06..0b4972a17 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:50:16 -gem5 started Jan 23 2012 04:22:25 +gem5 compiled Feb 11 2012 13:07:02 +gem5 started Feb 11 2012 13:54:08 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token +command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 4911f0b0e..e1d06acb6 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000232 # Nu sim_ticks 231701 # Number of ticks simulated final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 23819 # Simulator instruction rate (inst/s) -host_tick_rate 861729 # Simulator tick rate (ticks/s) -host_mem_usage 217800 # Number of bytes of host memory used -host_seconds 0.27 # Real time elapsed on the host +host_inst_rate 59077 # Simulator instruction rate (inst/s) +host_op_rate 59067 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2136733 # Simulator tick rate (ticks/s) +host_mem_usage 219660 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 231701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index aa987ffa6..15b38dd1a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -147,6 +160,7 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index fa89dfcd6..9412b907c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:42:19 -gem5 started Jan 23 2012 04:21:43 +gem5 compiled Feb 11 2012 13:05:44 +gem5 started Feb 11 2012 13:52:39 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer +command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index dfbcac63c..87ed3fb4b 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000208 # Nu sim_ticks 208400 # Number of ticks simulated final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 24253 # Simulator instruction rate (inst/s) -host_tick_rate 789193 # Simulator tick rate (ticks/s) -host_mem_usage 217184 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 64619 # Simulator instruction rate (inst/s) +host_op_rate 64607 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2102096 # Simulator tick rate (ticks/s) +host_mem_usage 218760 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 208400 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini index 0772d2ee5..3d3a73e3a 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout index 9cf822901..05fd4efdd 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt index beb747c41..168276764 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000343 # Nu sim_ticks 342698 # Number of ticks simulated final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 32385 # Simulator instruction rate (inst/s) -host_tick_rate 1732860 # Simulator tick rate (ticks/s) -host_mem_usage 218476 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 61504 # Simulator instruction rate (inst/s) +host_op_rate 61493 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3290073 # Simulator tick rate (ticks/s) +host_mem_usage 220236 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 34460 # Number of bytes read from this memory system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory system.physmem.bytes_written 6696 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 342698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index f51983ecf..3b46c790f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index d977e688b..5e2927c57 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:58:59 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:12 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 84a161e81..6278fa873 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000033 # Nu sim_ticks 33007000 # Number of ticks simulated final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 110064 # Simulator instruction rate (inst/s) -host_tick_rate 566999999 # Simulator tick rate (ticks/s) -host_mem_usage 206896 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 37663 # Simulator instruction rate (inst/s) +host_op_rate 37658 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 194071847 # Simulator tick rate (ticks/s) +host_mem_usage 209060 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated +sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28544 # Number of bytes read from this memory system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 17 # Nu system.cpu.numCycles 66014 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 6404 # Number of instructions executed +system.cpu.committedInsts 6404 # Number of instructions committed +system.cpu.committedOps 6404 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses system.cpu.num_func_calls 251 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 6136 # To system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits -system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits -system.cpu.icache.overall_hits 6136 # number of overall hits -system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses -system.cpu.icache.demand_misses 279 # number of demand (read+write) misses -system.cpu.icache.overall_misses 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits +system.cpu.icache.overall_hits::total 6136 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 279 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 279 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses +system.cpu.icache.overall_misses::total 279 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15582000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15582000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15582000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15582000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15582000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6415 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6415 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6415 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6415 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6415 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043492 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.043492 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.043492 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 279 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 279 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 279 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.043492 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.043492 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.043492 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 279 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043492 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 1882 # To system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.025313 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits -system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1882 # number of overall hits -system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5320000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5320000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5320000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4088000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4088000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9408000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9408000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9408000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080169 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081951 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081951 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use @@ -198,31 +229,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005626 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 373 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 446 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23192000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 374 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 447 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.997326 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997763 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.l2cache.overall_misses::total 446 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 279 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 279 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996416 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -231,30 +295,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index f0e8b9ebf..d74613835 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 2afd9a6f8..6aed6d3ac 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:23 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d94c5613d..d93b581f0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000007 # Nu sim_ticks 6833000 # Number of ticks simulated final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46364 # Simulator instruction rate (inst/s) -host_tick_rate 132671945 # Simulator tick rate (ticks/s) -host_mem_usage 207164 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 16400 # Simulator instruction rate (inst/s) +host_op_rate 16398 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46934615 # Simulator tick rate (ticks/s) +host_mem_usage 209144 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated +sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read 17280 # Number of bytes read from this memory system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -269,6 +271,7 @@ system.cpu.iew.wb_rate 0.261872 # in system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions +system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted @@ -289,7 +292,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle -system.cpu.commit.count 2576 # Number of instructions committed +system.cpu.commit.committedInsts 2576 # Number of instructions committed +system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 709 # Number of memory references committed system.cpu.commit.loads 415 # Number of loads committed @@ -305,6 +309,7 @@ system.cpu.rob.rob_writes 10410 # Th system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated +system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads @@ -321,26 +326,39 @@ system.cpu.icache.total_refs 700 # To system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits -system.cpu.icache.demand_hits 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits 700 # number of overall hits -system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses -system.cpu.icache.demand_misses 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits +system.cpu.icache.overall_hits::total 700 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses +system.cpu.icache.overall_misses::total 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -349,27 +367,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use @@ -377,32 +398,49 @@ system.cpu.dcache.total_refs 765 # To system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 45.439198 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 543 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits -system.cpu.dcache.demand_hits 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 765 # number of overall hits -system.cpu.dcache.ReadReq_misses 101 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses -system.cpu.dcache.demand_misses 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6421500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6421500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 644 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.156832 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 37118.497110 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 45.439198 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011094 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 543 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 765 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 765 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 765 # number of overall hits +system.cpu.dcache.overall_hits::total 765 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 173 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 173 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 173 # number of overall misses +system.cpu.dcache.overall_misses::total 173 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3605000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3605000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2816500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6421500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6421500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6421500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 644 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 644 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 938 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 938 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 938 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 938 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.156832 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.184435 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184435 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,32 +449,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2169000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 872000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3041000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3041000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.094720 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 88 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2169000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2169000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 872000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3041000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3041000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3041000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094720 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use @@ -444,30 +488,58 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 120.203882 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 270 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 270 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 8447500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 831000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 9278500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 9278500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 270 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34364.814815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34364.814815 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 91.660485 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.543397 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000871 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 185 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 246 # 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number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6346000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2932500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9278500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6346000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2932500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9278500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -476,30 +548,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # 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average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini index fad1e21b6..d4970301b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout index fdc12b275..8e9c64562 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 23e50fd7f..d3468c0e9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 182014 # Simulator instruction rate (inst/s) -host_tick_rate 91451888 # Simulator tick rate (ticks/s) -host_mem_usage 197324 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 24554 # Simulator instruction rate (inst/s) +host_op_rate 24550 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 12358328 # Simulator tick rate (ticks/s) +host_mem_usage 199092 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 2596 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index 89c8aeac1..2a33a674c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -66,7 +79,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -134,6 +147,7 @@ l2_select_num_bits=0 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer to_l2_latency=1 transitions_per_cycle=32 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats index 1c4da6ce4..9c8b2434f 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,26 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: Jan/23/2012 04:21:58 +Real time: Feb/12/2012 15:33:21 Profiler Stats -------------- -Elapsed_time_in_seconds: 2 -Elapsed_time_in_minutes: 0.0333333 -Elapsed_time_in_hours: 0.000555556 -Elapsed_time_in_days: 2.31481e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.26 -Virtual_time_in_minutes: 0.00433333 -Virtual_time_in_hours: 7.22222e-05 -Virtual_time_in_days: 3.00926e-06 +Virtual_time_in_seconds: 0.71 +Virtual_time_in_minutes: 0.0118333 +Virtual_time_in_hours: 0.000197222 +Virtual_time_in_days: 8.21759e-06 Ruby_current_time: 104867 Ruby_start_time: 0 Ruby_cycles: 104867 -mbytes_resident: 43.0078 -mbytes_total: 212.113 -resident_ratio: 0.202759 +mbytes_resident: 0 +mbytes_total: 0 ruby_cycles_executed: [ 104868 ] @@ -101,9 +100,9 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0636766 | standard deviation: 0.653474 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] +Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.235537 | standard deviation: 1.24505 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ] virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ] @@ -119,11 +118,11 @@ Resource Usage page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 11317 -page_faults: 0 +page_reclaims: 12663 +page_faults: 71 swaps: 0 block_inputs: 0 -block_outputs: 88 +block_outputs: 0 Network Stats ------------- @@ -320,11 +319,6 @@ M_I Fwd_GETS [0 ] 0 M_I Fwd_GET_INSTR [0 ] 0 M_I WB_Ack [124 ] 124 -E_I Load [0 ] 0 -E_I Ifetch [0 ] 0 -E_I Store [0 ] 0 -E_I L1_Replacement [0 ] 0 - SINK_WB_ACK Load [0 ] 0 SINK_WB_ACK Ifetch [0 ] 0 SINK_WB_ACK Store [0 ] 0 @@ -348,8 +342,8 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory --- L2Cache --- - Event Counts - L1_GET_INSTR [300 ] 300 -L1_GETS [206 ] 206 -L1_GETX [70 ] 70 +L1_GETS [205 ] 205 +L1_GETX [69 ] 69 L1_UPGRADE [0 ] 0 L1_PUTX [124 ] 124 L1_PUTX_old [0 ] 0 @@ -405,8 +399,8 @@ MT L2_Replacement_clean [141 ] 141 MT MEM_Inv [0 ] 0 M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [2 ] 2 -M_I L1_GETX [2 ] 2 +M_I L1_GETS [1 ] 1 +M_I L1_GETX [1 ] 1 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 M_I L1_PUTX_old [0 ] 0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index dc0ba2922..22e5bbd3f 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:44:57 -gem5 started Jan 23 2012 04:21:56 -gem5 executing on zizzer -command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory +gem5 compiled Feb 12 2012 15:33:08 +gem5 started Feb 12 2012 15:33:21 +gem5 executing on Alis-MacBook-Pro.local +command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index ebac3fa83..bb0141a2a 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000105 # Nu sim_ticks 104867 # Number of ticks simulated final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 1196 # Simulator instruction rate (inst/s) -host_tick_rate 48657 # Simulator tick rate (ticks/s) -host_mem_usage 217208 # Number of bytes of host memory used -host_seconds 2.16 # Real time elapsed on the host +host_inst_rate 10837 # Simulator instruction rate (inst/s) +host_op_rate 10836 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 440871 # Simulator tick rate (ticks/s) +host_mem_usage 267756 # Number of bytes of host memory used +host_seconds 0.24 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 104867 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index e5748fef4..1d5a893ff 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -132,6 +145,7 @@ number_of_TBEs=256 recycle_latency=10 request_latency=2 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 0529ad1d8..7ff042055 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:47:36 -gem5 started Jan 23 2012 04:22:12 +gem5 compiled Feb 11 2012 13:06:37 +gem5 started Feb 11 2012 13:53:34 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory +command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 8d97fa8c6..aeddd4cb4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 13096 # Simulator instruction rate (inst/s) -host_tick_rate 434048 # Simulator tick rate (ticks/s) -host_mem_usage 217400 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 37008 # Simulator instruction rate (inst/s) +host_op_rate 36998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1226055 # Simulator tick rate (ticks/s) +host_mem_usage 219168 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 85418 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 4c0569af0..d5f1dd8ea 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -141,6 +154,7 @@ number_of_TBEs=256 recycle_latency=10 retry_threshold=1 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 476a0b599..f1a5aa8ce 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:50:16 -gem5 started Jan 23 2012 04:22:25 +gem5 compiled Feb 11 2012 13:07:02 +gem5 started Feb 11 2012 13:54:19 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token +command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index fd5600236..bd362a91b 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000088 # Nu sim_ticks 87899 # Number of ticks simulated final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 12702 # Simulator instruction rate (inst/s) -host_tick_rate 433208 # Simulator tick rate (ticks/s) -host_mem_usage 216416 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 58227 # Simulator instruction rate (inst/s) +host_op_rate 58203 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1984496 # Simulator tick rate (ticks/s) +host_mem_usage 218264 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 87899 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index 209bb4d8d..82df55c27 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -147,6 +160,7 @@ no_mig_atomic=true number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 20c68eff3..f44aeab20 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:42:19 -gem5 started Jan 23 2012 04:21:49 +gem5 compiled Feb 11 2012 13:05:44 +gem5 started Feb 11 2012 13:52:40 gem5 executing on zizzer -command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer +command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 5c579e1af..a79092ea7 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000078 # Nu sim_ticks 78448 # Number of ticks simulated final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 29294 # Simulator instruction rate (inst/s) -host_tick_rate 891567 # Simulator tick rate (ticks/s) -host_mem_usage 215964 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 53931 # Simulator instruction rate (inst/s) +host_op_rate 53912 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1640583 # Simulator tick rate (ticks/s) +host_mem_usage 217556 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 78448 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini index 2d5b16f7e..1b51d074e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=AlphaTLB size=64 +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout index af1c56980..acdbe4afb 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt index bcff12bb9..22da3c1b5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000123 # Nu sim_ticks 123378 # Number of ticks simulated final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 44691 # Simulator instruction rate (inst/s) -host_tick_rate 2138947 # Simulator tick rate (ticks/s) -host_mem_usage 216404 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 35379 # Simulator instruction rate (inst/s) +host_op_rate 35370 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1692995 # Simulator tick rate (ticks/s) +host_mem_usage 218176 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 13356 # Number of bytes read from this memory system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory system.physmem.bytes_written 2058 # Number of bytes written to this memory @@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 123378 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 72df69882..bcf14766c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=AlphaInterrupts + [system.cpu.itb] type=AlphaTLB size=48 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 6a994fb76..ec60c2fa2 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:48:33 -gem5 started Jan 23 2012 04:59:27 +gem5 compiled Feb 11 2012 13:05:17 +gem5 started Feb 11 2012 13:09:24 gem5 executing on zizzer -command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index e3a7a00a0..4d24e98d0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000017 # Nu sim_ticks 16769000 # Number of ticks simulated final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 297044 # Simulator instruction rate (inst/s) -host_tick_rate 1928782837 # Simulator tick rate (ticks/s) -host_mem_usage 206044 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 142484 # Simulator instruction rate (inst/s) +host_op_rate 142326 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 925222654 # Simulator tick rate (ticks/s) +host_mem_usage 208204 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated +sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read 15680 # Number of bytes read from this memory system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 33538 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 2577 # Number of instructions executed +system.cpu.committedInsts 2577 # Number of instructions committed +system.cpu.committedOps 2577 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses system.cpu.num_func_calls 140 # number of times a function call or return occured @@ -78,26 +81,39 @@ system.cpu.icache.total_refs 2423 # To system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits -system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits -system.cpu.icache.overall_hits 2423 # number of overall hits -system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses -system.cpu.icache.demand_misses 163 # number of demand (read+write) misses -system.cpu.icache.overall_misses 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits +system.cpu.icache.overall_hits::total 2423 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses +system.cpu.icache.overall_misses::total 163 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use @@ -133,32 +147,49 @@ system.cpu.dcache.total_refs 627 # To system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits -system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 627 # number of overall hits -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses -system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits +system.cpu.dcache.overall_hits::total 627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.dcache.overall_misses::total 82 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1512000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1512000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4592000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4592000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4592000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,30 +198,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use @@ -198,30 +229,58 @@ system.cpu.l2cache.total_refs 0 # To system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.ReadReq_misses 218 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 27 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 245 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 12740000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 27 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 245 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 27 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 27 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 245 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.l2cache.overall_misses::total 245 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 27 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 163 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 82 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 245 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 163 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 82 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 245 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -230,30 +289,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 218 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 27 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 245 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 7fe95aa88..a46f1b25d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -136,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -444,20 +437,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -492,20 +478,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -534,7 +513,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 8159ae453..ab1ef55e9 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout -Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 10 2012 00:18:03 -gem5 started Feb 10 2012 07:27:01 -gem5 executing on ribera.cs.wisc.edu -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:35:50 +gem5 executing on zizzer +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 691966ecb..010933949 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000010 # Nu sim_ticks 10000500 # Number of ticks simulated final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48981 # Simulator instruction rate (inst/s) -host_tick_rate 85336508 # Simulator tick rate (ticks/s) -host_mem_usage 252096 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -sim_insts 5739 # Number of instructions simulated +host_inst_rate 72927 # Simulator instruction rate (inst/s) +host_op_rate 90959 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158457261 # Simulator tick rate (ticks/s) +host_mem_usage 221260 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4600 # Number of instructions simulated +sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 25856 # Number of bytes read from this memory system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -278,7 +280,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted @@ -299,7 +302,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle -system.cpu.commit.count 5739 # Number of instructions committed +system.cpu.commit.committedInsts 4600 # Number of instructions committed +system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2139 # Number of memory references committed system.cpu.commit.loads 1201 # Number of loads committed @@ -314,12 +318,13 @@ system.cpu.rob.rob_reads 21205 # Th system.cpu.rob.rob_writes 22566 # The number of ROB writes system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 5739 # Number of Instructions Simulated -system.cpu.committedInsts_total 5739 # Number of Instructions Simulated -system.cpu.cpi 3.485276 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.485276 # CPI: Total CPI of All Threads -system.cpu.ipc 0.286921 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.286921 # IPC: Total IPC of All Threads +system.cpu.committedInsts 4600 # Number of Instructions Simulated +system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4600 # Number of Instructions Simulated +system.cpu.cpi 4.348261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.348261 # CPI: Total CPI of All Threads +system.cpu.ipc 0.229977 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.229977 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 37816 # number of integer regfile reads system.cpu.int_regfile_writes 7658 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads @@ -331,26 +336,39 @@ system.cpu.icache.total_refs 1559 # To system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.855822 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1559 # number of ReadReq hits -system.cpu.icache.demand_hits 1559 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1559 # number of overall hits -system.cpu.icache.ReadReq_misses 360 # number of ReadReq misses -system.cpu.icache.demand_misses 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12552000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12552000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1919 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1919 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.187598 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.187598 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.187598 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 34866.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 34866.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 34866.666667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.855822 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072684 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072684 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1559 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1559 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1559 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1559 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1559 # number of overall hits +system.cpu.icache.overall_hits::total 1559 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12552000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12552000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12552000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12552000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12552000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12552000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1919 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1919 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1919 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1919 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1919 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1919 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187598 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.187598 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.187598 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,27 +377,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 9945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.154768 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.154768 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.154768 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9945000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9945000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9945000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9945000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use @@ -387,40 +408,63 @@ system.cpu.dcache.total_refs 2331 # To system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.085552 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1702 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 609 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 2311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2311 # number of overall hits -system.cpu.dcache.ReadReq_misses 169 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 304 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses 473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 473 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5350500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10725000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 16075500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16075500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1871 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2784 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2784 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.090326 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate 0.169899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.169899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33986.257928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33986.257928 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 89.085552 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021749 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021749 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1702 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1702 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2311 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2311 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2311 # number of overall hits +system.cpu.dcache.overall_hits::total 2311 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 473 # number of overall misses +system.cpu.dcache.overall_misses::total 473 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5350500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5350500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10725000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10725000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16075500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16075500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16075500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16075500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1871 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2784 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2784 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2784 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2784 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090326 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -429,33 +473,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 57 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 262 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 112 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 112 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 154 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 154 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 154 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 154 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3230000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3230000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4735000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4735000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4735000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059861 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use @@ -463,31 +514,67 @@ system.cpu.l2cache.total_refs 42 # To system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 188.110462 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits -system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 42 # number of overall hits -system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 409 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 140.315748 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 47.794714 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004282 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001459 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 24 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 24 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 24 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 88 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 130 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 409 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 130 # number of overall misses +system.cpu.l2cache.overall_misses::total 409 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9586000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3027500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12613500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1452000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1452000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9586000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4479500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14065500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9586000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4479500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14065500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 112 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 409 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 154 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 154 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.939394 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.785714 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.939394 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -496,31 +583,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 1ee45ad85..a2c85dbcd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,32 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=ArmInterrupts [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -88,7 +119,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index 13e73ddc3..ef47c4ce8 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 04:24:50 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:36:01 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 8e7751fe7..1e73e7e3d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2875500 # Number of ticks simulated final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25921 # Simulator instruction rate (inst/s) -host_tick_rate 12986430 # Simulator tick rate (ticks/s) -host_mem_usage 208728 # Number of bytes of host memory used -host_seconds 0.22 # Real time elapsed on the host -sim_insts 5739 # Number of instructions simulated +host_inst_rate 866385 # Simulator instruction rate (inst/s) +host_op_rate 1077395 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 538148768 # Simulator tick rate (ticks/s) +host_mem_usage 211284 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 4600 # Number of instructions simulated +sim_ops 5739 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22944 # Number of bytes read from this memory system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory system.physmem.bytes_written 3648 # Number of bytes written to this memory @@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.numCycles 5752 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5739 # Number of instructions executed +system.cpu.committedInsts 4600 # Number of instructions committed +system.cpu.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index d881a3977..1d87891a2 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=ArmTLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +106,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +120,21 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=ArmInterrupts + [system.cpu.itb] type=ArmTLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +max_backoff=100000 +min_backoff=0 +sys=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +147,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +169,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 25474862b..378a682d4 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:16:21 -gem5 started Jan 23 2012 04:24:50 +gem5 compiled Feb 11 2012 13:10:40 +gem5 started Feb 11 2012 15:36:11 gem5 executing on zizzer -command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 9108e20ee..a93efeca8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000026 # Nu sim_ticks 26361000 # Number of ticks simulated final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 20483 # Simulator instruction rate (inst/s) -host_tick_rate 95024596 # Simulator tick rate (ticks/s) -host_mem_usage 217432 # Number of bytes of host memory used -host_seconds 0.28 # Real time elapsed on the host -sim_insts 5682 # Number of instructions simulated +host_inst_rate 456104 # Simulator instruction rate (inst/s) +host_op_rate 565540 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2619225899 # Simulator tick rate (ticks/s) +host_mem_usage 220184 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 4574 # Number of instructions simulated +sim_ops 5682 # Number of ops (including micro ops) simulated system.physmem.bytes_read 22400 # Number of bytes read from this memory system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls 13 # Nu system.cpu.numCycles 52722 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5682 # Number of instructions executed +system.cpu.committedInsts 4574 # Number of instructions committed +system.cpu.committedOps 5682 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 185 # number of times a function call or return occured @@ -88,26 +91,39 @@ system.cpu.icache.total_refs 4373 # To system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits -system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits -system.cpu.icache.overall_hits 4373 # number of overall hits -system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses -system.cpu.icache.demand_misses 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits +system.cpu.icache.overall_hits::total 4373 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses +system.cpu.icache.overall_misses::total 241 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use @@ -143,36 +157,57 @@ system.cpu.dcache.total_refs 1941 # To system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 870 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1919 # number of overall hits -system.cpu.dcache.ReadReq_misses 98 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 43 # number of WriteReq misses -system.cpu.dcache.demand_misses 141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7224000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7224000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.068447 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits +system.cpu.dcache.overall_hits::total 1919 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses +system.cpu.dcache.overall_misses::total 141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4816000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4816000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2408000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2408000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7224000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,30 +216,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use @@ -212,31 +247,67 @@ system.cpu.l2cache.total_refs 32 # To system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits -system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 32 # number of overall hits -system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 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of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -245,30 +316,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index 1ccb30b9c..600677fb9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 677598e87..9f59be0ce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:29 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:30 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 78172e7b6..6cd55fbff 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000020 # Nu sim_ticks 19785000 # Number of ticks simulated final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71616 # Simulator instruction rate (inst/s) -host_tick_rate 243111037 # Simulator tick rate (ticks/s) -host_mem_usage 208328 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 101976 # Simulator instruction rate (inst/s) +host_op_rate 101944 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 346042004 # Simulator tick rate (ticks/s) +host_mem_usage 210372 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory system.physmem.bytes_inst_read 20288 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -54,9 +56,10 @@ system.cpu.comNops 657 # Nu system.cpu.comNonSpec 10 # Number of Non-Speculative instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 5827 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads @@ -110,26 +113,39 @@ system.cpu.icache.total_refs 443 # To system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 148.138598 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 443 # number of ReadReq hits -system.cpu.icache.demand_hits 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits 443 # number of overall hits -system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses -system.cpu.icache.demand_misses 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55799.120235 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits +system.cpu.icache.overall_hits::total 443 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses +system.cpu.icache.overall_misses::total 341 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -138,27 +154,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 22 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use @@ -166,32 +185,49 @@ system.cpu.dcache.total_refs 1838 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 89.732679 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 763 # number of WriteReq hits -system.cpu.dcache.demand_hits 1838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1838 # number of overall hits -system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 162 # number of WriteReq misses -system.cpu.dcache.demand_misses 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13984500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.120153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.120153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55715.139442 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 763 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1838 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1838 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1838 # number of overall hits +system.cpu.dcache.overall_hits::total 1838 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 162 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 162 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses +system.cpu.dcache.overall_misses::total 251 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,32 +236,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 111 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 113 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7448500 # 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number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 111 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 111 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use @@ -233,31 +275,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 508c3cad4..00305a8e7 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -80,6 +89,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -88,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -125,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -424,20 +428,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -445,6 +442,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -460,20 +460,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index eb1e6f70f..afa267678 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:41 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:39 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index e49d82dd9..9ff42644b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu sim_ticks 12272500 # Number of ticks simulated final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65845 # Simulator instruction rate (inst/s) -host_tick_rate 156294886 # Simulator tick rate (ticks/s) -host_mem_usage 208908 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 97350 # Simulator instruction rate (inst/s) +host_op_rate 97317 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 230983195 # Simulator tick rate (ticks/s) +host_mem_usage 211060 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated +sim_ops 5169 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30400 # Number of bytes read from this memory system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -255,6 +257,7 @@ system.cpu.iew.wb_rate 0.289986 # in system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted @@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle -system.cpu.commit.count 5826 # Number of instructions committed +system.cpu.commit.committedInsts 5826 # Number of instructions committed +system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2089 # Number of memory references committed system.cpu.commit.loads 1164 # Number of loads committed @@ -291,6 +295,7 @@ system.cpu.rob.rob_writes 20794 # Th system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated +system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads @@ -307,26 +312,39 @@ system.cpu.icache.total_refs 1363 # To system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits -system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1363 # number of overall hits -system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses -system.cpu.icache.demand_misses 418 # number of demand (read+write) misses -system.cpu.icache.overall_misses 418 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits +system.cpu.icache.overall_hits::total 1363 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses +system.cpu.icache.overall_misses::total 418 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -335,27 +353,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 82 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.188658 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.188658 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.188658 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use @@ -363,32 +384,49 @@ system.cpu.dcache.total_refs 2380 # To system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 92.121984 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 578 # number of WriteReq hits -system.cpu.dcache.demand_hits 2380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2380 # number of overall hits -system.cpu.dcache.ReadReq_misses 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 347 # number of WriteReq misses -system.cpu.dcache.demand_misses 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 11508000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 16275500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.068734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.167832 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.167832 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33907.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33907.291667 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits +system.cpu.dcache.overall_hits::total 2380 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses +system.cpu.dcache.overall_misses::total 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -397,32 +435,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 338 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.047028 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.049650 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.049650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use @@ -430,31 +474,64 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 221.521956 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006760 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 424 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # 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number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini index 8bad8df13..9563d85bf 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=MipsTLB size=64 +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout index 4b9270f18..7716b33a4 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:47 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:41 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index 397c3f1f6..9ae16c4c6 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2913500 # Number of ticks simulated final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 231601 # Simulator instruction rate (inst/s) -host_tick_rate 115720913 # Simulator tick rate (ticks/s) -host_mem_usage 199128 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 1078442 # Simulator instruction rate (inst/s) +host_op_rate 1075012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 535874927 # Simulator tick rate (ticks/s) +host_mem_usage 200784 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27687 # Number of bytes read from this memory system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory system.physmem.bytes_written 3658 # Number of bytes written to this memory @@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 5828 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.committedInsts 5827 # Number of instructions committed +system.cpu.committedOps 5827 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses system.cpu.num_func_calls 194 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini index e5b4b16c8..da3c93787 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=MipsTLB size=64 +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout index f6eaf03f7..ac3ff100c 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:56 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:52 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt index 65d0aed82..8087912dc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000293 # Nu sim_ticks 292960 # Number of ticks simulated final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 55801 # Simulator instruction rate (inst/s) -host_tick_rate 2804966 # Simulator tick rate (ticks/s) -host_mem_usage 220172 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 71598 # Simulator instruction rate (inst/s) +host_op_rate 71583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3598224 # Simulator tick rate (ticks/s) +host_mem_usage 221836 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27687 # Number of bytes read from this memory system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory system.physmem.bytes_written 3658 # Number of bytes written to this memory @@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 292960 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.committedInsts 5827 # Number of instructions committed +system.cpu.committedOps 5827 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses system.cpu.num_func_calls 194 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index 36444e22d..3cd70d03a 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=MipsInterrupts + [system.cpu.itb] type=MipsTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index 7525d1ad5..29b03eaff 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:56:13 -gem5 started Jan 23 2012 04:23:52 +gem5 compiled Feb 11 2012 13:07:32 +gem5 started Feb 11 2012 13:54:50 gem5 executing on zizzer -command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 566ce19a4..5a0520753 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000032 # Nu sim_ticks 32088000 # Number of ticks simulated final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263412 # Simulator instruction rate (inst/s) -host_tick_rate 1449372115 # Simulator tick rate (ticks/s) -host_mem_usage 207940 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 603210 # Simulator instruction rate (inst/s) +host_op_rate 602100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3309896144 # Simulator tick rate (ticks/s) +host_mem_usage 209992 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated +sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28096 # Number of bytes read from this memory system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -40,7 +42,8 @@ system.cpu.workload.num_syscalls 8 # Nu system.cpu.numCycles 64176 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5827 # Number of instructions executed +system.cpu.committedInsts 5827 # Number of instructions committed +system.cpu.committedOps 5827 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses system.cpu.num_func_calls 194 # number of times a function call or return occured @@ -64,26 +67,39 @@ system.cpu.icache.total_refs 5526 # To system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits -system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits -system.cpu.icache.overall_hits 5526 # number of overall hits -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses -system.cpu.icache.overall_misses 303 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.051981 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.051981 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.051981 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55722.772277 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55722.772277 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits +system.cpu.icache.overall_hits::total 5526 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 303 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 303 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 303 # number of overall misses +system.cpu.icache.overall_misses::total 303 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16884000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16884000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16884000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16884000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16884000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -92,26 +108,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15975000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15975000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15975000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051981 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.051981 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.051981 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use @@ -119,32 +133,49 @@ system.cpu.dcache.total_refs 1951 # To system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.021352 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1951 # number of overall hits -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses -system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 4872000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits +system.cpu.dcache.overall_hits::total 1951 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4872000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4872000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2856000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2856000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -153,30 +184,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # 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number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 439 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 20176000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2652000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22828000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22828000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 388 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 439 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 301 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22828000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 303 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,30 +281,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index fb36c719f..eed88a81d 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -53,6 +60,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -70,6 +78,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -81,6 +90,7 @@ max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 +needsTSO=false numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 @@ -89,6 +99,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -126,20 +137,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -425,20 +429,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -446,6 +443,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=PowerInterrupts + [system.cpu.itb] type=PowerTLB size=64 @@ -461,20 +461,13 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 8cb241542..8e7d01159 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:58:39 -gem5 started Jan 23 2012 04:24:00 +gem5 compiled Feb 11 2012 13:07:55 +gem5 started Feb 11 2012 13:55:01 gem5 executing on zizzer -command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 5a2ad1a0a..7c789f568 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000011 # Nu sim_ticks 10910500 # Number of ticks simulated final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 80565 # Simulator instruction rate (inst/s) -host_tick_rate 151515044 # Simulator tick rate (ticks/s) -host_mem_usage 205800 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 114395 # Simulator instruction rate (inst/s) +host_op_rate 114354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 215042277 # Simulator tick rate (ticks/s) +host_mem_usage 207892 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated +sim_ops 5800 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28608 # Number of bytes read from this memory system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -255,6 +257,7 @@ system.cpu.iew.wb_rate 0.361058 # in system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted @@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle -system.cpu.commit.count 5800 # Number of instructions committed +system.cpu.commit.committedInsts 5800 # Number of instructions committed +system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 2008 # Number of memory references committed system.cpu.commit.loads 962 # Number of loads committed @@ -291,6 +295,7 @@ system.cpu.rob.rob_writes 20673 # Th system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated +system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads @@ -306,26 +311,39 @@ system.cpu.icache.total_refs 1291 # To system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 169.539680 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.082783 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1291 # number of ReadReq hits -system.cpu.icache.demand_hits 1291 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1291 # number of overall hits -system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses -system.cpu.icache.demand_misses 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.245470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.245470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.245470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 169.539680 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.082783 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.082783 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1291 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1291 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1291 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1291 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1291 # number of overall hits +system.cpu.icache.overall_hits::total 1291 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 420 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 420 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 420 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 420 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 420 # number of overall misses +system.cpu.icache.overall_misses::total 420 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15114500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15114500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15114500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15114500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15114500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15114500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1711 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1711 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1711 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1711 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1711 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.245470 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.245470 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.245470 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -334,27 +352,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.205143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.205143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.205143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12207500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12207500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12207500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12207500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12207500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12207500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34779.202279 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 66.296919 # Cycle average of tags in use @@ -362,32 +383,49 @@ system.cpu.dcache.total_refs 2156 # To system.cpu.dcache.sampled_refs 105 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 20.533333 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 66.296919 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.016186 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1428 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 728 # number of WriteReq hits -system.cpu.dcache.demand_hits 2156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2156 # number of overall hits -system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 318 # number of WriteReq misses -system.cpu.dcache.demand_misses 406 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2947000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 10802500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 13749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 13749500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1516 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.058047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.304015 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.158470 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.158470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 33865.763547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 33865.763547 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 66.296919 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.016186 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.016186 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1428 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1428 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 728 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 728 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits +system.cpu.dcache.overall_hits::total 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 88 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 406 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 406 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 406 # number of overall misses +system.cpu.dcache.overall_misses::total 406 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2947000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2947000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10802500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10802500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13749500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1516 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2562 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2562 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2562 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2562 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058047 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304015 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.158470 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33488.636364 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.125786 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,32 +434,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 31 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 270 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 301 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 57 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 105 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 105 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 1963500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 1751000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 3714500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 3714500 # 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number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 31 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 270 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 270 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 57 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 57 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 105 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 105 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 105 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1963500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3714500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3714500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3714500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.037599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.040984 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34447.368421 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36479.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35376.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 200.613051 # Cycle average of tags in use @@ -429,31 +473,67 @@ system.cpu.l2cache.total_refs 9 # To system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.022556 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 200.613051 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.006122 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 9 # number of ReadReq hits -system.cpu.l2cache.demand_hits 9 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 9 # number of overall hits -system.cpu.l2cache.ReadReq_misses 399 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 48 # 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miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.980263 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34435.123043 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34435.123043 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 168.132824 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.480228 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005131 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000991 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006122 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 7 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 2 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3574000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15392500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 57 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980057 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980057 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980057 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.104651 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34463.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34968.750000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,30 +542,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 399 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 447 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12434000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.977941 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.980263 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.980263 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10708500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1725500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12434000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10708500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3251500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13960000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10708500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3251500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini index f4325cdae..252e46831 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,17 +30,19 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload UnifiedTLB=true checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -41,6 +50,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -55,6 +65,9 @@ icache_port=system.membus.port[2] type=PowerTLB size=64 +[system.cpu.interrupts] +type=PowerInterrupts + [system.cpu.itb] type=PowerTLB size=64 diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout index ef2f9ace6..2b3bb9fb6 100755 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 03:58:39 -gem5 started Jan 23 2012 04:24:03 +gem5 compiled Feb 11 2012 13:07:55 +gem5 started Feb 11 2012 13:55:02 gem5 executing on zizzer -command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index 5070ee2a1..5d83b2bac 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2900000 # Number of ticks simulated final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 305071 # Simulator instruction rate (inst/s) -host_tick_rate 152367478 # Simulator tick rate (ticks/s) -host_mem_usage 196296 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 430782 # Simulator instruction rate (inst/s) +host_op_rate 430227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 214814147 # Simulator tick rate (ticks/s) +host_mem_usage 197864 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5801 # Number of instructions simulated +sim_ops 5801 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26925 # Number of bytes read from this memory system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory system.physmem.bytes_written 4209 # Number of bytes written to this memory @@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls 9 # Nu system.cpu.numCycles 5801 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5801 # Number of instructions executed +system.cpu.committedInsts 5801 # Number of instructions committed +system.cpu.committedOps 5801 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses system.cpu.num_func_calls 200 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 32a7f4ad9..eed996339 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=InOrderCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 RASSize=16 @@ -45,6 +52,7 @@ div32RepeatRate=1 div8Latency=1 div8RepeatRate=1 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchBuffSize=4 @@ -57,6 +65,7 @@ globalCtrBits=2 globalHistoryBits=13 globalPredictorSize=8192 instShiftAmt=2 +interrupts=system.cpu.interrupts itb=system.cpu.itb localCtrBits=2 localHistoryBits=11 @@ -72,6 +81,7 @@ multRepeatRate=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 stageTracing=false stageWidth=4 @@ -93,20 +103,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -129,20 +132,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -150,6 +146,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -165,20 +164,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 024efc4d5..13c85267e 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:09 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:12 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 18201500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 1ce5039d0..99d0ed042 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000018 # Nu sim_ticks 18201500 # Number of ticks simulated final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29731 # Simulator instruction rate (inst/s) -host_tick_rate 101330259 # Simulator tick rate (ticks/s) -host_mem_usage 213072 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 71915 # Simulator instruction rate (inst/s) +host_op_rate 71898 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 245008016 # Simulator tick rate (ticks/s) +host_mem_usage 211144 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27072 # Number of bytes read from this memory system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -36,9 +38,10 @@ system.cpu.comNops 173 # Nu system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed system.cpu.comInts 2537 # Number of Integer instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread) +system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) +system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) +system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads @@ -92,26 +95,39 @@ system.cpu.icache.total_refs 791 # To system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits -system.cpu.icache.demand_hits 791 # number of demand (read+write) hits -system.cpu.icache.overall_hits 791 # number of overall hits -system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses -system.cpu.icache.demand_misses 347 # number of demand (read+write) misses -system.cpu.icache.overall_misses 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits +system.cpu.icache.overall_hits::total 791 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses +system.cpu.icache.overall_misses::total 347 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -120,27 +136,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use @@ -148,32 +167,49 @@ system.cpu.dcache.total_refs 1049 # To system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.859932 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020229 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 392 # number of WriteReq hits -system.cpu.dcache.demand_hits 1049 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1049 # number of overall hits -system.cpu.dcache.ReadReq_misses 59 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 281 # number of WriteReq misses -system.cpu.dcache.demand_misses 340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3290500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 15457500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 18748000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.082402 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.417533 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.244780 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55141.176471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55141.176471 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 82.859932 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 392 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1049 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1049 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1049 # number of overall hits +system.cpu.dcache.overall_hits::total 1049 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 281 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 281 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 340 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses +system.cpu.dcache.overall_misses::total 340 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3290500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3290500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15457500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15457500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18748000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18748000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18748000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,32 +218,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 200 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits 205 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 205 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7192500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 200 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 200 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 205 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 205 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 205 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2865500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2865500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7192500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7192500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use @@ -215,31 +257,67 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 162.297266 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004953 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 342 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 423 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 17918500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 22149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 22149000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 345 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.991304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.992958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52361.702128 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52361.702128 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 136.185515 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.111751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 423 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15132500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15132500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7016500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22149000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15132500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7016500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22149000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -248,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 342 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 423 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 13747000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3255500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 17002500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 17002500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.991304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.992958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini index 8aa4dc707..328fede16 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -54,6 +64,9 @@ icache_port=system.membus.port[2] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout index 9cbff76e8..51b7334cc 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:11 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:13 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 2701000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 57eaeacb0..12998e98f 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000003 # Nu sim_ticks 2701000 # Number of ticks simulated final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117056 # Simulator instruction rate (inst/s) -host_tick_rate 59184907 # Simulator tick rate (ticks/s) -host_mem_usage 203964 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 963329 # Simulator instruction rate (inst/s) +host_op_rate 960313 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484321069 # Simulator tick rate (ticks/s) +host_mem_usage 201636 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26135 # Number of bytes read from this memory system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory system.physmem.bytes_written 5065 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 5403 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.committedInsts 5340 # Number of instructions committed +system.cpu.committedOps 5340 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 146 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini index e13b78d74..bca11e4c0 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0] type=SparcTLB size=64 +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -131,6 +144,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout index 8b55b99bf..f70d252d3 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:20 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:24 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 253364 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt index 5fbe4680b..a13bd4161 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000253 # Nu sim_ticks 253364 # Number of ticks simulated final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 57666 # Simulator instruction rate (inst/s) -host_tick_rate 2735530 # Simulator tick rate (ticks/s) -host_mem_usage 224736 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 70723 # Simulator instruction rate (inst/s) +host_op_rate 70707 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3354080 # Simulator tick rate (ticks/s) +host_mem_usage 222404 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 26135 # Number of bytes read from this memory system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory system.physmem.bytes_written 5065 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 253364 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.committedInsts 5340 # Number of instructions committed +system.cpu.committedOps 5340 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 146 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 31f964ca0..a61827466 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -94,20 +97,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,6 +111,9 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=SparcInterrupts + [system.cpu.itb] type=SparcTLB size=64 @@ -130,20 +129,13 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index a3d57b80d..5f1c3c546 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:02:00 -gem5 started Jan 23 2012 04:24:14 +gem5 compiled Feb 11 2012 13:08:33 +gem5 started Feb 11 2012 13:55:23 gem5 executing on zizzer -command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello World!Exiting @ tick 28206000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 0e1d1294b..e8bbbf4c9 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000028 # Nu sim_ticks 28206000 # Number of ticks simulated final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103151 # Simulator instruction rate (inst/s) -host_tick_rate 544654705 # Simulator tick rate (ticks/s) -host_mem_usage 212680 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 534426 # Simulator instruction rate (inst/s) +host_op_rate 533460 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2812998715 # Simulator tick rate (ticks/s) +host_mem_usage 210748 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated +sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 24896 # Number of bytes read from this memory system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 56412 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 5340 # Number of instructions executed +system.cpu.committedInsts 5340 # Number of instructions committed +system.cpu.committedOps 5340 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 146 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 5127 # To system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 116.975932 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.057117 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits -system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits -system.cpu.icache.overall_hits 5127 # number of overall hits -system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses -system.cpu.icache.demand_misses 257 # number of demand (read+write) misses -system.cpu.icache.overall_misses 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits +system.cpu.icache.overall_hits::total 5127 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses +system.cpu.icache.overall_misses::total 257 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047734 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 1254 # To system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 82.065697 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020036 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 662 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 592 # number of WriteReq hits -system.cpu.dcache.demand_hits 1254 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1254 # number of overall hits -system.cpu.dcache.ReadReq_misses 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses -system.cpu.dcache.demand_misses 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 2982000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4536000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7518000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7518000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.075419 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.097192 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.097192 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 55688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 55688.888889 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1254 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1254 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1254 # number of overall hits +system.cpu.dcache.overall_hits::total 1254 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2982000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2982000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4536000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4536000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7518000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7518000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7518000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7518000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075419 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097192 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097192 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.075419 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use @@ -166,31 +197,67 @@ system.cpu.l2cache.total_refs 3 # To system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 142.102892 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004337 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses 308 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 81 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 389 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 20228000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 311 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 392 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.990354 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.992347 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 3 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 255 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 308 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 255 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 389 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 389 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 257 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 392 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 257 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 392 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992218 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992218 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,30 +266,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 15560000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.992347 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 255 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 308 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 255 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 8f8ece24e..7b5ea1d59 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,7 +30,7 @@ system_port=system.membus.port[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -52,6 +59,7 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb fetchToDecodeDelay=1 @@ -69,6 +77,7 @@ iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 +interrupts=system.cpu.interrupts issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -89,6 +98,7 @@ numRobs=1 numThreads=1 phase=0 predType=tournament +profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 @@ -126,20 +136,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -149,7 +152,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.fuPool] type=FUPool @@ -425,20 +435,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=20 trace_addr=0 two_queue=false @@ -446,9 +449,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -461,25 +480,18 @@ is_top_level=false latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -490,7 +502,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -503,7 +515,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -522,7 +534,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index b49f2b572..ac1cd3610 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,12 +1,10 @@ -Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 28 2012 12:11:40 -gem5 started Jan 28 2012 12:11:57 -gem5 executing on ribera.cs.wisc.edu -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:05 +gem5 executing on zizzer +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 8477728c8..658a056fb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000012 # Nu sim_ticks 11989500 # Number of ticks simulated final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1330 # Simulator instruction rate (inst/s) -host_tick_rate 1625690 # Simulator tick rate (ticks/s) -host_mem_usage 239860 # Number of bytes of host memory used -host_seconds 7.38 # Real time elapsed on the host -sim_insts 9809 # Number of instructions simulated +host_inst_rate 61798 # Simulator instruction rate (inst/s) +host_op_rate 111900 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 136747555 # Simulator tick rate (ticks/s) +host_mem_usage 218292 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 5416 # Number of instructions simulated +sim_ops 9809 # Number of ops (including micro ops) simulated system.physmem.bytes_read 28288 # Number of bytes read from this memory system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized 0 # nu system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions +system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions +system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted @@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100. system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle -system.cpu.commit.count 9809 # Number of instructions committed +system.cpu.commit.committedInsts 5416 # Number of instructions committed +system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1990 # Number of memory references committed system.cpu.commit.loads 1056 # Number of loads committed @@ -271,12 +275,13 @@ system.cpu.rob.rob_reads 34653 # Th system.cpu.rob.rob_writes 42403 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 9809 # Number of Instructions Simulated -system.cpu.committedInsts_total 9809 # Number of Instructions Simulated -system.cpu.cpi 2.444694 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.444694 # CPI: Total CPI of All Threads -system.cpu.ipc 0.409049 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.409049 # IPC: Total IPC of All Threads +system.cpu.committedInsts 5416 # Number of Instructions Simulated +system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 5416 # Number of Instructions Simulated +system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads +system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 23430 # number of integer regfile reads system.cpu.int_regfile_writes 14518 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -287,26 +292,39 @@ system.cpu.icache.total_refs 1498 # To system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 140.870525 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.068784 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 1498 # number of ReadReq hits -system.cpu.icache.demand_hits 1498 # number of demand (read+write) hits -system.cpu.icache.overall_hits 1498 # number of overall hits -system.cpu.icache.ReadReq_misses 368 # number of ReadReq misses -system.cpu.icache.demand_misses 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 13394000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 13394000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 1866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 1866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.197213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.197213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.197213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 36396.739130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 36396.739130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 36396.739130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits +system.cpu.icache.overall_hits::total 1498 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses +system.cpu.icache.overall_misses::total 368 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,27 +333,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 10471500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.159700 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.159700 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.159700 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35139.261745 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use @@ -343,32 +364,49 @@ system.cpu.dcache.total_refs 2275 # To system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 83.526549 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1417 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 858 # number of WriteReq hits -system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses 111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 76 # number of WriteReq misses -system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 187 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3859500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 2916500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 6776000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 2462 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 2462 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.072644 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.075955 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.075955 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 34770.270270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 38375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 36235.294118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 36235.294118 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 83.526549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020392 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020392 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1417 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1417 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits +system.cpu.dcache.overall_hits::total 2275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 187 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 187 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 187 # number of overall misses +system.cpu.dcache.overall_misses::total 187 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3859500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3859500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2916500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2916500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6776000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6776000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6776000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6776000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2462 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2462 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2462 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2462 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.072644 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.075955 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075955 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38375 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,31 +415,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 41 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 41 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 70 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.045812 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.059301 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.059301 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35185.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35375 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 35284.246575 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 41 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 41 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2463000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2463000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2688500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2688500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5151500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5151500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045812 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059301 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35185.714286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35375 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35284.246575 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 173.809724 # Cycle average of tags in use @@ -409,31 +452,64 @@ system.cpu.l2cache.total_refs 2 # To system.cpu.l2cache.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005479 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 173.809724 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.005304 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses 366 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 76 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 442 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 442 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 12541000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 2603000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 15144000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 15144000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 368 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 76 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 444 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 444 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.994565 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.995495 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.995495 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 34265.027322 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 34262.443439 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 34262.443439 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 140.468506 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.341218 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004287 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001017 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005304 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 296 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 70 # 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number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2603000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4986000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15144000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4986000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15144000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 368 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 76 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 76 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 444 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 444 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993289 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993289 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993289 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -442,30 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 366 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 76 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 442 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 442 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11369000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2368500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 13737500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 13737500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994565 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.995495 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.995495 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31062.841530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.473684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 70 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 76 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 442 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 442 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9202000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2167000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11369000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2368500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2368500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9202000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4535500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9202000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4535500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13737500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini index e5a1ce348..8e464f4fc 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=AtomicSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false @@ -52,11 +62,34 @@ icache_port=system.membus.port[2] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[5] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[7] +pio=system.membus.port[6] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.membus.port[4] [system.cpu.tracer] type=ExeTracer @@ -88,7 +121,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port +port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout index de652c174..51c6cbf48 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:38 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:16 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index e2f539833..d15c91451 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000006 # Nu sim_ticks 5651000 # Number of ticks simulated final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225004 # Simulator instruction rate (inst/s) -host_tick_rate 129531520 # Simulator tick rate (ticks/s) -host_mem_usage 202604 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host -sim_insts 9810 # Number of instructions simulated +host_inst_rate 364793 # Simulator instruction rate (inst/s) +host_op_rate 659825 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379660541 # Simulator tick rate (ticks/s) +host_mem_usage 207748 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5417 # Number of instructions simulated +sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62348 # Number of bytes read from this memory system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory system.physmem.bytes_written 7110 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 11303 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.committedInsts 5417 # Number of instructions committed +system.cpu.committedOps 9810 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini index 3ef5774b9..95be41a11 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000 time_sync_spin_threshold=100000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000 [system] type=System children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=timing memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0] [system.cpu] type=TimingSimpleCPU -children=dtb itb tracer workload +children=dtb interrupts itb tracer workload checker=Null clock=1 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -49,11 +59,34 @@ icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.port[3] + +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_port=system.l1_cntrl0.sequencer.port[5] +pio=system.l1_cntrl0.sequencer.port[4] [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.port[2] [system.cpu.tracer] type=ExeTracer @@ -131,6 +164,7 @@ issue_latency=2 number_of_TBEs=256 recycle_latency=10 ruby_system=system.ruby +send_evictions=false sequencer=system.l1_cntrl0.sequencer transitions_per_cycle=32 version=0 @@ -157,7 +191,7 @@ using_network_tester=false using_ruby_tester=false version=0 physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port +port=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout index 9c1cf6357..f8a22f9ca 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:43 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:37 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt index 49089d227..31a5db86e 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000276 # Nu sim_ticks 276484 # Number of ticks simulated final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 88128 # Simulator instruction rate (inst/s) -host_tick_rate 2483404 # Simulator tick rate (ticks/s) -host_mem_usage 223444 # Number of bytes of host memory used +host_inst_rate 47191 # Simulator instruction rate (inst/s) +host_op_rate 85448 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2407911 # Simulator tick rate (ticks/s) +host_mem_usage 228676 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host -sim_insts 9810 # Number of instructions simulated +sim_insts 5417 # Number of instructions simulated +sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 62348 # Number of bytes read from this memory system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory system.physmem.bytes_written 7110 # Number of bytes written to this memory @@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 276484 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.committedInsts 5417 # Number of instructions committed +system.cpu.committedOps 9810 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 36b722b34..7bd202ff4 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -1,6 +1,7 @@ [root] type=Root children=system +full_system=false time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000 [system] type=System children=cpu membus physmem +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 mem_mode=atomic memories=system.physmem num_work_ids=16 physmem=system.physmem +readfile= +symbolfile= work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -23,16 +30,18 @@ system_port=system.membus.port[0] [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache itb l2cache toL2Bus tracer workload +children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload checker=Null clock=500 cpu_id=0 defer_registration=false do_checkpoint_insts=true +do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb function_trace=false function_trace_start=0 +interrupts=system.cpu.interrupts itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -40,6 +49,7 @@ max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 phase=0 +profile=0 progress_interval=0 system=system tracer=system.cpu.tracer @@ -58,20 +68,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=262144 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1] [system.cpu.dtb] type=X86TLB +children=walker size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[3] [system.cpu.icache] type=BaseCache @@ -94,20 +104,13 @@ is_top_level=true latency=1000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=131072 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false @@ -115,9 +118,25 @@ write_buffers=8 cpu_side=system.cpu.icache_port mem_side=system.cpu.toL2Bus.port[0] +[system.cpu.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_port=system.membus.port[4] +pio=system.membus.port[3] + [system.cpu.itb] type=X86TLB +children=walker size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +system=system +port=system.cpu.toL2Bus.port[2] [system.cpu.l2cache] type=BaseCache @@ -130,25 +149,18 @@ is_top_level=false latency=10000 max_miss_count=0 mshrs=10 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 +prefetcher=Null prioritizeRequests=false repl=Null size=2097152 subblock_size=0 +system=system tgts_per_mshr=5 trace_addr=0 two_queue=false write_buffers=8 -cpu_side=system.cpu.toL2Bus.port[2] +cpu_side=system.cpu.toL2Bus.port[4] mem_side=system.membus.port[2] [system.cpu.toL2Bus] @@ -159,7 +171,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side +port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side [system.cpu.tracer] type=ExeTracer @@ -191,7 +203,7 @@ clock=1000 header_cycles=1 use_default_range=false width=64 -port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side +port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port [system.physmem] type=PhysicalMemory diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 074c5468c..89203c6bc 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2012 04:08:34 -gem5 started Jan 23 2012 04:24:38 +gem5 compiled Feb 11 2012 13:08:53 +gem5 started Feb 11 2012 14:04:26 gem5 executing on zizzer -command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index dcf7af574..c2e4355d3 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,11 +4,13 @@ sim_seconds 0.000029 # Nu sim_ticks 28768000 # Number of ticks simulated final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320748 # Simulator instruction rate (inst/s) -host_tick_rate 940055576 # Simulator tick rate (ticks/s) -host_mem_usage 211332 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host -sim_insts 9810 # Number of instructions simulated +host_inst_rate 265683 # Simulator instruction rate (inst/s) +host_op_rate 480724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1408532008 # Simulator tick rate (ticks/s) +host_mem_usage 216996 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5417 # Number of instructions simulated +sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read 23104 # Number of bytes read from this memory system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory @@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls 11 # Nu system.cpu.numCycles 57536 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.num_insts 9810 # Number of instructions executed +system.cpu.committedInsts 5417 # Number of instructions committed +system.cpu.committedOps 9810 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_func_calls 0 # number of times a function call or return occured @@ -46,26 +49,39 @@ system.cpu.icache.total_refs 6683 # To system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits -system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits -system.cpu.icache.overall_hits 6683 # number of overall hits -system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses -system.cpu.icache.demand_misses 228 # number of demand (read+write) misses -system.cpu.icache.overall_misses 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits +system.cpu.icache.overall_hits::total 6683 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses +system.cpu.icache.overall_misses::total 228 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 228 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 228 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.032991 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate 0.032991 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate 0.032991 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 228 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 228 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 228 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032991 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use @@ -101,32 +115,49 @@ system.cpu.dcache.total_refs 1856 # To system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.019695 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits 1001 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits -system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits -system.cpu.dcache.overall_hits 1856 # number of overall hits -system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses -system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate 0.052083 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency +system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 855 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1856 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1856 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1856 # number of overall hits +system.cpu.dcache.overall_hits::total 1856 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.dcache.overall_misses::total 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3080000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3080000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4424000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7504000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7504000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7504000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1056 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1056 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1990 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1990 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1990 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1990 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052083 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084582 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067337 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067337 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -135,30 +166,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.052083 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084582 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067337 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use @@ -166,31 +197,64 @@ system.cpu.l2cache.total_refs 1 # To system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context -system.cpu.l2cache.occ_percent::0 0.004084 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses 282 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses 79 # number of ReadExReq misses -system.cpu.l2cache.demand_misses 361 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency 18772000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses 283 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses 79 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses 362 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate 0.996466 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate 0.997238 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency +system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits +system.cpu.l2cache.overall_hits::total 1 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 227 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 282 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 227 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 361 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.l2cache.overall_misses::total 361 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 228 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 134 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 362 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 228 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 134 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 362 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995614 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995614 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -199,30 +263,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses 79 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses 361 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses 361 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency 14440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency 14440000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |