diff options
Diffstat (limited to 'tests/quick/se/00.hello/ref')
18 files changed, 5458 insertions, 5469 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index eedb7e6a0..f228f639d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 34993500 # Number of ticks simulated -final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000038 # Number of seconds simulated +sim_ticks 37928000 # Number of ticks simulated +final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25302 # Simulator instruction rate (inst/s) -host_op_rate 25300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138325772 # Simulator tick rate (ticks/s) -host_mem_usage 279800 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 174102 # Simulator instruction rate (inst/s) +host_op_rate 174036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1031016392 # Simulator tick rate (ticks/s) +host_mem_usage 293404 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34895000 # Total gap between requests +system.physmem.totGap 37822500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3849750 # Total ticks spent queuing -system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 3251500 # Total ticks spent queuing +system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.03 # Data bus utilization in percentage +system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 435 # Number of row buffer hits during reads +system.physmem.readRowHits 437 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65469.04 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 70961.54 # Average gap between requests +system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) -system.physmem_0.averagePower 827.438306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) +system.physmem_0.averagePower 825.080242 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) -system.physmem_1.averagePower 815.785757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) +system.physmem_1.averagePower 809.305525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1972 # Number of BP lookups -system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1968 # Number of BP lookups +system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups system.cpu.branchPred.BTBHits 385 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2254 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2268 # DTB accesses -system.cpu.itb.fetch_hits 2642 # ITB hits +system.cpu.itb.fetch_hits 2639 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2659 # ITB accesses +system.cpu.itb.fetch_accesses 2656 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 69987 # number of cpu cycles simulated +system.cpu.numCycles 75856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.935469 # CPI: cycles per instruction -system.cpu.ipc 0.091446 # IPC: instructions per cycle -system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.852500 # CPI: cycles per instruction +system.cpu.ipc 0.084370 # IPC: instructions per cycle +system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits -system.cpu.dcache.overall_hits::total 1973 # number of overall hits +system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits +system.cpu.dcache.overall_hits::total 1975 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16373500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses +system.cpu.dcache.overall_misses::total 226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5649 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits -system.cpu.icache.overall_hits::total 2277 # number of overall hits +system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5643 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits +system.cpu.icache.overall_hits::total 2274 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.091079 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.671740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -534,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7033500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24623500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12077500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24623500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12077500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) @@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67646.978022 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73265.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,17 +597,17 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20056500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5835000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20056500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9973000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -654,10 +654,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution @@ -678,9 +678,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.2 # Layer utilization (%) +system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7064bc28f..edf4ba710 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20537500 # Number of ticks simulated -final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22074000 # Number of ticks simulated +final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92569 # Simulator instruction rate (inst/s) -host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 298254404 # Simulator tick rate (ticks/s) -host_mem_usage 293992 # Number of bytes of host memory used +host_inst_rate 94896 # Simulator instruction rate (inst/s) +host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 328609283 # Simulator tick rate (ticks/s) +host_mem_usage 293652 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Number of read requests accepted +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::6 1 # Pe system.physmem.perBankRdBursts::7 3 # Per bank write bursts system.physmem.perBankRdBursts::8 0 # Per bank write bursts system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts system.physmem.perBankRdBursts::13 120 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20412000 # Total gap between requests +system.physmem.totGap 21941500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 487 # Read request sizes (log2) +system.physmem.readPktSize::6 486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 4742750 # Total ticks spent queuing -system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation +system.physmem.totQLat 4363750 # Total ticks spent queuing +system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.86 # Data bus utilization in percentage -system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.01 # Data bus utilization in percentage +system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 390 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41913.76 # Average gap between requests -system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 45147.12 # Average gap between requests +system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) -system.physmem_0.averagePower 881.195525 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) +system.physmem_0.averagePower 873.750829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) -system.physmem_1.averagePower 864.696352 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) +system.physmem_1.averagePower 853.818096 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2806 # Number of BP lookups -system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2808 # Number of BP lookups +system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 686 # Number of BTB hits +system.cpu.branchPred.BTBHits 676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2085 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 2105 # DTB read hits +system.cpu.dtb.read_misses 56 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2140 # DTB read accesses -system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.read_accesses 2161 # DTB read accesses +system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1099 # DTB write accesses -system.cpu.dtb.data_hits 3154 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1104 # DTB write accesses +system.cpu.dtb.data_hits 3179 # DTB hits +system.cpu.dtb.data_misses 86 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3239 # DTB accesses -system.cpu.itb.fetch_hits 2196 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3265 # DTB accesses +system.cpu.itb.fetch_hits 2195 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2234 # ITB accesses +system.cpu.itb.fetch_accesses 2229 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41076 # number of cpu cycles simulated +system.cpu.numCycles 44149 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2413 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode +system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups +system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10718 # Type of FU issued -system.cpu.iq.rate 0.260931 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10742 # Type of FU issued +system.cpu.iq.rate 0.243312 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19169 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions +system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed +system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3244 # number of memory reference insts executed -system.cpu.iew.exec_branches 1603 # Number of branches executed -system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.248904 # Inst execution rate -system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5300 # num instructions producing a value -system.cpu.iew.wb_consumers 7279 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3270 # number of memory reference insts executed +system.cpu.iew.exec_branches 1599 # Number of branches executed +system.cpu.iew.exec_stores 1106 # Number of stores executed +system.cpu.iew.exec_rate 0.232123 # Inst execution rate +system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9797 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5308 # num instructions producing a value +system.cpu.iew.wb_consumers 7306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back +system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,187 +568,187 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25507 # The number of ROB reads -system.cpu.rob.rob_writes 27214 # The number of ROB writes -system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25491 # The number of ROB reads +system.cpu.rob.rob_writes 27316 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12992 # number of integer regfile reads -system.cpu.int_regfile_writes 7455 # number of integer regfile writes +system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13019 # number of integer regfile reads +system.cpu.int_regfile_writes 7461 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits +system.cpu.dcache.overall_hits::total 2347 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4706 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits -system.cpu.icache.overall_hits::total 1718 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses -system.cpu.icache.overall_misses::total 478 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4704 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits +system.cpu.icache.overall_hits::total 1716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses +system.cpu.icache.overall_misses::total 479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.218223 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71122.129436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71122.129436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,54 +757,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22315500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22315500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142987 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142987 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24276250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24276250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24276250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24276250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24276250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24276250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143052 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143052 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77312.898089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77312.898089 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.773509 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.195035 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.460945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.471795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60.723240 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4391 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4391 # Number of data accesses +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4382 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4382 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -813,60 +812,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 487 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21990500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7915750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29906250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5408750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5408750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21990500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13324500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses +system.cpu.l2cache.overall_misses::total 486 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8448250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 32399000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5570250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5570250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37969250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14018500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37969250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70257.188498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72515.400411 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72515.400411 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76519.968051 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83646.039604 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.454106 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77364.583333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77364.583333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78126.028807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78126.028807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -876,100 +875,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18043000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20032750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7188250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 27221000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11862500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31895250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20032750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11862500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31895250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadReq 414 # Transaction distribution +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::samples 486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) +system.membus.snoop_fanout::total 486 # Request fanout histogram +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index dcfebc3a2..95d6f5391 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544000 # Number of ticks simulated -final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32544500 # Number of ticks simulated +final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 485157 # Simulator instruction rate (inst/s) -host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2465828156 # Simulator tick rate (ticks/s) -host_mem_usage 286540 # Number of bytes of host memory used +host_inst_rate 643051 # Simulator instruction rate (inst/s) +host_op_rate 642147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3266208350 # Simulator tick rate (ticks/s) +host_mem_usage 291356 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 373 # Transaction distribution -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65088 # number of cpu cycles simulated +system.cpu.numCycles 65089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65088 # Number of busy cycles +system.cpu.num_busy_cycles 65089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits +system.cpu.dcache.overall_hits::total 1880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy @@ -262,17 +343,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) @@ -295,17 +376,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -325,17 +406,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses @@ -347,122 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits -system.cpu.dcache.overall_hits::total 1880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -491,5 +468,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 373 # Transaction distribution +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram +system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 6a0f7583b..a634edee1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18733500 # Number of ticks simulated -final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20287000 # Number of ticks simulated +final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33056 # Simulator instruction rate (inst/s) -host_op_rate 33048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 239448729 # Simulator tick rate (ticks/s) -host_mem_usage 278492 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 136939 # Simulator instruction rate (inst/s) +host_op_rate 136838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1073215892 # Simulator tick rate (ticks/s) +host_mem_usage 292092 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 761843756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761843756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 290388876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18651500 # Total gap between requests +system.physmem.totGap 20198000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1952250 # Total ticks spent queuing -system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation +system.physmem.totQLat 1763250 # Total ticks spent queuing +system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.22 # Data bus utilization in percentage -system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.59 # Data bus utilization in percentage +system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 257 # Number of row buffer hits during reads +system.physmem.readRowHits 258 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 60556.82 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined +system.physmem.avgGap 65577.92 # Average gap between requests +system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) -system.physmem_0.averagePower 806.306964 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ) +system.physmem_0.averagePower 803.504500 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) -system.physmem_1.averagePower 848.926575 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ) +system.physmem_1.averagePower 838.851326 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.lookups 791 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 974 # ITB hits +system.cpu.itb.fetch_hits 969 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 987 # ITB accesses +system.cpu.itb.fetch_accesses 982 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,29 +293,29 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 37467 # number of cpu cycles simulated +system.cpu.numCycles 40574 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.494004 # CPI: cycles per instruction -system.cpu.ipc 0.068994 # IPC: instructions per cycle -system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked -system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.695938 # CPI: cycles per instruction +system.cpu.ipc 0.063711 # IPC: instructions per cycle +system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.478730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011836 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses @@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4644500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3502000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8146500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6389750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2171 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits -system.cpu.icache.overall_hits::total 751 # number of overall hits +system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2161 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits +system.cpu.icache.overall_hits::total 746 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228953 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses @@ -528,17 +528,17 @@ system.cpu.l2cache.demand_misses::total 308 # nu system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14661500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4251500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # 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number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,17 +591,17 @@ system.cpu.l2cache.demand_mshr_misses::total 308 system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -613,17 +613,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -649,9 +649,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -672,9 +672,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 15.3 # Layer utilization (%) +system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 49b58755c..165a7d5f5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11765500 # Number of ticks simulated -final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12774000 # Number of ticks simulated +final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73154 # Simulator instruction rate (inst/s) -host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360297045 # Simulator tick rate (ticks/s) -host_mem_usage 293708 # Number of bytes of host memory used +host_inst_rate 77109 # Simulator instruction rate (inst/s) +host_op_rate 77075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412290611 # Simulator tick rate (ticks/s) +host_mem_usage 293132 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1017211338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462368790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1479580128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1017211338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462368790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1479580128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11676000 # Total gap between requests +system.physmem.totGap 12677500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.076923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 220.895953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 363.044972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7 17.95% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 7.69% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.69% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.13% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 7.69% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation -system.physmem.totQLat 1802000 # Total ticks spent queuing -system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation +system.physmem.totQLat 1960500 # Total ticks spent queuing +system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.56 # Data bus utilization in percentage -system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.65 # Data bus utilization in percentage +system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 223 # Number of row buffer hits during reads +system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42926.47 # Average gap between requests -system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) -system.physmem_0.averagePower 838.417275 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) +system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) -system.physmem_1.averagePower 879.072239 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) +system.physmem_1.averagePower 865.181917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1090 # Number of BP lookups -system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 202 # Number of BTB hits +system.cpu.branchPred.lookups 1106 # Number of BP lookups +system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 214 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 689 # DTB read hits -system.cpu.dtb.read_misses 23 # DTB read misses +system.cpu.dtb.read_hits 705 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 712 # DTB read accesses -system.cpu.dtb.write_hits 352 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 730 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 370 # DTB write accesses -system.cpu.dtb.data_hits 1041 # DTB hits -system.cpu.dtb.data_misses 41 # DTB misses +system.cpu.dtb.write_accesses 386 # DTB write accesses +system.cpu.dtb.data_hits 1072 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1082 # DTB accesses -system.cpu.itb.fetch_hits 938 # ITB hits +system.cpu.dtb.data_accesses 1116 # DTB accesses +system.cpu.itb.fetch_hits 947 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 964 # ITB accesses +system.cpu.itb.fetch_accesses 973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23532 # number of cpu cycles simulated +system.cpu.numCycles 25549 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4442 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6549 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 938 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 155 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.330561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6093 84.50% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 49 0.68% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.71% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 84 1.16% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 131 1.82% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.80% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.93% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.86% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 544 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.046320 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.278302 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 757 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 975 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 55 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 180 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 156 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 995 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5674 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 452 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 30 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5438 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 960 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6138 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6131 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2145 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 115 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3891 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.539592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.280898 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5712 79.21% 79.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 492 6.82% 86.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 353 4.90% 90.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 253 3.51% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 197 2.73% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.68% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.72% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19 0.26% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2776 71.34% 71.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 739 18.99% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 375 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3891 # Type of FU issued -system.cpu.iq.rate 0.165349 # Inst issue rate -system.cpu.iq.fu_busy_cnt 51 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013107 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6745 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3580 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3966 # Type of FU issued +system.cpu.iq.rate 0.155231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 58 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6922 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3935 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 468 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 393 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5027 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 883 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 22 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 169 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 191 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 713 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 136 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 336 # number of nop insts executed -system.cpu.iew.exec_refs 1083 # number of memory reference insts executed -system.cpu.iew.exec_branches 638 # Number of branches executed -system.cpu.iew.exec_stores 370 # Number of stores executed -system.cpu.iew.exec_rate 0.159570 # Inst execution rate -system.cpu.iew.wb_sent 3650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3586 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1711 # num instructions producing a value -system.cpu.iew.wb_consumers 2190 # num instructions consuming a value +system.cpu.iew.exec_nop 340 # number of nop insts executed +system.cpu.iew.exec_refs 1117 # number of memory reference insts executed +system.cpu.iew.exec_branches 655 # Number of branches executed +system.cpu.iew.exec_stores 386 # Number of stores executed +system.cpu.iew.exec_rate 0.150495 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3676 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1745 # num instructions producing a value +system.cpu.iew.wb_consumers 2262 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152388 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.781279 # average fanout of values written-back +system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381234 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252230 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5909 87.45% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193 2.86% 90.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 297 4.40% 94.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 108 1.60% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.07% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.78% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.49% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.33% 98.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70 1.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,102 +568,102 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 70 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11453 # The number of ROB reads -system.cpu.rob.rob_writes 10498 # The number of ROB writes -system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11659 # The number of ROB reads +system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.858400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.858400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.101436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.101436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4543 # number of integer regfile reads -system.cpu.int_regfile_writes 2774 # number of integer regfile writes +system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads +system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4655 # number of integer regfile reads +system.cpu.int_regfile_writes 2832 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits +system.cpu.dcache.overall_hits::total 743 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -672,87 +672,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.663102 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 92.065177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044954 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 685 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 685 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 685 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 685 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 685 # number of overall hits -system.cpu.icache.overall_hits::total 685 # number of overall hits +system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2081 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits +system.cpu.icache.overall_hits::total 694 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17329249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17329249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17329249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17329249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 938 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 938 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.269723 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.269723 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.269723 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.269723 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68495.055336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68495.055336 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.267159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.267159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.267159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.267159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74762.841897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74762.841897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -768,39 +768,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12893999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12893999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14404999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14404999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 121.503793 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.236486 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.265551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.238242 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.076745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29.159741 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003700 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses @@ -815,17 +815,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14216750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4732500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18949250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14216750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6548500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14216750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6548500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20765250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -848,17 +848,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76025.401070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77581.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76408.266129 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76342.830882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76342.830882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -878,17 +878,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -900,17 +900,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution @@ -935,10 +935,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution @@ -959,9 +959,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 6695f502c..364bc6f05 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16524000 # Number of ticks simulated -final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16524500 # Number of ticks simulated +final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428144 # Simulator instruction rate (inst/s) -host_op_rate 427151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2733498759 # Simulator tick rate (ticks/s) -host_mem_usage 286260 # Number of bytes of host memory used +host_inst_rate 396950 # Simulator instruction rate (inst/s) +host_op_rate 396157 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2535599202 # Simulator tick rate (ticks/s) +host_mem_usage 290048 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 218 # Transaction distribution -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 13.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33048 # number of cpu cycles simulated +system.cpu.numCycles 33049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33048 # Number of busy cycles +system.cpu.num_busy_cycles 33049 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits +system.cpu.dcache.overall_hits::total 627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.dcache.overall_misses::total 82 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,34 +290,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id @@ -256,17 +337,17 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) @@ -289,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,17 +400,17 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -341,122 +422,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -485,5 +462,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 218 # Transaction distribution +system.membus.trans_dist::ReadResp 218 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 245 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 245 # Request fanout histogram +system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 452f74fef..a4c548b0e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27981000 # Number of ticks simulated -final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 30427500 # Number of ticks simulated +final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40383 # Simulator instruction rate (inst/s) -host_op_rate 47269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245344554 # Simulator tick rate (ticks/s) -host_mem_usage 297404 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 90683 # Simulator instruction rate (inst/s) +host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 599001910 # Simulator tick rate (ticks/s) +host_mem_usage 308040 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27895500 # Total gap between requests +system.physmem.totGap 30336000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,75 +187,76 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2478000 # Total ticks spent queuing -system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2605000 # Total ticks spent queuing +system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.52 # Data bus utilization in percentage -system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66260.10 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 72057.01 # Average gap between requests +system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.107753 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.018629 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) -system.physmem_1.averagePower 786.272135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.664197 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1926 # Number of BP lookups +system.cpu.branchPred.lookups 1927 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups system.cpu.branchPred.BTBHits 326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -376,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 55962 # number of cpu cycles simulated +system.cpu.numCycles 60855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4604 # Number of instructions committed system.cpu.committedOps 5390 # Number of ops (including micro ops) committed system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 12.155083 # CPI: cycles per instruction -system.cpu.ipc 0.082270 # IPC: instructions per cycle -system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.217854 # CPI: cycles per instruction +system.cpu.ipc 0.075655 # IPC: instructions per cycle +system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits -system.cpu.dcache.overall_hits::total 1900 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -422,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4804 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits -system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4806 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits +system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses @@ -628,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) @@ -661,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses @@ -719,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution @@ -743,25 +744,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 378 # Transaction distribution system.membus.trans_dist::ReadResp 378 # Transaction distribution @@ -782,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index bac015830..eb7b98cb0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16223000 # Number of ticks simulated -final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17307500 # Number of ticks simulated +final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54860 # Simulator instruction rate (inst/s) -host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193800024 # Simulator tick rate (ticks/s) -host_mem_usage 308908 # Number of bytes of host memory used +host_inst_rate 56147 # Simulator instruction rate (inst/s) +host_op_rate 65749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211593476 # Simulator tick rate (ticks/s) +host_mem_usage 308560 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16156000 # Total gap between requests +system.physmem.totGap 17240500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,76 +187,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3126000 # Total ticks spent queuing -system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3336500 # Total ticks spent queuing +system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.24 # Data bus utilization in percentage -system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.47 # Data bus utilization in percentage +system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40695.21 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43426.95 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) -system.physmem_0.averagePower 920.354334 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ) +system.physmem_0.averagePower 909.263856 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) -system.physmem_1.averagePower 810.522027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.611620 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2638 # Number of BP lookups -system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2634 # Number of BP lookups +system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 783 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups +system.cpu.branchPred.BTBHits 781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -495,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32447 # number of cpu cycles simulated +system.cpu.numCycles 34616 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2145 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2057 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 43 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4743 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available @@ -619,113 +620,113 @@ system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8358 # Type of FU issued -system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.FU_type_0::total 8345 # Type of FU issued +system.cpu.iq.rate 0.241073 # Inst issue rate system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3148 # number of memory reference insts executed -system.cpu.iew.exec_branches 1457 # Number of branches executed -system.cpu.iew.exec_stores 1240 # Number of stores executed -system.cpu.iew.exec_rate 0.248498 # Inst execution rate -system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7601 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3572 # num instructions producing a value -system.cpu.iew.wb_consumers 6998 # num instructions consuming a value +system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_branches 1452 # Number of branches executed +system.cpu.iew.exec_stores 1232 # Number of stores executed +system.cpu.iew.exec_rate 0.232465 # Inst execution rate +system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3567 # num instructions producing a value +system.cpu.iew.wb_consumers 6985 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -771,122 +772,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21720 # The number of ROB writes -system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22770 # The number of ROB reads +system.cpu.rob.rob_writes 21679 # The number of ROB writes +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7945 # number of integer regfile reads -system.cpu.int_regfile_writes 4420 # number of integer regfile writes -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.cc_regfile_reads 28734 # number of cc regfile reads -system.cpu.cc_regfile_writes 3302 # number of cc regfile writes -system.cpu.misc_regfile_reads 3189 # number of misc regfile reads +system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads +system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7923 # number of integer regfile reads +system.cpu.int_regfile_writes 4408 # number of integer regfile writes +system.cpu.fp_regfile_reads 32 # number of floating regfile reads +system.cpu.cc_regfile_reads 28677 # number of cc regfile reads +system.cpu.cc_regfile_writes 3298 # number of cc regfile writes +system.cpu.misc_regfile_reads 3185 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits +system.cpu.dcache.overall_hits::total 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,169 +896,169 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits -system.cpu.icache.overall_hits::total 1666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses -system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # 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average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76548.913043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79127.976190 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77150.694444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77414.800995 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77414.800995 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1105,50 +1106,50 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 79 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution @@ -1162,7 +1163,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram @@ -1170,21 +1171,17 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution @@ -1205,9 +1202,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 9157ec7b3..9add0d45b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16487000 # Number of ticks simulated -final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17911000 # Number of ticks simulated +final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33036 # Simulator instruction rate (inst/s) -host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118603969 # Simulator tick rate (ticks/s) -host_mem_usage 248576 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 61363 # Simulator instruction rate (inst/s) +host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 239307903 # Simulator tick rate (ticks/s) +host_mem_usage 305224 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 26048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408 # Number of read requests accepted +system.physmem.num_reads::total 406 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 88 # Per bank write bursts system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::3 44 # Per bank write bursts system.physmem.perBankRdBursts::4 18 # Per bank write bursts system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 37 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16473500 # Total gap between requests +system.physmem.totGap 17897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408 # Read request sizes (log2) +system.physmem.readPktSize::6 407 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,13 +94,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3192729 # Total ticks spent queuing -system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation +system.physmem.totQLat 3190492 # Total ticks spent queuing +system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.37 # Data bus utilization in percentage -system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.36 # Data bus utilization in percentage +system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40376.23 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43974.20 # Average gap between requests +system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) -system.physmem_0.averagePower 918.403600 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) +system.physmem_0.averagePower 903.874941 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) -system.physmem_1.averagePower 817.101847 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.131217 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2361 # Number of BP lookups -system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 473 # Number of BTB hits +system.cpu.branchPred.BTBHits 476 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32975 # number of cpu cycles simulated +system.cpu.numCycles 35823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 4080 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7157 # Type of FU issued -system.cpu.iq.rate 0.217043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7136 # Type of FU issued +system.cpu.iq.rate 0.199202 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11164 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2417 # number of memory reference insts executed -system.cpu.iew.exec_branches 1277 # Number of branches executed -system.cpu.iew.exec_stores 1017 # Number of stores executed -system.cpu.iew.exec_rate 0.205034 # Inst execution rate -system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6587 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2990 # num instructions producing a value -system.cpu.iew.wb_consumers 5391 # num instructions consuming a value +system.cpu.iew.exec_refs 2409 # number of memory reference insts executed +system.cpu.iew.exec_branches 1271 # Number of branches executed +system.cpu.iew.exec_stores 1015 # Number of stores executed +system.cpu.iew.exec_rate 0.188036 # Inst execution rate +system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2981 # num instructions producing a value +system.cpu.iew.wb_consumers 5387 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,122 +654,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22003 # The number of ROB reads -system.cpu.rob.rob_writes 16441 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22696 # The number of ROB reads +system.cpu.rob.rob_writes 16433 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6737 # number of integer regfile reads -system.cpu.int_regfile_writes 3765 # number of integer regfile writes +system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6713 # number of integer regfile reads +system.cpu.int_regfile_writes 3756 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24010 # number of cc regfile reads -system.cpu.cc_regfile_writes 2910 # number of cc regfile writes -system.cpu.misc_regfile_reads 2599 # number of misc regfile reads +system.cpu.cc_regfile_reads 23929 # number of cc regfile reads +system.cpu.cc_regfile_writes 2892 # number of cc regfile writes +system.cpu.misc_regfile_reads 2595 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits -system.cpu.dcache.overall_hits::total 1876 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses -system.cpu.dcache.overall_misses::total 369 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses +system.cpu.dcache.overall_misses::total 362 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -778,120 +778,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7990 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits -system.cpu.icache.overall_hits::total 3485 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # 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number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # 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Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # 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number of overall misses -system.cpu.l2cache.overall_misses::total 387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1005,118 +1005,116 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 67 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 64 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 378 # Transaction distribution -system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.membus.trans_dist::ReadResp 375 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::samples 407 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 408 # Request fanout histogram -system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 23.0 # Layer utilization (%) +system.membus.snoop_fanout::total 407 # Request fanout histogram +system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 72322cbec..cdd01be72 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 396323 # Simulator instruction rate (inst/s) -host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232084410 # Simulator tick rate (ticks/s) -host_mem_usage 298640 # Number of bytes of host memory used +host_inst_rate 771856 # Simulator instruction rate (inst/s) +host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 450886881 # Simulator tick rate (ticks/s) +host_mem_usage 297796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -347,18 +347,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b8c713e42..bd1ca933f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 370272 # Simulator instruction rate (inst/s) -host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216878622 # Simulator tick rate (ticks/s) -host_mem_usage 297624 # Number of bytes of host memory used +host_inst_rate 801222 # Simulator instruction rate (inst/s) +host_op_rate 936270 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 468120222 # Simulator tick rate (ticks/s) +host_mem_usage 297024 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -228,18 +228,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 872a056d2..8573f117d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815000 # Number of ticks simulated -final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25815500 # Number of ticks simulated +final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376930 # Simulator instruction rate (inst/s) -host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2127142386 # Simulator tick rate (ticks/s) -host_mem_usage 307352 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 263675 # Simulator instruction rate (inst/s) +host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1488783160 # Simulator tick rate (ticks/s) +host_mem_usage 306760 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51630 # number of cpu cycles simulated +system.cpu.numCycles 51631 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy @@ -440,17 +440,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,17 +503,17 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses @@ -525,17 +525,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -549,19 +549,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) @@ -588,9 +586,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ca0260a61..f65d4ed09 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21163500 # Number of ticks simulated -final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22762000 # Number of ticks simulated +final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81533 # Simulator instruction rate (inst/s) -host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345921870 # Simulator tick rate (ticks/s) -host_mem_usage 292088 # Number of bytes of host memory used +host_inst_rate 85129 # Simulator instruction rate (inst/s) +host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388456550 # Simulator tick rate (ticks/s) +host_mem_usage 291584 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21120 # Nu system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21083000 # Total gap between requests +system.physmem.totGap 22674500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation -system.physmem.totQLat 5392000 # Total ticks spent queuing -system.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation +system.physmem.totQLat 5218000 # Total ticks spent queuing +system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.13 # Data bus utilization in percentage -system.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.35 # Data bus utilization in percentage +system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44762.21 # Average gap between requests +system.physmem.avgGap 48141.19 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) -system.physmem_0.averagePower 790.660351 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) +system.physmem_0.averagePower 781.248697 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) -system.physmem_1.averagePower 944.255803 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) +system.physmem_1.averagePower 935.597347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2146 # Number of BP lookups -system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 528 # Number of BTB hits +system.cpu.branchPred.lookups 2110 # Number of BP lookups +system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups +system.cpu.branchPred.BTBHits 525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 42328 # number of cpu cycles simulated +system.cpu.numCycles 45525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13064 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2037 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2743 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 298 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8280 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8280 # Type of FU issued -system.cpu.iq.rate 0.195615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 197 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8204 # Type of FU issued +system.cpu.iq.rate 0.180209 # Inst issue rate +system.cpu.iq.fu_busy_cnt 196 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1553 # number of nop insts executed -system.cpu.iew.exec_refs 3252 # number of memory reference insts executed -system.cpu.iew.exec_branches 1379 # Number of branches executed -system.cpu.iew.exec_stores 1058 # Number of stores executed -system.cpu.iew.exec_rate 0.187984 # Inst execution rate -system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7468 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2915 # num instructions producing a value -system.cpu.iew.wb_consumers 4399 # num instructions consuming a value +system.cpu.iew.exec_nop 1532 # number of nop insts executed +system.cpu.iew.exec_refs 3217 # number of memory reference insts executed +system.cpu.iew.exec_branches 1365 # Number of branches executed +system.cpu.iew.exec_stores 1057 # Number of stores executed +system.cpu.iew.exec_rate 0.172982 # Inst execution rate +system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7410 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2869 # num instructions producing a value +system.cpu.iew.wb_consumers 4254 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back +system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,102 +554,102 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23983 # The number of ROB reads -system.cpu.rob.rob_writes 22065 # The number of ROB writes -system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23990 # The number of ROB reads +system.cpu.rob.rob_writes 21831 # The number of ROB writes +system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10767 # number of integer regfile reads -system.cpu.int_regfile_writes 5247 # number of integer regfile writes +system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads +system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10639 # number of integer regfile reads +system.cpu.int_regfile_writes 5201 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 164 # number of misc regfile reads +system.cpu.misc_regfile_reads 165 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits +system.cpu.dcache.overall_hits::total 2418 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -658,82 +658,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4407 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits -system.cpu.icache.overall_hits::total 1593 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses -system.cpu.icache.overall_misses::total 444 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4385 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses +system.cpu.icache.overall_misses::total 449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.221619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.221619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.221619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.221619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,51 +742,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26389500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26389500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 218.150435 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses @@ -807,17 +807,17 @@ system.cpu.l2cache.demand_misses::total 471 # nu system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 471 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26025000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 33763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26025000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26025000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37797500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) @@ -840,17 +840,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993671 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,17 +870,17 @@ system.cpu.l2cache.demand_mshr_misses::total 471 system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses @@ -892,17 +892,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution @@ -927,11 +927,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 421 # Transaction distribution system.membus.trans_dist::ReadResp 421 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution @@ -951,9 +951,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 84d2a731d..4f23a8939 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30902000 # Number of ticks simulated -final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30902500 # Number of ticks simulated +final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104539 # Simulator instruction rate (inst/s) -host_op_rate 104503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 574021463 # Simulator tick rate (ticks/s) -host_mem_usage 276192 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 544856 # Simulator instruction rate (inst/s) +host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2985748792 # Simulator tick rate (ticks/s) +host_mem_usage 288768 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 380 # Transaction distribution -system.membus.trans_dist::ReadResp 380 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 430 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430 # Request fanout histogram -system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -72,7 +49,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 61804 # number of cpu cycles simulated +system.cpu.numCycles 61805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -91,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61804 # Number of busy cycles +system.cpu.num_busy_cycles 61805 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -130,15 +107,119 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses +system.cpu.dcache.overall_misses::total 137 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -157,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses @@ -175,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -195,33 +276,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy @@ -248,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) @@ -281,17 +362,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,17 +392,17 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses @@ -333,122 +414,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses -system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -477,5 +454,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 380 # Transaction distribution +system.membus.trans_dist::ReadResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 430 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 430 # Request fanout histogram +system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index e81ca8aaa..c9ca56107 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18857500 # Number of ticks simulated -final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20101000 # Number of ticks simulated +final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101158 # Simulator instruction rate (inst/s) -host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329193143 # Simulator tick rate (ticks/s) -host_mem_usage 288984 # Number of bytes of host memory used +host_inst_rate 103196 # Simulator instruction rate (inst/s) +host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 357968408 # Simulator tick rate (ticks/s) +host_mem_usage 289136 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18724000 # Total gap between requests +system.physmem.totGap 19960500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3635500 # Total ticks spent queuing -system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3861750 # Total ticks spent queuing +system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.04 # Data bus utilization in percentage +system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 356 # Number of row buffer hits during reads +system.physmem.readRowHits 357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42171.17 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 44956.08 # Average gap between requests +system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) -system.physmem_0.averagePower 961.471341 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) +system.physmem_0.averagePower 951.571203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) -system.physmem_1.averagePower 751.599242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.063003 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2332 # Number of BP lookups -system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2330 # Number of BP lookups +system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups -system.cpu.branchPred.BTBHits 661 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups +system.cpu.branchPred.BTBHits 660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -279,237 +279,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 37716 # number of cpu cycles simulated +system.cpu.numCycles 40203 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1951 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst +system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4184 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.241489 # Inst issue rate -system.cpu.iq.fu_busy_cnt 251 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9105 # Type of FU issued +system.cpu.iq.rate 0.226476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 252 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14543 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3329 # number of memory reference insts executed -system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_refs 3330 # number of memory reference insts executed +system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.230724 # Inst execution rate -system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8300 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4483 # num instructions producing a value -system.cpu.iew.wb_consumers 7102 # num instructions consuming a value +system.cpu.iew.exec_rate 0.216427 # Inst execution rate +system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4465 # num instructions producing a value +system.cpu.iew.wb_consumers 7078 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back +system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,61 +555,61 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21860 # The number of ROB reads -system.cpu.rob.rob_writes 21470 # The number of ROB writes -system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22278 # The number of ROB reads +system.cpu.rob.rob_writes 21482 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads -system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13744 # number of integer regfile reads -system.cpu.int_regfile_writes 7176 # number of integer regfile writes +system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13740 # number of integer regfile reads +system.cpu.int_regfile_writes 7173 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits +system.cpu.dcache.overall_hits::total 2276 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -618,38 +618,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2713 # system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -658,14 +658,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -674,119 +674,119 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4007 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits -system.cpu.icache.overall_hits::total 1391 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4005 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits +system.cpu.icache.overall_hits::total 1389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses +system.cpu.icache.overall_misses::total 439 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses @@ -810,17 +810,17 @@ system.cpu.l2cache.demand_misses::total 445 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) @@ -843,17 +843,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984513 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_misses::total 445 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses @@ -895,17 +895,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution @@ -930,11 +930,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -954,9 +954,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 52edf7aee..f6a7e842c 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800000 # Number of ticks simulated -final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27800500 # Number of ticks simulated +final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 583909 # Simulator instruction rate (inst/s) -host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3038583452 # Simulator tick rate (ticks/s) -host_mem_usage 285748 # Number of bytes of host memory used +host_inst_rate 510787 # Simulator instruction rate (inst/s) +host_op_rate 510102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2658808340 # Simulator tick rate (ticks/s) +host_mem_usage 289420 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308 # Transaction distribution -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.6 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55600 # number of cpu cycles simulated +system.cpu.numCycles 55601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -112,15 +89,119 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits +system.cpu.dcache.overall_hits::total 1253 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -139,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -157,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy @@ -233,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) @@ -266,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses @@ -318,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -462,5 +439,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 308 # Transaction distribution +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 389 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 389 # Request fanout histogram +system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 3b4d7b677..8ea066b3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19678000 # Number of ticks simulated -final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21143500 # Number of ticks simulated +final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46918 # Simulator instruction rate (inst/s) -host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171550123 # Simulator tick rate (ticks/s) -host_mem_usage 309548 # Number of bytes of host memory used +host_inst_rate 49814 # Simulator instruction rate (inst/s) +host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195722405 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19629500 # Total gap between requests +system.physmem.totGap 21095000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,308 +186,310 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 4347000 # Total ticks spent queuing -system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation +system.physmem.totQLat 5105750 # Total ticks spent queuing +system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.60 # Data bus utilization in percentage -system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.86 # Data bus utilization in percentage +system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 309 # Number of row buffer hits during reads +system.physmem.readRowHits 307 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47073.14 # Average gap between requests -system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50587.53 # Average gap between requests +system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) -system.physmem_0.averagePower 837.810088 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) +system.physmem_0.averagePower 824.789199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) -system.physmem_1.averagePower 889.816201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) +system.physmem_1.averagePower 885.596400 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3423 # Number of BP lookups -system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.lookups 3414 # Number of BP lookups +system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups +system.cpu.branchPred.BTBHits 863 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39357 # number of cpu cycles simulated +system.cpu.numCycles 42288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 12291 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2168 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.270406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.764504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669642 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17618 80.47% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 1.08% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 0.79% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 259 1.18% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.95% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19573 82.11% 82.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 0.99% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 173 0.73% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.08% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.87% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 228 0.96% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 337 1.41% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.86% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2621 11.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2194 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 719 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3480 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3970 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24219 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12043 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3332 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12311 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3474 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 3820 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27591 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33558 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16528 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1503 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2441 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1612 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16525 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11007 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21893 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.773238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750147 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.712551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16772 76.61% 76.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1137 5.19% 81.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 886 4.05% 85.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 636 2.91% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 833 3.80% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 590 2.69% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 599 2.74% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 316 1.44% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.57% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18713 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1142 4.79% 83.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 888 3.73% 87.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 640 2.68% 89.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 832 3.49% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.45% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 601 2.52% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 23838 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14382 80.36% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17897 # Type of FU issued -system.cpu.iq.rate 0.454735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17882 # Type of FU issued +system.cpu.iq.rate 0.422862 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32462 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18114 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 228 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1388 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 677 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 601 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1862 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21468 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2441 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1612 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3251 # number of memory reference insts executed -system.cpu.iew.exec_branches 1662 # Number of branches executed +system.cpu.iew.exec_refs 3249 # number of memory reference insts executed +system.cpu.iew.exec_branches 1660 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.430063 # Inst execution rate -system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11006 # num instructions producing a value -system.cpu.iew.wb_consumers 17135 # num instructions consuming a value +system.cpu.iew.exec_rate 0.399877 # Inst execution rate +system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16357 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10994 # num instructions producing a value +system.cpu.iew.wb_consumers 17115 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back +system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21874 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.445598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336765 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 1.83% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 142 0.71% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.57% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.37% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18628 85.16% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1010 4.62% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 544 2.49% 92.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 738 3.37% 95.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 1.69% 97.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.64% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.52% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.33% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 259 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21874 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,102 +535,102 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 41131 # The number of ROB reads -system.cpu.rob.rob_writes 44929 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 43058 # The number of ROB reads +system.cpu.rob.rob_writes 44876 # The number of ROB writes +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21341 # number of integer regfile reads -system.cpu.int_regfile_writes 13120 # number of integer regfile writes +system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21328 # number of integer regfile reads +system.cpu.int_regfile_writes 13105 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8069 # number of cc regfile reads +system.cpu.cc_regfile_reads 8064 # number of cc regfile reads system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7491 # number of misc regfile reads +system.cpu.misc_regfile_reads 7485 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits +system.cpu.dcache.overall_hits::total 2393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses +system.cpu.dcache.overall_misses::total 212 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses @@ -637,82 +639,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4612 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits -system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4604 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits +system.cpu.icache.overall_hits::total 1796 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,39 +735,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 276 system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses @@ -786,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 417 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -819,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997608 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses @@ -871,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -908,11 +910,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 3 # system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution @@ -934,9 +936,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b43d6cab2..2ef89d07d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358000 # Number of ticks simulated -final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28358500 # Number of ticks simulated +final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 307468 # Simulator instruction rate (inst/s) -host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618053178 # Simulator tick rate (ticks/s) -host_mem_usage 302528 # Number of bytes of host memory used +host_inst_rate 312703 # Simulator instruction rate (inst/s) +host_op_rate 566020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1645401799 # Simulator tick rate (ticks/s) +host_mem_usage 307640 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,43 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 282 # Transaction distribution -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56716 # number of cpu cycles simulated +system.cpu.numCycles 56717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -117,15 +92,119 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits +system.cpu.dcache.overall_hits::total 1854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.dcache.overall_misses::total 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -144,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -162,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -235,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) @@ -268,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses @@ -320,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -466,5 +441,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 282 # Transaction distribution +system.membus.trans_dist::ReadResp 282 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 361 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 361 # Request fanout histogram +system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |