diff options
Diffstat (limited to 'tests/quick/se/00.hello')
18 files changed, 3079 insertions, 3080 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index ff8d4bf12..89a25c4c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21216000 because target called exit() +Exiting @ tick 21234500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index fc30a21c8..fdd02b36e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21216000 # Number of ticks simulated -final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 21234500 # Number of ticks simulated +final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 38129 # Simulator instruction rate (inst/s) -host_op_rate 38124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126288909 # Simulator tick rate (ticks/s) -host_mem_usage 209388 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 95244 # Simulator instruction rate (inst/s) +host_op_rate 95219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 315647941 # Simulator tick rate (ticks/s) +host_mem_usage 209384 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read 30016 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 469 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1414781297 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 907993967 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1414781297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -36,10 +36,10 @@ system.cpu.dtb.data_hits 2084 # DT system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 929 # ITB hits +system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 946 # ITB accesses +system.cpu.itb.fetch_accesses 925 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,16 +53,16 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42433 # number of cpu cycles simulated +system.cpu.numCycles 42470 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11397 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 442 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35050 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7383 # Number of cycles cpu stages are processed. -system.cpu.activity 17.399194 # Percentage of cycles cpu is active +system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. +system.cpu.activity 17.402873 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -74,92 +74,92 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150920 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads +system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150920 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1670 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1199 # Number of conditional branches predicted +system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1608 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1410 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 414 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 29.361702 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 565 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1105 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5165 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9745 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 3002 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2138 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 357 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 294 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2183 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4447 # Number of Instructions Executed. +system.cpu.execution_unit.executions 4474 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 37465 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4968 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.707869 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38516 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3917 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.231023 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38252 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.853180 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41093 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.157920 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 37964 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4469 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.531897 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.882502 # Cycle average of tags in use -system.cpu.icache.total_refs 581 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use +system.cpu.icache.total_refs 558 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.882502 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067814 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067814 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 581 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 581 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 581 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 581 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 581 # number of overall hits -system.cpu.icache.overall_hits::total 581 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses -system.cpu.icache.overall_misses::total 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19241000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19241000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 929 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 929 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 929 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 929 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 929 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.374596 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.374596 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.374596 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits +system.cpu.icache.overall_hits::total 558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -168,40 +168,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 46 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 46 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 46 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 46 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16049000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16049000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16049000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16049000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.325081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.671807 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025066 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025066 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits @@ -218,14 +218,14 @@ system.cpu.dcache.demand_misses::cpu.data 347 # n system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5508500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5508500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19064000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19064000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19064000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -238,10 +238,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54222 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -266,34 +266,34 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -311,17 +311,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -340,13 +340,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,16 +367,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -385,12 +385,12 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index 684d7e9b2..16153e12a 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:12 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:02 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12004500 because target called exit() +Exiting @ tick 12450500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 49671266a..bfc4cc915 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12004500 # Number of ticks simulated -final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12450500 # Number of ticks simulated +final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 42281 # Simulator instruction rate (inst/s) -host_op_rate 42276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79460110 # Simulator tick rate (ticks/s) -host_mem_usage 210060 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 87465 # Simulator instruction rate (inst/s) +host_op_rate 87444 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 170447462 # Simulator tick rate (ticks/s) +host_mem_usage 210080 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 31040 # Number of bytes read from this memory -system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory +system.physmem.bytes_read 31360 # Number of bytes read from this memory +system.physmem.bytes_inst_read 20096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 485 # Number of read requests responded to by this memory +system.physmem.num_reads 490 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2518774346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1614071724 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2518774346 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1860 # DTB read hits -system.cpu.dtb.read_misses 44 # DTB read misses +system.cpu.dtb.read_hits 1943 # DTB read hits +system.cpu.dtb.read_misses 53 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1904 # DTB read accesses -system.cpu.dtb.write_hits 1041 # DTB write hits -system.cpu.dtb.write_misses 28 # DTB write misses +system.cpu.dtb.read_accesses 1996 # DTB read accesses +system.cpu.dtb.write_hits 1071 # DTB write hits +system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1069 # DTB write accesses -system.cpu.dtb.data_hits 2901 # DTB hits -system.cpu.dtb.data_misses 72 # DTB misses +system.cpu.dtb.write_accesses 1103 # DTB write accesses +system.cpu.dtb.data_hits 3014 # DTB hits +system.cpu.dtb.data_misses 85 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2973 # DTB accesses -system.cpu.itb.fetch_hits 2039 # ITB hits -system.cpu.itb.fetch_misses 29 # ITB misses +system.cpu.dtb.data_accesses 3099 # DTB accesses +system.cpu.itb.fetch_hits 2367 # ITB hits +system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2068 # ITB accesses +system.cpu.itb.fetch_accesses 2393 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,246 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24010 # number of cpu cycles simulated +system.cpu.numCycles 24902 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2507 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits +system.cpu.BPredUnit.lookups 2873 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2318 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2784 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2587 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 28 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. +system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9757 # Type of FU issued -system.cpu.iq.rate 0.406372 # Inst issue rate -system.cpu.iq.fu_busy_cnt 106 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10522 # Type of FU issued +system.cpu.iq.rate 0.422536 # Inst issue rate +system.cpu.iq.fu_busy_cnt 112 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80 # number of nop insts executed -system.cpu.iew.exec_refs 2985 # number of memory reference insts executed -system.cpu.iew.exec_branches 1504 # Number of branches executed -system.cpu.iew.exec_stores 1071 # Number of stores executed -system.cpu.iew.exec_rate 0.387880 # Inst execution rate -system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8992 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4719 # num instructions producing a value -system.cpu.iew.wb_consumers 6404 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 3117 # number of memory reference insts executed +system.cpu.iew.exec_branches 1605 # Number of branches executed +system.cpu.iew.exec_stores 1108 # Number of stores executed +system.cpu.iew.exec_rate 0.396675 # Inst execution rate +system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9487 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4957 # num instructions producing a value +system.cpu.iew.wb_consumers 6732 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back +system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -303,64 +303,64 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22763 # The number of ROB reads -system.cpu.rob.rob_writes 24313 # The number of ROB writes -system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24667 # The number of ROB reads +system.cpu.rob.rob_writes 26868 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 11830 # number of integer regfile reads -system.cpu.int_regfile_writes 6732 # number of integer regfile writes +system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads +system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12526 # number of integer regfile reads +system.cpu.int_regfile_writes 7116 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use -system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use +system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.112304 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078180 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078180 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1606 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1606 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1606 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1606 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1606 # number of overall hits -system.cpu.icache.overall_hits::total 1606 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 433 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 433 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 433 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 433 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 433 # number of overall misses -system.cpu.icache.overall_misses::total 433 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15431000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15431000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15431000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15431000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15431000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212359 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212359 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212359 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits +system.cpu.icache.overall_hits::total 1909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses +system.cpu.icache.overall_misses::total 458 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -369,80 +369,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 121 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 121 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 121 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 121 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 121 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11021000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11021000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use -system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use +system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.290272 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026682 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1645 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1645 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2154 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2154 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2154 # number of overall hits -system.cpu.dcache.overall_hits::total 2154 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 154 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 154 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits +system.cpu.dcache.overall_hits::total 2244 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses -system.cpu.dcache.overall_misses::total 510 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12467500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12467500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17965000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17965000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17965000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1799 # 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2664 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2664 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2664 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2664 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085603 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191441 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191441 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -451,103 +451,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 336 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 336 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3654500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2611500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6266000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6266000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056142 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065315 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.084939 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 61.558127 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004885 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001879 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006764 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 311 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 412 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 485 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10665000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3498000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14163000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2513500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10665000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6011500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16676500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10665000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses +system.cpu.l2cache.overall_misses::total 490 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -556,42 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 6aed6d3ac..eb202613d 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:09:23 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 17:33:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6833000 because target called exit() +Exiting @ tick 7015000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d93b581f0..686010297 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6833000 # Number of ticks simulated -final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7015000 # Number of ticks simulated +final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16400 # Simulator instruction rate (inst/s) -host_op_rate 16398 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 46934615 # Simulator tick rate (ticks/s) -host_mem_usage 209144 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 73930 # Simulator instruction rate (inst/s) +host_op_rate 73884 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 217009042 # Simulator tick rate (ticks/s) +host_mem_usage 209140 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 17280 # Number of bytes read from this memory -system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory +system.physmem.bytes_read 17600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 12096 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 270 # Number of read requests responded to by this memory +system.physmem.num_reads 275 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2528903849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1732767452 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2528903849 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2508909480 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1724305061 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2508909480 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 679 # DTB read hits -system.cpu.dtb.read_misses 26 # DTB read misses +system.cpu.dtb.read_hits 711 # DTB read hits +system.cpu.dtb.read_misses 43 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 705 # DTB read accesses -system.cpu.dtb.write_hits 356 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 754 # DTB read accesses +system.cpu.dtb.write_hits 380 # DTB write hits +system.cpu.dtb.write_misses 23 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 374 # DTB write accesses -system.cpu.dtb.data_hits 1035 # DTB hits -system.cpu.dtb.data_misses 44 # DTB misses +system.cpu.dtb.write_accesses 403 # DTB write accesses +system.cpu.dtb.data_hits 1091 # DTB hits +system.cpu.dtb.data_misses 66 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1079 # DTB accesses -system.cpu.itb.fetch_hits 941 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 1157 # DTB accesses +system.cpu.itb.fetch_hits 1067 # ITB hits +system.cpu.itb.fetch_misses 33 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 971 # ITB accesses +system.cpu.itb.fetch_accesses 1100 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -53,245 +53,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13667 # number of cpu cycles simulated +system.cpu.numCycles 14031 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1038 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 518 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 226 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 732 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 219 # Number of BTB hits +system.cpu.BPredUnit.lookups 1201 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 208 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3757 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6399 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1038 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 427 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1112 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 750 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 212 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 785 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 941 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 156 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.002507 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.418848 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5271 82.58% 82.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 60 0.94% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 117 1.83% 85.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 94 1.47% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 140 2.19% 89.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 57 0.89% 89.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 55 0.86% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 1.00% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 525 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6383 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075949 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.468208 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4647 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 226 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1081 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 423 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 158 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 80 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5725 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 284 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 423 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4742 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 57 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1197 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 995 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 19 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5471 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 14 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 3940 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6152 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6140 # Number of integer rename lookups +system.cpu.rename.RunCycles 1115 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2172 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 107 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 881 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 453 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4657 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3881 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1177 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6383 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608021 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298413 # Number of insts issued each cycle +system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4813 75.40% 75.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 542 8.49% 83.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 388 6.08% 89.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 264 4.14% 94.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 199 3.12% 97.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 107 1.68% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.86% 99.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10 0.16% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 5 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6383 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1 2.44% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 41.46% 43.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 56.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2767 71.30% 71.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 733 18.89% 90.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 380 9.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3881 # Type of FU issued -system.cpu.iq.rate 0.283969 # Inst issue rate -system.cpu.iq.fu_busy_cnt 41 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010564 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14222 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3573 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4206 # Type of FU issued +system.cpu.iq.rate 0.299765 # Inst issue rate +system.cpu.iq.fu_busy_cnt 43 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3915 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 35 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 466 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 159 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 423 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5001 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 64 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 881 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 453 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 121 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3749 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 706 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 132 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1080 # number of memory reference insts executed -system.cpu.iew.exec_branches 629 # Number of branches executed -system.cpu.iew.exec_stores 374 # Number of stores executed -system.cpu.iew.exec_rate 0.274310 # Inst execution rate -system.cpu.iew.wb_sent 3647 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3579 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1702 # num instructions producing a value -system.cpu.iew.wb_consumers 2165 # num instructions consuming a value +system.cpu.iew.exec_nop 368 # number of nop insts executed +system.cpu.iew.exec_refs 1160 # number of memory reference insts executed +system.cpu.iew.exec_branches 681 # Number of branches executed +system.cpu.iew.exec_stores 403 # Number of stores executed +system.cpu.iew.exec_rate 0.285439 # Inst execution rate +system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3813 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1793 # num instructions producing a value +system.cpu.iew.wb_consumers 2339 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.261872 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back +system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 5960 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.432215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.290536 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5068 85.03% 85.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 222 3.72% 88.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 314 5.27% 94.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 119 2.00% 96.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 70 1.17% 97.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.89% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.57% 98.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 20 0.34% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 60 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -302,63 +303,63 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 10645 # The number of ROB reads -system.cpu.rob.rob_writes 10410 # The number of ROB writes -system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11567 # The number of ROB reads +system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads -system.cpu.ipc 0.174654 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.174654 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4520 # number of integer regfile reads -system.cpu.int_regfile_writes 2768 # number of integer regfile writes +system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4832 # number of integer regfile reads +system.cpu.int_regfile_writes 2958 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 91.574139 # Cycle average of tags in use -system.cpu.icache.total_refs 700 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use +system.cpu.icache.total_refs 817 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits -system.cpu.icache.overall_hits::total 700 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses -system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits +system.cpu.icache.overall_hits::total 817 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses +system.cpu.icache.overall_misses::total 250 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -367,80 +368,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.439198 # Cycle average of tags in use -system.cpu.dcache.total_refs 765 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use +system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.439198 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011094 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 765 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 765 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 765 # number of overall hits -system.cpu.dcache.overall_hits::total 765 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 101 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits +system.cpu.dcache.overall_hits::total 793 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 173 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.dcache.overall_misses::total 173 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3605000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3605000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6421500 # 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number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 938 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 938 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.156832 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184435 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184435 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -449,83 +450,83 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 88 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 88 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 85 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090618 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 120.203882 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 246 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.660485 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.543397 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000871 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 185 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 246 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9278500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 185 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 246 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses +system.cpu.l2cache.overall_misses::total 275 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 185 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 270 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 185 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 270 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses @@ -533,13 +534,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34500 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,28 +549,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 246 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5756000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1905500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses @@ -577,13 +578,13 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index ab1ef55e9..e7e46b503 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:10:40 -gem5 started Feb 11 2012 15:35:50 +gem5 compiled Feb 12 2012 17:19:56 +gem5 started Feb 12 2012 19:57:12 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10000500 because target called exit() +Exiting @ tick 10389500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 010933949..6eeb02481 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10000500 # Number of ticks simulated -final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10389500 # Number of ticks simulated +final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72927 # Simulator instruction rate (inst/s) -host_op_rate 90959 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158457261 # Simulator tick rate (ticks/s) -host_mem_usage 221260 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 66059 # Simulator instruction rate (inst/s) +host_op_rate 82394 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 149123755 # Simulator tick rate (ticks/s) +host_mem_usage 221320 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4600 # Number of instructions simulated sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 25856 # Number of bytes read from this memory -system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory +system.physmem.bytes_read 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 404 # Number of read requests responded to by this memory +system.physmem.num_reads 400 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2585470726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1785510724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2585470726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -63,245 +63,246 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20002 # number of cpu cycles simulated +system.cpu.numCycles 20780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2398 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits +system.cpu.BPredUnit.lookups 2550 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6118 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12133 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1919 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.338286 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.716814 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8814 76.59% 76.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.96% 82.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 227 1.97% 84.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 313 2.72% 86.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11508 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119888 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.606589 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6263 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2491 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6539 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2270 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2634 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2397 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 41 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11508 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.756517 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.438154 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 48 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8023 69.72% 69.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11508 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8706 # Type of FU issued -system.cpu.iq.rate 0.435256 # Inst issue rate -system.cpu.iq.fu_busy_cnt 203 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29182 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9138 # Type of FU issued +system.cpu.iq.rate 0.439750 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3178 # number of memory reference insts executed -system.cpu.iew.exec_branches 1354 # Number of branches executed -system.cpu.iew.exec_stores 1169 # Number of stores executed -system.cpu.iew.exec_rate 0.414059 # Inst execution rate -system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7840 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3690 # num instructions producing a value -system.cpu.iew.wb_consumers 7291 # num instructions consuming a value +system.cpu.iew.exec_refs 3325 # number of memory reference insts executed +system.cpu.iew.exec_branches 1404 # Number of branches executed +system.cpu.iew.exec_stores 1195 # Number of stores executed +system.cpu.iew.exec_rate 0.415544 # Inst execution rate +system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8156 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3863 # num instructions producing a value +system.cpu.iew.wb_consumers 7813 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back +system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10622 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.540294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.352838 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8286 78.01% 78.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 420 3.95% 92.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle system.cpu.commit.committedInsts 4600 # Number of instructions committed system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -312,63 +313,63 @@ system.cpu.commit.branches 945 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4985 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21205 # The number of ROB reads -system.cpu.rob.rob_writes 22566 # The number of ROB writes -system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22664 # The number of ROB reads +system.cpu.rob.rob_writes 24737 # The number of ROB writes +system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4600 # Number of Instructions Simulated system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.348261 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.348261 # CPI: Total CPI of All Threads -system.cpu.ipc 0.229977 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.229977 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 37816 # number of integer regfile reads -system.cpu.int_regfile_writes 7658 # number of integer regfile writes +system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads +system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39570 # number of integer regfile reads +system.cpu.int_regfile_writes 8020 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 14992 # number of misc regfile reads +system.cpu.misc_regfile_reads 16023 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 148.855822 # Cycle average of tags in use -system.cpu.icache.total_refs 1559 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use +system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.855822 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072684 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072684 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1559 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1559 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1559 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1559 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1559 # number of overall hits -system.cpu.icache.overall_hits::total 1559 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses -system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12552000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12552000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12552000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12552000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12552000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1919 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1919 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1919 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1919 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1919 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187598 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.187598 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.187598 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits +system.cpu.icache.overall_hits::total 1663 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses +system.cpu.icache.overall_misses::total 365 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,94 +378,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9945000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9945000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9945000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9945000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use -system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use +system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.085552 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021749 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1702 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1702 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2311 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2311 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2311 # number of overall hits -system.cpu.dcache.overall_hits::total 2311 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits +system.cpu.dcache.overall_hits::total 2389 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 473 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 473 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 473 # number of overall misses -system.cpu.dcache.overall_misses::total 473 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5350500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5350500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10725000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10725000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5506000 # 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number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2784 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2784 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2784 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2784 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090326 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169899 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169899 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -473,108 +474,108 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # 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miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,48 +584,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 9f59be0ce..e34fa5006 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:30 +gem5 compiled Feb 12 2012 17:16:48 +gem5 started Feb 12 2012 18:16:47 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19785000 because target called exit() +Exiting @ tick 19775000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 6cd55fbff..e8bd2f84c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19785000 # Number of ticks simulated -final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19775000 # Number of ticks simulated +final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101976 # Simulator instruction rate (inst/s) -host_op_rate 101944 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 346042004 # Simulator tick rate (ticks/s) -host_mem_usage 210372 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 108846 # Simulator instruction rate (inst/s) +host_op_rate 108810 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 369151681 # Simulator tick rate (ticks/s) +host_mem_usage 210376 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read 29120 # Number of bytes read from this memory @@ -17,9 +17,9 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 455 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1471822087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1025423300 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1471822087 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1472566372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1025941846 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1472566372 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,16 +39,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39571 # number of cpu cycles simulated +system.cpu.numCycles 39551 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9159 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 403 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34166 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5405 # Number of cycles cpu stages are processed. -system.cpu.activity 13.658993 # Percentage of cycles cpu is active +system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. +system.cpu.activity 13.572350 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -60,92 +60,92 @@ system.cpu.committedInsts 5827 # Nu system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) -system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147254 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads +system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147254 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1185 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 896 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 611 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1035 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 443 # Number of BTB hits +system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1152 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted +system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect +system.cpu.branch_predictor.BTBLookups 867 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 309 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 42.801932 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 536 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 649 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5108 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 35.640138 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 402 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 750 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5104 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8516 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8512 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1344 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2228 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 317 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 285 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 602 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 314 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.720524 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3132 # Number of Instructions Executed. +system.cpu.regfile_manager.regForwards 1330 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2238 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.predicted 320 # Number of Branches Incorrectly Predicted +system.cpu.execution_unit.mispredictPct 65.065502 # Percentage of Incorrect Branches Predicts +system.cpu.execution_unit.executions 3155 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 35846 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3725 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.413459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36723 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2848 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.197190 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36778 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2793 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.058199 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38328 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 36722 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.152790 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36760 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.056712 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 38308 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.141189 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36666 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.341235 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.142778 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 36647 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.342419 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.138598 # Cycle average of tags in use -system.cpu.icache.total_refs 443 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 148.175887 # Cycle average of tags in use +system.cpu.icache.total_refs 411 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.388715 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.138598 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072333 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072333 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 443 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 443 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 443 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 443 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 443 # number of overall hits -system.cpu.icache.overall_hits::total 443 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 341 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 341 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 341 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 341 # number of overall misses -system.cpu.icache.overall_misses::total 341 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19027500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19027500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19027500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19027500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19027500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 784 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 784 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 784 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 784 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 784 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.434949 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.434949 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.434949 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 148.175887 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072352 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072352 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits +system.cpu.icache.overall_hits::total 411 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 343 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 343 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 343 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 343 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 343 # number of overall misses +system.cpu.icache.overall_misses::total 343 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19128500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19128500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19128500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19128500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19128500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19128500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -154,40 +154,40 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 24 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16952500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16952500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16952500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16952500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.406888 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16951500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16951500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16951500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16951500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.732679 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.732679 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021907 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021907 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 89.746602 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021911 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021911 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits @@ -206,12 +206,12 @@ system.cpu.dcache.overall_misses::cpu.data 251 # system.cpu.dcache.overall_misses::total 251 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8912000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8912000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13984500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13984500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13984500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8910500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8910500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13983000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13983000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13983000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -225,9 +225,9 @@ system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -254,32 +254,32 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 138 system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2746000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7448500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7448500 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2745500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7448000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 149.817885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.700002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004572 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006272 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -297,17 +297,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21170000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2682000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16585000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7267000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23852000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16585000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7267000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -326,13 +326,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index afa267678..e545392ce 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:32 -gem5 started Feb 11 2012 13:54:39 +gem5 compiled Feb 12 2012 17:16:48 +gem5 started Feb 12 2012 18:16:57 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12272500 because target called exit() +Exiting @ tick 12671500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 9ff42644b..f9bef2483 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12272500 # Number of ticks simulated -final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12671500 # Number of ticks simulated +final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97350 # Simulator instruction rate (inst/s) -host_op_rate 97317 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 230983195 # Simulator tick rate (ticks/s) -host_mem_usage 211060 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 93816 # Simulator instruction rate (inst/s) +host_op_rate 93786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 229841550 # Simulator tick rate (ticks/s) +host_mem_usage 211032 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30400 # Number of bytes read from this memory -system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory +system.physmem.bytes_read 30912 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 475 # Number of read requests responded to by this memory +system.physmem.num_reads 483 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2477082909 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1736565492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2477082909 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24546 # number of cpu cycles simulated +system.cpu.numCycles 25344 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1975 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1343 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 399 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1578 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 493 # Number of BTB hits +system.cpu.BPredUnit.lookups 2242 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 251 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7903 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12258 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1975 # Number of branches that fetch encountered +system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3024 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1186 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 756 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1781 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 229 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.972240 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.277843 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9584 76.02% 76.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1250 9.91% 85.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 108 0.86% 86.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.10% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 289 2.29% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 92 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 132 1.05% 91.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 145 1.15% 93.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 869 6.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12608 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080461 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.499389 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8092 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 871 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2857 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 737 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 107 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11425 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 737 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8263 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 258 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2740 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 111 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11004 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 101 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 6697 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13109 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13105 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3128 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2966 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3287 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 281 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2346 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1174 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8640 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7815 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2984 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1806 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12608 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.619845 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.285923 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9257 73.42% 73.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1317 10.45% 83.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 832 6.60% 90.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 510 4.05% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 356 2.82% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 201 1.59% 98.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.67% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 35 0.28% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12608 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.05% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.05% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 91 62.33% 64.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 35.62% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4596 58.81% 58.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.03% 58.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2128 27.23% 86.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1083 13.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7815 # Type of FU issued -system.cpu.iq.rate 0.318382 # Inst issue rate -system.cpu.iq.fu_busy_cnt 146 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018682 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 28430 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11643 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7116 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8177 # Type of FU issued +system.cpu.iq.rate 0.322640 # Inst issue rate +system.cpu.iq.fu_busy_cnt 152 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 7959 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1182 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 249 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 737 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 165 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10031 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 128 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2346 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1174 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 416 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7531 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2028 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 284 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1378 # number of nop insts executed -system.cpu.iew.exec_refs 3087 # number of memory reference insts executed -system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1059 # Number of stores executed -system.cpu.iew.exec_rate 0.306812 # Inst execution rate -system.cpu.iew.wb_sent 7210 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7118 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2758 # num instructions producing a value -system.cpu.iew.wb_consumers 3946 # num instructions consuming a value +system.cpu.iew.exec_nop 1464 # number of nop insts executed +system.cpu.iew.exec_refs 3166 # number of memory reference insts executed +system.cpu.iew.exec_branches 1317 # Number of branches executed +system.cpu.iew.exec_stores 1061 # Number of stores executed +system.cpu.iew.exec_rate 0.306305 # Inst execution rate +system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7307 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2841 # num instructions producing a value +system.cpu.iew.wb_consumers 4060 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.289986 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back +system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11871 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.490776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.277197 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9472 79.79% 79.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 966 8.14% 87.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 656 5.53% 93.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 321 2.70% 96.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 147 1.24% 97.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 102 0.86% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.54% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.35% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -288,63 +288,63 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21779 # The number of ROB reads -system.cpu.rob.rob_writes 20794 # The number of ROB writes +system.cpu.rob.rob_reads 22904 # The number of ROB reads +system.cpu.rob.rob_writes 22029 # The number of ROB writes system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads -system.cpu.ipc 0.210584 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.210584 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10280 # number of integer regfile reads -system.cpu.int_regfile_writes 4987 # number of integer regfile writes +system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads +system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10565 # number of integer regfile reads +system.cpu.int_regfile_writes 5131 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 153 # number of misc regfile reads -system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 161.224498 # Cycle average of tags in use -system.cpu.icache.total_refs 1363 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 151 # number of misc regfile reads +system.cpu.icache.replacements 19 # number of replacements +system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use +system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits -system.cpu.icache.overall_hits::total 1363 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses -system.cpu.icache.overall_misses::total 418 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15148000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15148000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15148000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15148000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1781 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1781 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1781 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1781 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1781 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234700 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234700 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234700 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits +system.cpu.icache.overall_hits::total 1592 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses +system.cpu.icache.overall_misses::total 447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,80 +353,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 336 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 336 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 336 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11784000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11784000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11784000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11784000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188658 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.121984 # Cycle average of tags in use -system.cpu.dcache.total_refs 2380 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use +system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.760563 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.121984 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022491 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1802 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1802 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2380 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2380 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2380 # number of overall hits -system.cpu.dcache.overall_hits::total 2380 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2472 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2472 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2472 # number of overall hits +system.cpu.dcache.overall_hits::total 2472 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses -system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4767500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4767500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11508000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11508000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16275500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16275500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16275500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1935 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1935 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses +system.cpu.dcache.overall_misses::total 472 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.068734 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.167832 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.167832 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -437,12 +437,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 338 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 338 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 338 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -451,87 +451,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3272000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1836000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5108000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5108000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047028 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.049650 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 221.521956 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 424 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.007075 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 163.434563 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.087393 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004988 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001773 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006760 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.134201 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006908 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 333 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 424 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 432 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 333 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 341 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 475 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 333 # number of overall misses +system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 341 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 475 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11418500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1760500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11418500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4903000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16321500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11418500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4903000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16321500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 336 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11691000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 427 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 336 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,42 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 8e7d01159..a3c2e1876 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:07:55 -gem5 started Feb 11 2012 13:55:01 +gem5 compiled Feb 12 2012 17:17:52 +gem5 started Feb 12 2012 18:17:19 gem5 executing on zizzer command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10910500 because target called exit() +Exiting @ tick 11243500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 7c789f568..e78f47ce4 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,25 +1,25 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10910500 # Number of ticks simulated -final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11243500 # Number of ticks simulated +final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114395 # Simulator instruction rate (inst/s) -host_op_rate 114354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 215042277 # Simulator tick rate (ticks/s) -host_mem_usage 207892 # Number of bytes of host memory used +host_inst_rate 108078 # Simulator instruction rate (inst/s) +host_op_rate 108043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 209380098 # Simulator tick rate (ticks/s) +host_mem_usage 207884 # Number of bytes of host memory used host_seconds 0.05 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28608 # Number of bytes read from this memory -system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28736 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 447 # Number of read requests responded to by this memory +system.physmem.num_reads 449 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2622061317 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 2017872691 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2622061317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -39,245 +39,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 21822 # number of cpu cycles simulated +system.cpu.numCycles 22488 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2297 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1905 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 402 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1853 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 666 # Number of BTB hits +system.cpu.BPredUnit.lookups 2514 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 189 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6507 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12976 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2297 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 855 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2210 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1212 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 909 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1711 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 10433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.243746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.642546 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8223 78.82% 78.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 152 1.46% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 173 1.66% 81.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 127 1.22% 83.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 217 2.08% 85.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 137 1.31% 86.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 283 2.71% 89.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 122 1.17% 90.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 999 9.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 10433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.105261 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.594629 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6670 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 983 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2045 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 656 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 304 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 152 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11459 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 428 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 656 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6866 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 379 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 350 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1920 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 262 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 10928 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 207 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 9549 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17852 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17781 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 71 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2252 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2095 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4542 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 544 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1864 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1573 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 44 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9933 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8536 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3878 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 53 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 10433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.818173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531685 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7234 69.34% 69.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1021 9.79% 79.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 762 7.30% 86.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 472 4.52% 90.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 448 4.29% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 290 2.78% 98.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 132 1.27% 99.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.49% 99.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.22% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 10433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.84% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 68 44.16% 50.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 77 50.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5388 63.12% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1717 20.11% 83.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1429 16.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8536 # Type of FU issued -system.cpu.iq.rate 0.391165 # Inst issue rate -system.cpu.iq.fu_busy_cnt 154 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018041 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 27649 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 13831 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7849 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 74 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 30 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8652 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 38 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 9284 # Type of FU issued +system.cpu.iq.rate 0.412842 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 902 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 527 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 656 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 186 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10002 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 43 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1864 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1573 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 60 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 238 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 300 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8170 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1611 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 366 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 2952 # number of memory reference insts executed -system.cpu.iew.exec_branches 1313 # Number of branches executed -system.cpu.iew.exec_stores 1341 # Number of stores executed -system.cpu.iew.exec_rate 0.374393 # Inst execution rate -system.cpu.iew.wb_sent 7993 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7879 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4173 # num instructions producing a value -system.cpu.iew.wb_consumers 6691 # num instructions consuming a value +system.cpu.iew.exec_refs 3258 # number of memory reference insts executed +system.cpu.iew.exec_branches 1391 # Number of branches executed +system.cpu.iew.exec_stores 1554 # Number of stores executed +system.cpu.iew.exec_rate 0.389274 # Inst execution rate +system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8387 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4351 # num instructions producing a value +system.cpu.iew.wb_consumers 7020 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.361058 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back +system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 9777 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.593229 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.375317 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7386 75.54% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 981 10.03% 85.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 642 6.57% 92.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 262 2.68% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 190 1.94% 96.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 116 1.19% 97.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 75 0.77% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.42% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 84 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -288,62 +288,62 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 84 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 19701 # The number of ROB reads -system.cpu.rob.rob_writes 20673 # The number of ROB writes -system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21145 # The number of ROB reads +system.cpu.rob.rob_writes 22688 # The number of ROB writes +system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads -system.cpu.ipc 0.265787 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.265787 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12979 # number of integer regfile reads -system.cpu.int_regfile_writes 6957 # number of integer regfile writes -system.cpu.fp_regfile_reads 28 # number of floating regfile reads +system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads +system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13921 # number of integer regfile reads +system.cpu.int_regfile_writes 7265 # number of integer regfile writes +system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 169.539680 # Cycle average of tags in use -system.cpu.icache.total_refs 1291 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use +system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 169.539680 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.082783 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.082783 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1291 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1291 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1291 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1291 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1291 # number of overall hits -system.cpu.icache.overall_hits::total 1291 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 420 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 420 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 420 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 420 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 420 # number of overall misses -system.cpu.icache.overall_misses::total 420 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15114500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15114500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15114500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15114500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15114500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1711 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1711 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1711 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1711 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1711 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.245470 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.245470 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.245470 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits +system.cpu.icache.overall_hits::total 1462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -352,80 +352,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12207500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12207500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12207500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12207500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.205143 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34779.202279 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34779.202279 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 82 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2562 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2562 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2562 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2562 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.304015 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.158470 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.158470 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33488.636364 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.125786 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33865.763547 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -434,106 +434,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # 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mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # 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number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3574000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15392500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 57 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses +system.cpu.l2cache.overall_misses::total 449 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 351 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 105 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 351 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 105 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.980057 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964912 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.980057 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.980952 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.980057 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.980952 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.104651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34463.636364 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34968.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.104651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34699.029126 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,42 +539,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 447 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 447 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10708500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1725500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12434000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10708500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3251500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10708500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3251500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13960000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 13c85267e..cf9740828 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:33 -gem5 started Feb 11 2012 13:55:12 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:17:30 gem5 executing on zizzer command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18201500 because target called exit() +Hello World!Exiting @ tick 18196500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 99d0ed042..440f0bc0a 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18201500 # Number of ticks simulated -final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18196500 # Number of ticks simulated +final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71915 # Simulator instruction rate (inst/s) -host_op_rate 71898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245008016 # Simulator tick rate (ticks/s) -host_mem_usage 211144 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 90140 # Simulator instruction rate (inst/s) +host_op_rate 90112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 306976844 # Simulator tick rate (ticks/s) +host_mem_usage 211148 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read 27072 # Number of bytes read from this memory @@ -17,20 +17,20 @@ system.physmem.bytes_written 0 # Nu system.physmem.num_reads 423 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 1487349944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1016179985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 1487349944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36404 # number of cpu cycles simulated +system.cpu.numCycles 36394 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9720 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30130 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6274 # Number of cycles cpu stages are processed. -system.cpu.activity 17.234370 # Percentage of cycles cpu is active +system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. +system.cpu.activity 17.109963 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -42,98 +42,98 @@ system.cpu.committedInsts 5340 # Nu system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) -system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146687 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads +system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146687 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 1662 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1123 # Number of conditional branches predicted +system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads +system.cpu.branch_predictor.lookups 1617 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1455 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 643 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 44.192440 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 710 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 952 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9612 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1747 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1473 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 394 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 442 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.regfile_manager.regForwards 1686 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 1487 # Number of Address Generations +system.cpu.execution_unit.predictedTakenIncorrect 319 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.execution_unit.predictedNotTakenIncorrect 517 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3977 # Number of Instructions Executed. +system.cpu.execution_unit.executions 3979 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 31738 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4666 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.817273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33193 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3211 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.820459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33357 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3047 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.369959 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35421 # Number of cycles 0 instructions are processed. +system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.700253 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33233 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3171 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.710581 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.669321 # Cycle average of tags in use -system.cpu.icache.total_refs 791 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use +system.cpu.icache.total_refs 827 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits -system.cpu.icache.overall_hits::total 791 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits +system.cpu.icache.overall_hits::total 827 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses system.cpu.icache.overall_misses::total 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits @@ -148,28 +148,28 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.859932 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.859932 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020229 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020229 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits @@ -186,14 +186,14 @@ system.cpu.dcache.demand_misses::cpu.data 340 # n system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses system.cpu.dcache.overall_misses::total 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3290500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3290500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15457500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15457500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18748000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18748000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18748000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -206,10 +206,10 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -234,31 +234,31 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2865500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7192500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7192500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7192500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.297266 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.185515 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.111751 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy @@ -282,17 +282,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15132500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17918500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15132500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7016500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15132500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7016500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22149000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -311,13 +311,13 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index ac1cd3610..eda7f85a5 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:08:53 -gem5 started Feb 11 2012 14:04:05 +gem5 compiled Feb 12 2012 17:18:12 +gem5 started Feb 12 2012 18:26:23 gem5 executing on zizzer command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11989500 because target called exit() +Exiting @ tick 12299500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 658a056fb..475f993c2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,264 +1,264 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11989500 # Number of ticks simulated -final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12299500 # Number of ticks simulated +final_tick 12299500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61798 # Simulator instruction rate (inst/s) -host_op_rate 111900 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 136747555 # Simulator tick rate (ticks/s) -host_mem_usage 218292 # Number of bytes of host memory used +host_inst_rate 59298 # Simulator instruction rate (inst/s) +host_op_rate 107375 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134612595 # Simulator tick rate (ticks/s) +host_mem_usage 218308 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 28288 # Number of bytes read from this memory -system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory +system.physmem.bytes_read 28864 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19328 # Number of instructions bytes read from this memory system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 442 # Number of read requests responded to by this memory +system.physmem.num_reads 451 # Number of read requests responded to by this memory system.physmem.num_writes 0 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 2359397806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 1580049210 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total 2359397806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read 2346762063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1571445994 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 2346762063 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 23980 # number of cpu cycles simulated +system.cpu.numCycles 24600 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3019 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3019 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2695 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 978 # Number of BTB hits +system.cpu.BPredUnit.lookups 3225 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3225 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 566 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2653 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 811 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7194 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3019 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 978 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3921 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2194 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3367 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1866 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.543567 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.980612 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7427 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15574 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3225 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2532 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3117 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 203 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1968 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.630863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.070076 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12367 76.42% 76.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 166 1.03% 77.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 172 1.06% 78.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.47% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 224 1.38% 81.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 191 1.18% 82.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 276 1.71% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 137 0.85% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2411 14.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 12804 75.73% 75.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 179 1.06% 76.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.97% 77.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 216 1.28% 79.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 176 1.04% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 185 1.09% 81.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.50% 82.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 169 1.00% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2761 16.33% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16182 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125897 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.576772 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7550 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3508 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 122 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1687 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 23802 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1687 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7843 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2077 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3329 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 693 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22457 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 553 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21026 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 47090 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 47074 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 16907 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.131098 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.633089 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7993 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3065 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3795 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1928 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 26201 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1928 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8331 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1936 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3571 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 699 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24623 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 40 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 586 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 22939 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51440 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 51424 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9368 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11658 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13571 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 33 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1820 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2219 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1751 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20306 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 16792 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 10001 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12754 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16182 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.037696 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.845376 # Number of insts issued each cycle +system.cpu.rename.skidInsts 1885 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2380 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1795 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21756 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17955 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11342 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13993 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.061986 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.892645 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10903 67.38% 67.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1372 8.48% 75.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1062 6.56% 82.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 680 4.20% 86.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 659 4.07% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 684 4.23% 94.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 588 3.63% 98.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 200 1.24% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 34 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11435 67.63% 67.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1387 8.20% 75.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1028 6.08% 81.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 682 4.03% 85.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 697 4.12% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 717 4.24% 94.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 667 3.95% 98.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 261 1.54% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16182 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16907 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 86 64.66% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 24 18.05% 82.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 17.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 147 74.24% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 30 15.15% 89.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 21 10.61% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13517 80.50% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1828 10.89% 91.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1443 8.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14483 80.66% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1993 11.10% 91.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1475 8.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 16792 # Type of FU issued -system.cpu.iq.rate 0.700250 # Inst issue rate -system.cpu.iq.fu_busy_cnt 133 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 49947 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30352 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15608 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17955 # Type of FU issued +system.cpu.iq.rate 0.729878 # Inst issue rate +system.cpu.iq.fu_busy_cnt 198 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53081 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33143 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16452 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 16917 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18145 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 142 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 152 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 12 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 817 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1324 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 861 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1687 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1417 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20343 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 26 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2219 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1751 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1928 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21795 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2380 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1795 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 35 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 590 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 15942 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 850 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 653 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 716 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16888 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1067 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3065 # number of memory reference insts executed -system.cpu.iew.exec_branches 1589 # Number of branches executed -system.cpu.iew.exec_stores 1340 # Number of stores executed -system.cpu.iew.exec_rate 0.664804 # Inst execution rate -system.cpu.iew.wb_sent 15766 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15612 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10251 # num instructions producing a value -system.cpu.iew.wb_consumers 15131 # num instructions consuming a value +system.cpu.iew.exec_refs 3212 # number of memory reference insts executed +system.cpu.iew.exec_branches 1649 # Number of branches executed +system.cpu.iew.exec_stores 1365 # Number of stores executed +system.cpu.iew.exec_rate 0.686504 # Inst execution rate +system.cpu.iew.wb_sent 16662 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16456 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10670 # num instructions producing a value +system.cpu.iew.wb_consumers 15796 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back +system.cpu.iew.wb_rate 0.668943 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.675487 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11985 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14495 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.676716 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510487 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14979 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.654850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.499757 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10831 74.72% 74.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1349 9.31% 84.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 680 4.69% 88.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 780 5.38% 94.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 337 2.32% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.89% 97.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 140 0.97% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 65 0.45% 98.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 184 1.27% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11331 75.65% 75.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1373 9.17% 84.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 652 4.35% 89.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 726 4.85% 94.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 372 2.48% 96.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 130 0.87% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 138 0.92% 98.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 68 0.45% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 189 1.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14979 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -269,62 +269,62 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 184 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 34653 # The number of ROB reads -system.cpu.rob.rob_writes 42403 # The number of ROB writes +system.cpu.rob.rob_reads 36584 # The number of ROB reads +system.cpu.rob.rob_writes 45550 # The number of ROB writes system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7693 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads -system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 23430 # number of integer regfile reads -system.cpu.int_regfile_writes 14518 # number of integer regfile writes +system.cpu.cpi 4.542097 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.542097 # CPI: Total CPI of All Threads +system.cpu.ipc 0.220163 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.220163 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24791 # number of integer regfile reads +system.cpu.int_regfile_writes 15157 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.misc_regfile_reads 7406 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 140.870525 # Cycle average of tags in use -system.cpu.icache.total_refs 1498 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 146.671178 # Cycle average of tags in use +system.cpu.icache.total_refs 1576 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.184211 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits -system.cpu.icache.overall_hits::total 1498 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses -system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 146.671178 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071617 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071617 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1576 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1576 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1576 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1576 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1576 # number of overall hits +system.cpu.icache.overall_hits::total 1576 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 392 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 392 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 392 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 392 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 392 # number of overall misses +system.cpu.icache.overall_misses::total 392 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13905000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13905000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13905000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13905000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13905000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13905000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1968 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1968 # 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number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -333,80 +333,80 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10684500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10684500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10684500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10684500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154472 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35146.381579 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35146.381579 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.091432 # Cycle average of tags in use +system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.526549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020392 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1417 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1417 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 85.091432 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020774 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits -system.cpu.dcache.overall_hits::total 2275 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits +system.cpu.dcache.overall_hits::total 2365 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 187 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 187 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 187 # number of overall misses -system.cpu.dcache.overall_misses::total 187 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3859500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3859500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2916500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2916500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6776000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6776000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6776000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1528 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1528 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 193 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 193 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 193 # number of overall misses +system.cpu.dcache.overall_misses::total 193 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4056500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4056500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6974000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6974000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6974000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1624 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1624 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2462 # 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miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38375 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.075450 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075450 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34670.940171 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36134.715026 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,101 +415,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 41 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 41 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 41 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 70 # 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number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2463000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2688500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5151500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5151500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045812 # 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miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 453 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 453 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993421 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993289 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993421 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993289 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993421 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.847682 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34061.643836 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34250 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.847682 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34157.718121 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -518,42 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # 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number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11655500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2369500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9393500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4631500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14025000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9393500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4631500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14025000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31104.304636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30986.301370 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31104.304636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31083.892617 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |