diff options
Diffstat (limited to 'tests/quick/se/00.hello')
48 files changed, 4222 insertions, 4216 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini index 5cc0911e9..e1fc4e09c 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout index b9f1a2caf..da63093c1 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:15:31 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:18 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 21234500 because target called exit() +Exiting @ tick 21985500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 6887d118d..b38d65b68 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21234500 # Number of ticks simulated -final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21985500 # Number of ticks simulated +final_tick 21985500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73768 # Simulator instruction rate (inst/s) -host_op_rate 73752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 244499363 # Simulator tick rate (ticks/s) -host_mem_usage 214444 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 65949 # Simulator instruction rate (inst/s) +host_op_rate 65938 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 226330541 # Simulator tick rate (ticks/s) +host_mem_usage 218192 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 469 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 907202901 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 506345805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1413548706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 907202901 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 907202901 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 506345805 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1413548706 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 876213868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 489049601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365263469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 876213868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 876213868 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 876213868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 489049601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1365263469 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -35,14 +35,14 @@ system.cpu.dtb.read_hits 1186 # DT system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations system.cpu.dtb.read_accesses 1193 # DTB read accesses -system.cpu.dtb.write_hits 898 # DTB write hits +system.cpu.dtb.write_hits 900 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 901 # DTB write accesses -system.cpu.dtb.data_hits 2084 # DTB hits +system.cpu.dtb.write_accesses 903 # DTB write accesses +system.cpu.dtb.data_hits 2086 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2094 # DTB accesses +system.cpu.dtb.data_accesses 2096 # DTB accesses system.cpu.itb.fetch_hits 908 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv @@ -60,26 +60,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 42470 # number of cpu cycles simulated +system.cpu.numCycles 43972 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1608 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1607 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1126 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 1143 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5212 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9792 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2971 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2183 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken). @@ -90,12 +90,12 @@ system.cpu.execution_unit.executions 4474 # Nu system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 12078 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7391 # Number of cycles cpu stages are processed. -system.cpu.activity 17.402873 # Percentage of cycles cpu is active +system.cpu.timesIdled 536 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 36557 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7415 # Number of cycles cpu stages are processed. +system.cpu.activity 16.863004 # Percentage of cycles cpu is active system.cpu.comLoads 1185 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1051 # Number of Branches instructions committed @@ -107,72 +107,72 @@ system.cpu.committedInsts 6404 # Nu system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total) -system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.866334 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.866334 # CPI: Total CPI of All Threads +system.cpu.ipc 0.145638 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.145638 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 39051 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4921 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 11.191213 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 40084 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3888 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.841990 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 39791 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4181 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.508323 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42630 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1342 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.051942 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 39502 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4470 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 10.165560 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use -system.cpu.icache.total_refs 558 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 138.644500 # Cycle average of tags in use +system.cpu.icache.total_refs 557 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.850498 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits -system.cpu.icache.overall_hits::total 558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles +system.cpu.icache.occ_blocks::cpu.inst 138.644500 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.067698 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.067698 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 557 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 557 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 557 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 557 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 557 # number of overall hits +system.cpu.icache.overall_hits::total 557 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 351 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 351 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 351 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 351 # number of overall misses +system.cpu.icache.overall_misses::total 351 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19781500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19781500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19781500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19781500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19781500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19781500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55267.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55267.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55267.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.386564 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.386564 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.386564 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.386564 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.386564 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.386564 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56357.549858 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56357.549858 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56357.549858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56357.549858 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56357.549858 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -181,70 +181,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 49 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 49 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 49 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 49 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 49 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16493500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16493500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16493500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16493500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53150.662252 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53150.662252 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54614.238411 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54614.238411 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use -system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 102.468585 # Cycle average of tags in use +system.cpu.dcache.total_refs 1702 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 10.130952 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 102.468585 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025017 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025017 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits -system.cpu.dcache.overall_hits::total 1703 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 614 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1702 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1702 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1702 # number of overall hits +system.cpu.dcache.overall_hits::total 1702 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses -system.cpu.dcache.overall_misses::total 347 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 251 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 251 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 348 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses +system.cpu.dcache.overall_misses::total 348 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5918000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5918000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15290000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15290000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 21208000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 21208000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 21208000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 21208000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -255,36 +255,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2050 system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.081857 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289017 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.169268 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.169268 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56778.350515 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54220 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54935.158501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54935.158501 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.169756 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.169756 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.169756 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.169756 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60916.334661 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60942.528736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60942.528736 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60942.528736 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1689000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 45648.648649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 178 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 178 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 180 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -293,14 +293,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5509500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4096500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4096500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9606000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9606000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9606000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -309,26 +309,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 system.cpu.dcache.demand_mshr_miss_rate::total 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.081951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53821.052632 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53554.794521 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53705.357143 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56116.438356 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 194.857279 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.715070 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.142209 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004233 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001713 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005947 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -346,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16152000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21542000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9397500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 25549500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9397500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25549500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -379,17 +379,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52277.777778 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52349.315068 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52288.912580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52288.912580 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53661.129568 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56736.842105 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54398.989899 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54897.260274 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54897.260274 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54476.545842 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53661.129568 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55937.500000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54476.545842 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -409,17 +409,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12487000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4239000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16726000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3129500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3129500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12487000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19855500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12487000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19855500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -431,17 +431,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40092.171717 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40308.219178 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40125.799574 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41485.049834 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44621.052632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42237.373737 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42869.863014 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42869.863014 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41485.049834 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43860.119048 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42335.820896 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini index 280f44c05..fb11f0585 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index da5dd186c..809102793 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:21 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:18 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12146500 because target called exit() +Exiting @ tick 12811000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 40a9fef11..37f1f46b0 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12146500 # Number of ticks simulated -final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12811000 # Number of ticks simulated +final_tick 12811000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109785 # Simulator instruction rate (inst/s) -host_op_rate 109750 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 208686624 # Simulator tick rate (ticks/s) -host_mem_usage 218220 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 61639 # Simulator instruction rate (inst/s) +host_op_rate 61622 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 123585600 # Simulator tick rate (ticks/s) +host_mem_usage 219212 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory -system.physmem.bytes_read::total 31232 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 488 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory +system.physmem.bytes_read::total 31296 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory +system.physmem.num_reads::total 489 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1568651940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 874248693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2442900632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1568651940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1568651940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1568651940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 874248693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2442900632 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1978 # DTB read hits -system.cpu.dtb.read_misses 49 # DTB read misses +system.cpu.dtb.read_hits 1966 # DTB read hits +system.cpu.dtb.read_misses 45 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2027 # DTB read accesses +system.cpu.dtb.read_accesses 2011 # DTB read accesses system.cpu.dtb.write_hits 1059 # DTB write hits -system.cpu.dtb.write_misses 31 # DTB write misses +system.cpu.dtb.write_misses 28 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1090 # DTB write accesses -system.cpu.dtb.data_hits 3037 # DTB hits -system.cpu.dtb.data_misses 80 # DTB misses +system.cpu.dtb.write_accesses 1087 # DTB write accesses +system.cpu.dtb.data_hits 3025 # DTB hits +system.cpu.dtb.data_misses 73 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3117 # DTB accesses -system.cpu.itb.fetch_hits 2279 # ITB hits -system.cpu.itb.fetch_misses 30 # ITB misses +system.cpu.dtb.data_accesses 3098 # DTB accesses +system.cpu.itb.fetch_hits 2254 # ITB hits +system.cpu.itb.fetch_misses 39 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2309 # ITB accesses +system.cpu.itb.fetch_accesses 2293 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24294 # number of cpu cycles simulated +system.cpu.numCycles 25623 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2808 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits +system.cpu.BPredUnit.lookups 2750 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1591 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 527 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2077 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 402 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 69 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8523 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15693 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2750 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1150 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2817 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1761 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 996 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 745 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2254 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 361 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14299 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.097489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.491166 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11482 80.30% 80.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 287 2.01% 82.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 235 1.64% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.55% 85.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 257 1.80% 87.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 195 1.36% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 267 1.87% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 172 1.20% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1183 8.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2684 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14299 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107325 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.612458 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9448 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2627 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1110 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 255 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 14531 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2519 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups +system.cpu.rename.SquashCycles 1110 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9647 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 356 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2494 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 313 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13871 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 268 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10378 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17332 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 5795 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 32 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 762 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2605 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1307 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12446 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10341 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5740 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3350 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14299 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.723197 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.354818 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9905 69.27% 69.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1622 11.34% 80.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1176 8.22% 88.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 704 4.92% 93.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 444 3.11% 96.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 263 1.84% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 141 0.99% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34 0.24% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14299 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 7.27% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.27% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 65 59.09% 66.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 37 33.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7000 67.69% 67.71% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.72% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2210 21.37% 89.11% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1126 10.89% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10419 # Type of FU issued -system.cpu.iq.rate 0.428871 # Inst issue rate -system.cpu.iq.fu_busy_cnt 108 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10341 # Type of FU issued +system.cpu.iq.rate 0.403583 # Inst issue rate +system.cpu.iq.fu_busy_cnt 110 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010637 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35107 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18223 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9409 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10438 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1420 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 442 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1110 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 12564 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 188 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2605 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1307 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 139 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2022 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 545 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 83 # number of nop insts executed -system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_nop 88 # number of nop insts executed +system.cpu.iew.exec_refs 3112 # number of memory reference insts executed system.cpu.iew.exec_branches 1595 # Number of branches executed -system.cpu.iew.exec_stores 1093 # Number of stores executed -system.cpu.iew.exec_rate 0.405244 # Inst execution rate -system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9443 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4951 # num instructions producing a value -system.cpu.iew.wb_consumers 6720 # num instructions consuming a value +system.cpu.iew.exec_stores 1090 # Number of stores executed +system.cpu.iew.exec_rate 0.382313 # Inst execution rate +system.cpu.iew.wb_sent 9558 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9419 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4945 # num instructions producing a value +system.cpu.iew.wb_consumers 6634 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back +system.cpu.iew.wb_rate 0.367599 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.745402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6160 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 444 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13189 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485480 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.291478 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10357 78.53% 78.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1540 11.68% 90.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 523 3.97% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 223 1.69% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 163 1.24% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 109 0.83% 97.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.80% 98.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 29 0.22% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 139 1.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13189 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,70 +310,70 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 139 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24228 # The number of ROB reads -system.cpu.rob.rob_writes 26471 # The number of ROB writes -system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25262 # The number of ROB reads +system.cpu.rob.rob_writes 26244 # The number of ROB writes +system.cpu.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11324 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads -system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12506 # number of integer regfile reads -system.cpu.int_regfile_writes 7104 # number of integer regfile writes +system.cpu.cpi 4.012371 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.012371 # CPI: Total CPI of All Threads +system.cpu.ipc 0.249229 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249229 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12434 # number of integer regfile reads +system.cpu.int_regfile_writes 7077 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use -system.cpu.icache.total_refs 1829 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 159.968477 # Cycle average of tags in use +system.cpu.icache.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.714286 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits -system.cpu.icache.overall_hits::total 1829 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses -system.cpu.icache.overall_misses::total 450 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 159.968477 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078110 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078110 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits +system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses +system.cpu.icache.overall_misses::total 454 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16294000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16294000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16294000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16294000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16294000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16294000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2254 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2254 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2254 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2254 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2254 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.201420 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.201420 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.201420 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.201420 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.201420 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.201420 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35889.867841 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35889.867841 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35889.867841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35889.867841 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,94 +382,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 139 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 139 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 139 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 139 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11617000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.139752 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.139752 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.139752 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36879.365079 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36879.365079 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use -system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.786985 # Cycle average of tags in use +system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2275 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 107.786985 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026315 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026315 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits +system.cpu.dcache.overall_hits::total 2240 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 161 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 161 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 520 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 520 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 520 # 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number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084960 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084960 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188406 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188406 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188406 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188406 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39888.198758 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39888.198758 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41917.827298 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41917.827298 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41289.423077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41289.423077 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,119 +478,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054393 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 175 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2874500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2874500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7111000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7111000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7111000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7111000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063406 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063406 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41534.313725 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41534.313725 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39376.712329 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39376.712329 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40634.285714 # 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number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 176 # 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number of overall misses +system.cpu.l2cache.overall_misses::total 489 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11286500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4103500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 15390000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2793500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2793500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11286500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6897000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18183500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11286500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6897000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18183500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 175 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 490 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 175 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 490 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997959 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997959 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35944.267516 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40230.392157 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36995.192308 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38267.123288 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38267.123288 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37185.071575 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37185.071575 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10285500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3793000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14078500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2567500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2567500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10285500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6360500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16646000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10285500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6360500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16646000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32756.369427 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37186.274510 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33842.548077 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini index b0aed7d88..4b13e207f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout index 00df1b420..776a435c2 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:52:31 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:22 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 33007000 because target called exit() +Exiting @ tick 34425000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index 0370e845f..a9d405edb 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 33007000 # Number of ticks simulated -final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000034 # Number of seconds simulated +sim_ticks 34425000 # Number of ticks simulated +final_tick 34425000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 524144 # Simulator instruction rate (inst/s) -host_op_rate 523337 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2693393609 # Simulator tick rate (ticks/s) -host_mem_usage 214140 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 6722 # Simulator instruction rate (inst/s) +host_op_rate 6722 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36133024 # Simulator tick rate (ticks/s) +host_mem_usage 217168 # Number of bytes of host memory used +host_seconds 0.95 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 539037174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 325749084 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 864786257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 539037174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 539037174 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 539037174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 325749084 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 864786257 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 516833696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 312331155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 829164851 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 516833696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516833696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 516833696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 312331155 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 829164851 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 66014 # number of cpu cycles simulated +system.cpu.numCycles 68850 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6404 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 2060 # nu system.cpu.num_load_insts 1192 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 66014 # Number of busy cycles +system.cpu.num_busy_cycles 68850 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use +system.cpu.icache.tagsinuse 128.155444 # Cycle average of tags in use system.cpu.icache.total_refs 6136 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 128.155444 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.062576 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.062576 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 103.856385 # Cycle average of tags in use system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.680615 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025313 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025313 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 103.856385 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025356 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025356 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1090 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1090 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 184.699061 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 127.900723 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.441756 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003903 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005626 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 128.168283 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.530778 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003911 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001725 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005637 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini index 3b6b2b818..0de3d5fa0 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 2586fc610..07442c5d8 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:32 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:29 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 6934000 because target called exit() +Exiting @ tick 7252000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 729742f8d..572203942 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 6934000 # Number of ticks simulated -final_tick 6934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 7252000 # Number of ticks simulated +final_tick 7252000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29510 # Simulator instruction rate (inst/s) -host_op_rate 29504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85688409 # Simulator tick rate (ticks/s) -host_mem_usage 217944 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 57662 # Simulator instruction rate (inst/s) +host_op_rate 57638 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175044086 # Simulator tick rate (ticks/s) +host_mem_usage 217908 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory @@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total 12032 # Nu system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1735217768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 784539948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2519757716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1735217768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1735217768 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1735217768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 784539948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2519757716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1659128516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 750137893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2409266409 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1659128516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1659128516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1659128516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 750137893 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2409266409 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 704 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 712 # DTB read hits +system.cpu.dtb.read_misses 13 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 740 # DTB read accesses -system.cpu.dtb.write_hits 367 # DTB write hits -system.cpu.dtb.write_misses 22 # DTB write misses +system.cpu.dtb.read_accesses 725 # DTB read accesses +system.cpu.dtb.write_hits 368 # DTB write hits +system.cpu.dtb.write_misses 15 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 389 # DTB write accesses -system.cpu.dtb.data_hits 1071 # DTB hits -system.cpu.dtb.data_misses 58 # DTB misses +system.cpu.dtb.write_accesses 383 # DTB write accesses +system.cpu.dtb.data_hits 1080 # DTB hits +system.cpu.dtb.data_misses 28 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1129 # DTB accesses -system.cpu.itb.fetch_hits 999 # ITB hits +system.cpu.dtb.data_accesses 1108 # DTB accesses +system.cpu.itb.fetch_hits 1014 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1029 # ITB accesses +system.cpu.itb.fetch_accesses 1044 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 13869 # number of cpu cycles simulated +system.cpu.numCycles 14505 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1119 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 563 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 252 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 783 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 216 # Number of BTB hits +system.cpu.BPredUnit.lookups 1131 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 573 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 253 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 782 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 218 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6858 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1119 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 426 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1175 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 850 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 242 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 211 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 37 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 4349 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6900 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1131 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 429 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1183 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 857 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 264 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 783 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 170 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.037362 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.461313 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 948 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1014 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 172 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.939926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.361375 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5436 82.23% 82.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 51 0.77% 83.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 129 1.95% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 97 1.47% 86.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 136 2.06% 88.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 62 0.94% 89.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 66 1.00% 90.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.97% 91.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 570 8.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6158 83.89% 83.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 84.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.76% 86.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 101 1.38% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 139 1.89% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62 0.84% 90.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 0.90% 91.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 61 0.83% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 575 7.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6611 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.080684 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.494484 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4718 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 256 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1133 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6102 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 7341 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.077973 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.475698 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5395 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 291 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 13 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 501 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6151 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 67 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1046 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 43 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5849 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4252 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6619 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6607 # Number of integer rename lookups +system.cpu.rename.SquashCycles 501 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5491 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 66 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 174 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1058 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 51 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5908 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4280 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6676 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6664 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2484 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2512 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 137 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 945 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 145 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 960 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 476 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 5051 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2372 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1428 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1510 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6611 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608985 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.321430 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7341 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.548427 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.241979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 4990 75.48% 75.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 583 8.82% 84.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 382 5.78% 90.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 267 4.04% 94.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 192 2.90% 97.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 114 1.72% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 53 0.80% 99.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 18 0.27% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5680 77.37% 77.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 617 8.40% 85.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 387 5.27% 91.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 273 3.72% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 114 1.55% 99.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 56 0.76% 99.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.14% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 6 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7341 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 9.09% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 17 38.64% 47.73% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2 4.88% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 41.46% 46.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 53.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2853 70.86% 70.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 775 19.25% 90.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 397 9.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2876 71.44% 71.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 761 18.90% 90.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 388 9.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 4026 # Type of FU issued -system.cpu.iq.rate 0.290288 # Inst issue rate -system.cpu.iq.fu_busy_cnt 44 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010929 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 14762 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7351 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3682 # Number of integer instruction queue wakeup accesses +system.cpu.iq.rate 0.277559 # Inst issue rate +system.cpu.iq.fu_busy_cnt 41 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010184 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15500 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3688 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4063 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4060 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 530 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 545 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 182 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5319 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 96 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 945 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 501 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5407 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 98 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 960 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 476 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 57 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 150 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3873 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 741 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 3874 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 152 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 338 # number of nop insts executed -system.cpu.iew.exec_refs 1130 # number of memory reference insts executed -system.cpu.iew.exec_branches 650 # Number of branches executed -system.cpu.iew.exec_stores 389 # Number of stores executed -system.cpu.iew.exec_rate 0.279256 # Inst execution rate -system.cpu.iew.wb_sent 3778 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3688 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1732 # num instructions producing a value -system.cpu.iew.wb_consumers 2249 # num instructions consuming a value +system.cpu.iew.exec_nop 350 # number of nop insts executed +system.cpu.iew.exec_refs 1109 # number of memory reference insts executed +system.cpu.iew.exec_branches 649 # Number of branches executed +system.cpu.iew.exec_stores 383 # Number of stores executed +system.cpu.iew.exec_rate 0.267080 # Inst execution rate +system.cpu.iew.wb_sent 3756 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3694 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1740 # num instructions producing a value +system.cpu.iew.wb_consumers 2202 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.265917 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.770120 # average fanout of values written-back +system.cpu.iew.wb_rate 0.254671 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.790191 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 2738 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2822 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 172 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6117 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.421121 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.275697 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6840 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.376608 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.225423 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5226 85.43% 85.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 218 3.56% 89.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 319 5.21% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 117 1.91% 96.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 69 1.13% 97.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 56 0.92% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 32 0.52% 98.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 19 0.31% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 61 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5956 87.08% 87.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 217 3.17% 90.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 318 4.65% 94.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 115 1.68% 96.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 67 0.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 47 0.69% 98.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.47% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 21 0.31% 99.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 67 0.98% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6840 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,69 +310,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 67 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11123 # The number of ROB reads -system.cpu.rob.rob_writes 11131 # The number of ROB writes -system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7258 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11924 # The number of ROB reads +system.cpu.rob.rob_writes 11305 # The number of ROB writes +system.cpu.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.810222 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.810222 # CPI: Total CPI of All Threads -system.cpu.ipc 0.172110 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.172110 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4695 # number of integer regfile reads -system.cpu.int_regfile_writes 2856 # number of integer regfile writes +system.cpu.cpi 6.076665 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.076665 # CPI: Total CPI of All Threads +system.cpu.ipc 0.164564 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.164564 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4677 # number of integer regfile reads +system.cpu.int_regfile_writes 2861 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.248355 # Cycle average of tags in use -system.cpu.icache.total_refs 752 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 94.201337 # Cycle average of tags in use +system.cpu.icache.total_refs 769 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.090426 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.248355 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045531 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045531 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 752 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 752 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 752 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 752 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 752 # number of overall hits -system.cpu.icache.overall_hits::total 752 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 247 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 247 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 247 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 247 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 247 # number of overall misses -system.cpu.icache.overall_misses::total 247 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8946000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8946000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8946000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8946000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8946000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8946000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.247247 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.247247 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.247247 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.247247 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.247247 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.247247 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36218.623482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36218.623482 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 94.201337 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045997 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045997 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 769 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 769 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 769 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 769 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 769 # number of overall hits +system.cpu.icache.overall_hits::total 769 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 245 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 245 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 245 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 245 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 245 # number of overall misses +system.cpu.icache.overall_misses::total 245 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 9112500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 9112500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 9112500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 9112500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 9112500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 9112500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1014 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1014 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1014 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1014 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1014 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1014 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241617 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241617 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241617 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241617 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241617 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241617 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37193.877551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37193.877551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37193.877551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37193.877551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37193.877551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6660500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188188 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.188188 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.188188 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6932500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6932500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6932500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6932500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.185404 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.185404 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.185404 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.185404 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36875 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36875 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36875 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36875 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 45.780075 # Cycle average of tags in use -system.cpu.dcache.total_refs 785 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.851495 # Cycle average of tags in use +system.cpu.dcache.total_refs 774 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.235294 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.105882 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 45.780075 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011177 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 563 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 563 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 785 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 785 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 785 # number of overall hits -system.cpu.dcache.overall_hits::total 785 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 110 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 110 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses -system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3679000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3679000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2813500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2813500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 673 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 45.851495 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011194 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011194 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 561 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 561 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 774 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 774 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 774 # number of overall hits +system.cpu.dcache.overall_hits::total 774 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4328500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4328500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3561500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3561500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7890000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7890000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7890000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7890000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 967 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 967 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 967 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 967 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.163447 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.163447 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188211 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188211 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188211 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188211 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35673.076923 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 973 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 973 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 973 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 973 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.173785 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.204522 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.204522 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.204522 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.204522 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36682.203390 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36682.203390 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43969.135802 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43969.135802 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39648.241206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39648.241206 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39648.241206 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,14 +477,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -493,42 +493,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2166000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2166000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 871000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 871000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3037000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3037000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3037000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3037000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090639 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2511500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 981000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 981000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3492500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3492500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3492500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3492500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089838 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089838 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.087901 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.087901 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087359 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087359 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087359 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41172.131148 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41172.131148 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40875 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40875 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41088.235294 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 41088.235294 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.119430 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 123.109780 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.334885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.784545 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002848 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000878 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003727 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 94.284624 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.825156 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002877 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000880 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003757 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses @@ -540,17 +540,17 @@ system.cpu.l2cache.demand_misses::total 273 # nu system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6449000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2098500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8547500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 830000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 830000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6449000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2928500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9377500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6449000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2928500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9377500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6740500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2447000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9187500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 950000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 950000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6740500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3397000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10137500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6740500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3397000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10137500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35853.723404 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40114.754098 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36897.590361 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39583.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37133.699634 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35853.723404 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39964.705882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37133.699634 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -603,17 +603,17 @@ system.cpu.l2cache.demand_mshr_misses::total 273 system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5849000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1904500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7753500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 755000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 755000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5849000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8508500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5849000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8508500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6136500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2258000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8394500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 876000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 876000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6136500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3134000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9270500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6136500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3134000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9270500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.957447 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37016.393443 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33712.851406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.957447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36870.588235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33957.875458 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini index 3d54d7382..b94afa836 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout index 803a08b4e..95893429b 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:41 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:33 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 16769000 because target called exit() +Exiting @ tick 17541000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index fab613981..aabb78aae 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16769000 # Number of ticks simulated -final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17541000 # Number of ticks simulated +final_tick 17541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 308591 # Simulator instruction rate (inst/s) -host_op_rate 307918 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1999557615 # Simulator tick rate (ticks/s) -host_mem_usage 213304 # Number of bytes of host memory used +host_inst_rate 207586 # Simulator instruction rate (inst/s) +host_op_rate 207300 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1409208031 # Simulator tick rate (ticks/s) +host_mem_usage 216876 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 622100304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 312958435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 935058739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 622100304 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 622100304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 312958435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 935058739 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 594720940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299184767 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 893905707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 594720940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 594720940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 594720940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299184767 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 893905707 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -60,7 +60,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33538 # number of cpu cycles simulated +system.cpu.numCycles 35082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -79,18 +79,18 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33538 # Number of busy cycles +system.cpu.num_busy_cycles 35082 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use +system.cpu.icache.tagsinuse 80.027768 # Cycle average of tags in use system.cpu.icache.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 80.027768 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.039076 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.039076 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits @@ -161,14 +161,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 47.439715 # Cycle average of tags in use system.cpu.dcache.total_refs 627 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 47.418751 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011577 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011577 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 47.439715 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011582 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011582 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits @@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 107.121835 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 80.120406 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.980800 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002445 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 80.139278 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.982557 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000823 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003268 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003269 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 218 # number of ReadReq misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index d0f59b4b6..f2874fc12 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -556,7 +556,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port @@ -588,7 +588,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index c374c028c..3b3dd4083 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:34:53 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:18:47 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10305000 because target called exit() +Exiting @ tick 10843000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 9b64fc302..e9752a794 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10305000 # Number of ticks simulated -final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 10843000 # Number of ticks simulated +final_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40668 # Simulator instruction rate (inst/s) -host_op_rate 50741 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91257316 # Simulator tick rate (ticks/s) -host_mem_usage 232684 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 27388 # Simulator instruction rate (inst/s) +host_op_rate 34173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64670790 # Simulator tick rate (ticks/s) +host_mem_usage 232736 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -115,245 +115,245 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20611 # number of cpu cycles simulated +system.cpu.numCycles 21687 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits +system.cpu.BPredUnit.lookups 2517 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 676 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2573 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2368 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2347 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle +system.cpu.rename.skidInsts 753 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9087 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9186 # Type of FU issued -system.cpu.iq.rate 0.445684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 217 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9087 # Type of FU issued +system.cpu.iq.rate 0.419007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3377 # number of memory reference insts executed -system.cpu.iew.exec_branches 1400 # Number of branches executed -system.cpu.iew.exec_stores 1208 # Number of stores executed -system.cpu.iew.exec_rate 0.423027 # Inst execution rate -system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8236 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3901 # num instructions producing a value -system.cpu.iew.wb_consumers 7899 # num instructions consuming a value +system.cpu.iew.exec_refs 3344 # number of memory reference insts executed +system.cpu.iew.exec_branches 1407 # Number of branches executed +system.cpu.iew.exec_stores 1204 # Number of stores executed +system.cpu.iew.exec_rate 0.399318 # Inst execution rate +system.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8190 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3858 # num instructions producing a value +system.cpu.iew.wb_consumers 7806 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back +system.cpu.iew.wb_rate 0.377646 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -364,69 +364,69 @@ system.cpu.commit.branches 944 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22509 # The number of ROB reads -system.cpu.rob.rob_writes 24591 # The number of ROB writes -system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23828 # The number of ROB reads +system.cpu.rob.rob_writes 24602 # The number of ROB writes +system.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads -system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40006 # number of integer regfile reads -system.cpu.int_regfile_writes 8113 # number of integer regfile writes +system.cpu.cpi 4.723807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211694 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39657 # number of integer regfile reads +system.cpu.int_regfile_writes 8076 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15846 # number of misc regfile reads +system.cpu.misc_regfile_reads 15863 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use -system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use +system.cpu.icache.total_refs 1630 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits -system.cpu.icache.overall_hits::total 1637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits +system.cpu.icache.overall_hits::total 1630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses +system.cpu.icache.overall_misses::total 367 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -435,110 +435,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use +system.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits -system.cpu.dcache.overall_hits::total 2425 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2382 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2382 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2382 # number of overall hits +system.cpu.dcache.overall_hits::total 2382 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses -system.cpu.dcache.overall_misses::total 477 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses +system.cpu.dcache.overall_misses::total 501 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6900500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6900500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12710500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12710500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19611000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19611000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1970 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173777 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173777 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173777 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -547,16 +547,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -565,73 +565,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054315 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.907865 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37129.950495 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -673,56 +673,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # 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number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13605500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4515500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13605500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.883375 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 693c71c0c..9e38ceef5 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -497,7 +497,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -529,7 +529,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 8b9162b5e..b7b5be837 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:34:42 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:18:36 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10305000 because target called exit() +Exiting @ tick 10843000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index e182dd250..260f325f8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10305000 # Number of ticks simulated -final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000011 # Number of seconds simulated +sim_ticks 10843000 # Number of ticks simulated +final_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 29768 # Simulator instruction rate (inst/s) -host_op_rate 37142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66801597 # Simulator tick rate (ticks/s) -host_mem_usage 232684 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 17631 # Simulator instruction rate (inst/s) +host_op_rate 22000 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41635778 # Simulator tick rate (ticks/s) +host_mem_usage 232604 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25536 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 399 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 398 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,245 +70,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20611 # number of cpu cycles simulated +system.cpu.numCycles 21687 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2522 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits +system.cpu.BPredUnit.lookups 2517 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 676 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12862 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1997 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2573 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2368 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2347 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 45 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 46 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle +system.cpu.rename.skidInsts 753 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9087 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9186 # Type of FU issued -system.cpu.iq.rate 0.445684 # Inst issue rate -system.cpu.iq.fu_busy_cnt 217 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9087 # Type of FU issued +system.cpu.iq.rate 0.419007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3377 # number of memory reference insts executed -system.cpu.iew.exec_branches 1400 # Number of branches executed -system.cpu.iew.exec_stores 1208 # Number of stores executed -system.cpu.iew.exec_rate 0.423027 # Inst execution rate -system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8236 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3901 # num instructions producing a value -system.cpu.iew.wb_consumers 7899 # num instructions consuming a value +system.cpu.iew.exec_refs 3344 # number of memory reference insts executed +system.cpu.iew.exec_branches 1407 # Number of branches executed +system.cpu.iew.exec_stores 1204 # Number of stores executed +system.cpu.iew.exec_rate 0.399318 # Inst execution rate +system.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8190 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3858 # num instructions producing a value +system.cpu.iew.wb_consumers 7806 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back +system.cpu.iew.wb_rate 0.377646 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -319,69 +319,69 @@ system.cpu.commit.branches 944 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22509 # The number of ROB reads -system.cpu.rob.rob_writes 24591 # The number of ROB writes -system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23828 # The number of ROB reads +system.cpu.rob.rob_writes 24602 # The number of ROB writes +system.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads -system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 40006 # number of integer regfile reads -system.cpu.int_regfile_writes 8113 # number of integer regfile writes +system.cpu.cpi 4.723807 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211694 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39657 # number of integer regfile reads +system.cpu.int_regfile_writes 8076 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15846 # number of misc regfile reads +system.cpu.misc_regfile_reads 15863 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use -system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use +system.cpu.icache.total_refs 1630 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits -system.cpu.icache.overall_hits::total 1637 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits +system.cpu.icache.overall_hits::total 1630 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses +system.cpu.icache.overall_misses::total 367 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -390,110 +390,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10405500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148222 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use -system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use +system.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits -system.cpu.dcache.overall_hits::total 2425 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2382 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2382 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2382 # number of overall hits +system.cpu.dcache.overall_hits::total 2382 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses -system.cpu.dcache.overall_misses::total 477 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses +system.cpu.dcache.overall_misses::total 501 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6900500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6900500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12710500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12710500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19611000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19611000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19611000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1970 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency +system.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173777 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173777 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173777 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,16 +502,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -520,73 +520,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3667500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5380500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5380500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054315 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5027500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15000500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -598,28 +598,28 @@ system.cpu.l2cache.demand_accesses::total 445 # n system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935811 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,56 +628,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 6 # 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number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9090000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2983000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1532500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1532500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9090000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4515500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13605500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9090000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4515500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13605500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.883375 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index 89402c0d8..e19a07626 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -166,7 +166,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -198,7 +198,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index d4a066c4f..16fea9a8f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:26 +gem5 compiled Jul 2 2012 09:08:16 +gem5 started Jul 2 2012 15:19:21 gem5 executing on zizzer command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 26351000 because target called exit() +Exiting @ tick 27316000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index bac15b503..0ed449cb9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26351000 # Number of ticks simulated -final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27316000 # Number of ticks simulated +final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50718 # Simulator instruction rate (inst/s) -host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 292657577 # Simulator tick rate (ticks/s) -host_mem_usage 231660 # Number of bytes of host memory used +host_inst_rate 53670 # Simulator instruction rate (inst/s) +host_op_rate 66671 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 321019881 # Simulator tick rate (ticks/s) +host_mem_usage 231588 # Number of bytes of host memory used host_seconds 0.09 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 52702 # number of cpu cycles simulated +system.cpu.numCycles 54632 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -89,18 +89,18 @@ system.cpu.num_mem_refs 2138 # nu system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52702 # Number of busy cycles +system.cpu.num_busy_cycles 54632 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use +system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits @@ -171,14 +171,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini index ee123d638..3f1b44728 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 40197f717..3e33cecf6 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:16 +gem5 compiled Jul 2 2012 08:47:33 +gem5 started Jul 2 2012 11:28:42 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 19775000 because target called exit() +Exiting @ tick 20520000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 705e8dbde..615d61bce 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19775000 # Number of ticks simulated -final_tick 19775000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 20520000 # Number of ticks simulated +final_tick 20520000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79967 # Simulator instruction rate (inst/s) -host_op_rate 79947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271245925 # Simulator tick rate (ticks/s) -host_mem_usage 215348 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 67788 # Simulator instruction rate (inst/s) +host_op_rate 67774 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238625492 # Simulator tick rate (ticks/s) +host_mem_usage 219036 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1025941846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 446624526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1472566372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1025941846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1025941846 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1025941846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 446624526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1472566372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 988693957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 430409357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1419103314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 988693957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 988693957 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 988693957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 430409357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1419103314 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,27 +46,27 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 39551 # number of cpu cycles simulated +system.cpu.numCycles 41041 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1152 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 851 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1151 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 850 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 605 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 867 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 309 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 866 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 310 # Number of BTB hits system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 35.640138 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 402 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 750 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5104 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 35.796767 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 403 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 748 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5102 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3408 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8512 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8510 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1330 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2238 # Number of Address Generations +system.cpu.regfile_manager.regForwards 1331 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 2237 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 262 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 596 # Number of Branches Incorrectly Predicted @@ -76,12 +76,12 @@ system.cpu.execution_unit.executions 3155 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9142 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9765 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 404 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 34183 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5368 # Number of cycles cpu stages are processed. -system.cpu.activity 13.572350 # Percentage of cycles cpu is active +system.cpu.timesIdled 505 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35643 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5398 # Number of cycles cpu stages are processed. +system.cpu.activity 13.152701 # Percentage of cycles cpu is active system.cpu.comLoads 1164 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 916 # Number of Branches instructions committed @@ -93,72 +93,72 @@ system.cpu.committedInsts 5827 # Nu system.cpu.committedOps 5827 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions committed (Total) -system.cpu.cpi 6.787541 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.043247 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.787541 # CPI: Total CPI of All Threads -system.cpu.ipc 0.147329 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.043247 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141980 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.147329 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35911 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.203307 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 36722 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.141980 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37403 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3638 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 8.864306 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38212 # Number of cycles 0 instructions are processed. system.cpu.stage1.runCycles 2829 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.152790 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 36760 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2791 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.056712 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38308 # Number of cycles 0 instructions are processed. +system.cpu.stage1.utilization 6.893107 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38251 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2790 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 6.798080 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 39798 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1243 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.142778 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 36647 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.342419 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 3.028679 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38136 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2905 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.078288 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.175887 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.235290 # Cycle average of tags in use system.cpu.icache.total_refs 411 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.288401 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.175887 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072352 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072352 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.235290 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071892 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071892 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 411 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 411 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 411 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 411 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 411 # number of overall hits system.cpu.icache.overall_hits::total 411 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 343 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 343 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 343 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 343 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 343 # number of overall misses -system.cpu.icache.overall_misses::total 343 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19128500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19128500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19128500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19128500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19128500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19128500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.454907 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.454907 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.454907 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.454907 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.454907 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.454907 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55768.221574 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55768.221574 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55768.221574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55768.221574 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55768.221574 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses +system.cpu.icache.overall_misses::total 344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19612500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19612500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19612500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19612500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19612500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19612500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 755 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 755 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 755 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 755 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 755 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 755 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.455629 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.455629 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.455629 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.455629 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.455629 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.455629 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57013.081395 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 57013.081395 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 57013.081395 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 57013.081395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 57013.081395 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 57013.081395 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 29000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -167,70 +167,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 29000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 24 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 24 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 24 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 25 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16951500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16951500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16951500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16951500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16951500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16951500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53139.498433 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53139.498433 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53139.498433 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53139.498433 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17428000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17428000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17428000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17428000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17428000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17428000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.422517 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.422517 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.422517 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.422517 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54633.228840 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54633.228840 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54633.228840 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54633.228840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54633.228840 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54633.228840 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.746602 # Cycle average of tags in use -system.cpu.dcache.total_refs 1838 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.278998 # Cycle average of tags in use +system.cpu.dcache.total_refs 1835 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.318841 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.297101 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.746602 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021911 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021911 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1075 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1075 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 763 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 763 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1838 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1838 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1838 # number of overall hits -system.cpu.dcache.overall_hits::total 1838 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 162 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 162 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses -system.cpu.dcache.overall_misses::total 251 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5072500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5072500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8910500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8910500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13983000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13983000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13983000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13983000 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 89.278998 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021797 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021797 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1073 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1073 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 762 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1835 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1835 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1835 # number of overall hits +system.cpu.dcache.overall_hits::total 1835 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 163 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 163 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 254 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses +system.cpu.dcache.overall_misses::total 254 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5537000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5537000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10150000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10150000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15687000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15687000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15687000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15687000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -239,38 +239,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2089 # system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076460 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.175135 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.120153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.120153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.120153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.120153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56994.382022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55003.086420 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55003.086420 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55709.163347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55709.163347 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55709.163347 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078179 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078179 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.176216 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.176216 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.121589 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.121589 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.121589 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.121589 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60846.153846 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60846.153846 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61759.842520 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61759.842520 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61759.842520 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61759.842520 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1153500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1194500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51934.782609 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 111 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 111 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 112 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 112 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -279,14 +279,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4702500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2745500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7448000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7448000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7448000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7448000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5138000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2913500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2913500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8051500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8051500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8051500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8051500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -295,26 +295,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54051.724138 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53833.333333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53971.014493 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53971.014493 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59057.471264 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59057.471264 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58344.202899 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58344.202899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58344.202899 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58344.202899 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.517886 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 204.292602 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.817885 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.700002 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004572 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006272 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 148.846889 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.445713 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004542 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001692 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006235 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21170000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2682000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16585000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7267000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16585000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7267000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17060000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5021500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22081500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2843500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2843500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 17060000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7865000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24925000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 17060000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7865000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24925000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.611987 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52400.990099 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52588.235294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52588.235294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52421.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.611987 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52659.420290 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52421.978022 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53817.034700 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57718.390805 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54657.178218 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53817.034700 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56992.753623 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54780.219780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53817.034700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56992.753623 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54780.219780 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -395,17 +395,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13201000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3966500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17167500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2221000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2221000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13201000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19388500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13201000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19388500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -417,17 +417,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40215.346535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40352.941176 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40230.769231 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41643.533123 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45591.954023 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42493.811881 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43549.019608 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43549.019608 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41643.533123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44836.956522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42612.087912 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index a70bd3d3a..f6f1675ea 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -479,7 +479,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -511,7 +511,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index d99f33506..d96fc7f5c 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:52:53 +gem5 compiled Jul 2 2012 08:47:33 +gem5 started Jul 2 2012 11:28:53 gem5 executing on zizzer command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12478500 because target called exit() +Exiting @ tick 13016500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7981b4fdb..4a3a21e6c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12478500 # Number of ticks simulated -final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13016500 # Number of ticks simulated +final_tick 13016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84509 # Simulator instruction rate (inst/s) -host_op_rate 84485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 203899861 # Simulator tick rate (ticks/s) -host_mem_usage 220092 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54505 # Simulator instruction rate (inst/s) +host_op_rate 54495 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 137205108 # Simulator tick rate (ticks/s) +host_mem_usage 220060 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory system.physmem.bytes_read::total 30784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 21760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21760 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 340 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 481 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1671724350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 693273922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2364998271 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1671724350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1671724350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1671724350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 693273922 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2364998271 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24958 # number of cpu cycles simulated +system.cpu.numCycles 26034 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2172 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits +system.cpu.BPredUnit.lookups 2148 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1448 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 450 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1662 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 462 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 263 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8866 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13061 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2148 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 725 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3176 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1340 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 826 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.940114 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.257377 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10717 77.14% 77.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1298 9.34% 86.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 110 0.79% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 134 0.96% 88.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 300 2.16% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 103 0.74% 91.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 148 1.07% 92.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 126 0.91% 93.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 957 6.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3014 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 13893 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.082507 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.501690 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9037 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 974 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2996 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 835 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12168 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2873 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups +system.cpu.rename.SquashCycles 835 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9227 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 288 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2860 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 143 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11638 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7046 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13805 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13801 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3636 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 16 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 308 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2447 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9050 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8137 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3435 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1984 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.585691 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.249798 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10352 74.51% 74.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1446 10.41% 84.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 850 6.12% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 537 3.87% 94.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 350 2.52% 97.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 226 1.63% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 89 0.64% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 28 0.20% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13893 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4825 59.30% 59.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2212 27.18% 86.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1091 13.41% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8121 # Type of FU issued -system.cpu.iq.rate 0.325387 # Inst issue rate +system.cpu.iq.FU_type_0::total 8137 # Type of FU issued +system.cpu.iq.rate 0.312553 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018680 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30361 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12504 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7339 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8287 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewSquashCycles 835 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10551 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 78 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2447 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 378 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 479 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7784 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2096 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1469 # number of nop insts executed -system.cpu.iew.exec_refs 3191 # number of memory reference insts executed -system.cpu.iew.exec_branches 1304 # Number of branches executed -system.cpu.iew.exec_stores 1065 # Number of stores executed -system.cpu.iew.exec_rate 0.311163 # Inst execution rate -system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7294 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2836 # num instructions producing a value -system.cpu.iew.wb_consumers 4075 # num instructions consuming a value +system.cpu.iew.exec_nop 1489 # number of nop insts executed +system.cpu.iew.exec_refs 3163 # number of memory reference insts executed +system.cpu.iew.exec_branches 1325 # Number of branches executed +system.cpu.iew.exec_stores 1067 # Number of stores executed +system.cpu.iew.exec_rate 0.298994 # Inst execution rate +system.cpu.iew.wb_sent 7431 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7341 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2840 # num instructions producing a value +system.cpu.iew.wb_consumers 4066 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back +system.cpu.iew.wb_rate 0.281977 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.698475 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4721 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 404 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13058 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.446163 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.225344 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10619 81.32% 81.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1036 7.93% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 643 4.92% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 305 2.34% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 154 1.18% 97.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 84 0.64% 98.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 72 0.55% 98.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.30% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13058 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,69 +295,69 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22599 # The number of ROB reads -system.cpu.rob.rob_writes 21853 # The number of ROB writes -system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23486 # The number of ROB reads +system.cpu.rob.rob_writes 21936 # The number of ROB writes +system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 12141 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10560 # number of integer regfile reads -system.cpu.int_regfile_writes 5130 # number of integer regfile writes +system.cpu.cpi 5.036564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.036564 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198548 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198548 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10600 # number of integer regfile reads +system.cpu.int_regfile_writes 5152 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.misc_regfile_reads 155 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use -system.cpu.icache.total_refs 1503 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 163.172601 # Cycle average of tags in use +system.cpu.icache.total_refs 1511 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.405248 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits -system.cpu.icache.overall_hits::total 1503 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses -system.cpu.icache.overall_misses::total 435 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 163.172601 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079674 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079674 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1511 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1511 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1511 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1511 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1511 # number of overall hits +system.cpu.icache.overall_hits::total 1511 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses +system.cpu.icache.overall_misses::total 437 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15987000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15987000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15987000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15987000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15987000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15987000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224333 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.224333 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.224333 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.224333 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.224333 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.224333 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36583.524027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36583.524027 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -372,88 +372,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 94 system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 343 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 343 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 343 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 343 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 343 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12452000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12452000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12452000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12452000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12452000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12452000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176078 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.176078 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.176078 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36303.206997 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36303.206997 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use -system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.140441 # Cycle average of tags in use +system.cpu.dcache.total_refs 2441 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.312057 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits -system.cpu.dcache.overall_hits::total 2489 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses -system.cpu.dcache.overall_misses::total 472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 91.140441 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022251 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022251 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1863 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1863 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2441 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2441 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2441 # number of overall hits +system.cpu.dcache.overall_hits::total 2441 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 495 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 495 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 495 # number of overall misses +system.cpu.dcache.overall_misses::total 495 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5658500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5658500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13040000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13040000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18698500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18698500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18698500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18698500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2011 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2011 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2936 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2936 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2936 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2936 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073595 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073595 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.375135 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168597 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168597 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168597 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168597 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38233.108108 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38233.108108 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37579.250720 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37579.250720 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37774.747475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 37774.747475 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,119 +462,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # 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average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37054.054054 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37054.054054 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10999000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3463000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14462000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1839500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1839500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10999000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5302500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16301500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10999000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5302500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16301500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32350 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38477.777778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33632.558140 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini index f7cc4efef..1e54677ab 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout index ac53df969..3ee3fb923 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:48 +gem5 compiled Jul 2 2012 08:47:33 +gem5 started Jul 2 2012 11:29:16 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 32088000 because target called exit() +Exiting @ tick 33413000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 8f49928a9..eb8915cb4 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000032 # Number of seconds simulated -sim_ticks 32088000 # Number of ticks simulated -final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000033 # Number of seconds simulated +sim_ticks 33413000 # Number of ticks simulated +final_tick 33413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 540307 # Simulator instruction rate (inst/s) -host_op_rate 539410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2965678153 # Simulator tick rate (ticks/s) -host_mem_usage 215020 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 168189 # Simulator instruction rate (inst/s) +host_op_rate 168105 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 963489284 # Simulator tick rate (ticks/s) +host_mem_usage 219036 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 5827 # Number of instructions simulated sim_ops 5827 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19264 # Nu system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 439 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 576542064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 264328255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 840870320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 576542064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 576542064 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 576542064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 264328255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 840870320 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,7 +46,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 64176 # number of cpu cycles simulated +system.cpu.numCycles 66826 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5827 # Number of instructions committed @@ -65,18 +65,18 @@ system.cpu.num_mem_refs 2090 # nu system.cpu.num_load_insts 1164 # Number of load instructions system.cpu.num_store_insts 926 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 64176 # Number of busy cycles +system.cpu.num_busy_cycles 66826 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use +system.cpu.icache.tagsinuse 133.092783 # Cycle average of tags in use system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 133.092783 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.064987 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.064987 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits @@ -147,14 +147,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 87.717237 # Cycle average of tags in use system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 87.717237 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021415 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021415 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits @@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 188.818071 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 134.446837 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 54.371234 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004103 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001659 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005762 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 928f0469f..fe01ee3c1 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -480,7 +480,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -512,7 +512,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 584102e9c..4c16f50ba 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:53:15 +gem5 compiled Jul 2 2012 08:50:36 +gem5 started Jul 2 2012 11:29:39 gem5 executing on zizzer command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11179000 because target called exit() +Exiting @ tick 11812000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index f8f7991bd..0b8cd16ea 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11179000 # Number of ticks simulated -final_tick 11179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11812000 # Number of ticks simulated +final_tick 11812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61972 # Simulator instruction rate (inst/s) -host_op_rate 61960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119400246 # Simulator tick rate (ticks/s) -host_mem_usage 216052 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 59914 # Simulator instruction rate (inst/s) +host_op_rate 59903 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 121974515 # Simulator tick rate (ticks/s) +host_mem_usage 216016 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory -system.physmem.bytes_read::total 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2003757044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 578227033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2581984077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2003757044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2003757044 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2003757044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 578227033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2581984077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6400 # Number of bytes read from this memory +system.physmem.bytes_read::total 28928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 100 # Number of read requests responded to by this memory +system.physmem.num_reads::total 452 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1907213004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 541821876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2449034880 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1907213004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1907213004 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1907213004 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 541821876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2449034880 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22359 # number of cpu cycles simulated +system.cpu.numCycles 23625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2487 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2038 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 457 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2063 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 631 # Number of BTB hits +system.cpu.BPredUnit.lookups 2490 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2041 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 460 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2061 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 629 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 157 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6834 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14542 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2487 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 788 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1412 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 813 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14561 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2490 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 791 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2421 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1432 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 932 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.320439 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.737355 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1897 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 321 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.238075 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.668941 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8598 78.07% 78.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 170 1.54% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 167 1.52% 81.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 144 1.31% 82.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 198 1.80% 84.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 151 1.37% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 257 2.33% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 107 0.97% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1221 11.09% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9340 79.42% 79.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 172 1.46% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 167 1.42% 82.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 146 1.24% 83.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 197 1.68% 85.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 155 1.32% 86.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 255 2.17% 88.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.92% 89.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 10.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11013 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.111230 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.650387 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 884 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2239 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 359 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 11761 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.105397 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.616339 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7565 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1069 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2256 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 64 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 807 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 361 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12898 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 445 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7240 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 304 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2086 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12206 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 201 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10543 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19911 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19856 # Number of integer rename lookups +system.cpu.decode.DecodedInsts 12930 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 452 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 807 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7781 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 440 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 384 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2100 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 249 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12283 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 203 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10602 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 20025 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19970 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5536 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 518 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2072 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1895 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 60 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10882 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9264 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 154 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4859 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11013 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.841188 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.574613 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 5595 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 26 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2098 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1917 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 31 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11001 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 65 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9282 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4968 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4343 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 49 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11761 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789219 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.523023 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7627 69.25% 69.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1067 9.69% 78.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 747 6.78% 85.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 527 4.79% 90.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 479 4.35% 94.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 323 2.93% 97.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 151 1.37% 99.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 51 0.46% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8303 70.60% 70.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1127 9.58% 80.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 767 6.52% 86.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 536 4.56% 91.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 478 4.06% 95.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 324 2.75% 98.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 139 1.18% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 49 0.42% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 38 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11761 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.35% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 44.69% 48.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 93 51.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.87% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.87% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 78 44.83% 47.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 91 52.30% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5707 61.60% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.60% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1853 20.00% 81.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1702 18.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5709 61.51% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.51% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1861 20.05% 81.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1710 18.42% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9264 # Type of FU issued -system.cpu.iq.rate 0.414330 # Inst issue rate -system.cpu.iq.fu_busy_cnt 179 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019322 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29812 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15773 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8347 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9282 # Type of FU issued +system.cpu.iq.rate 0.392889 # Inst issue rate +system.cpu.iq.fu_busy_cnt 174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018746 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30604 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16005 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8374 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9409 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9422 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1110 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1136 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 871 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10943 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 107 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2072 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1895 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 807 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 227 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11066 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2098 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1917 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 311 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 389 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8757 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1710 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8779 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3276 # number of memory reference insts executed +system.cpu.iew.exec_refs 3289 # number of memory reference insts executed system.cpu.iew.exec_branches 1382 # Number of branches executed -system.cpu.iew.exec_stores 1566 # Number of stores executed -system.cpu.iew.exec_rate 0.391654 # Inst execution rate -system.cpu.iew.wb_sent 8550 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4334 # num instructions producing a value -system.cpu.iew.wb_consumers 6981 # num instructions consuming a value +system.cpu.iew.exec_stores 1573 # Number of stores executed +system.cpu.iew.exec_rate 0.371598 # Inst execution rate +system.cpu.iew.wb_sent 8575 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8401 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4358 # num instructions producing a value +system.cpu.iew.wb_consumers 6997 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.374525 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.620828 # average fanout of values written-back +system.cpu.iew.wb_rate 0.355598 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.622838 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5152 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5275 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 300 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10220 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.567515 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.347907 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 301 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10954 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.529487 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308345 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7783 76.15% 76.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1041 10.19% 86.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 649 6.35% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 256 2.50% 95.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 188 1.84% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 1.06% 98.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 57 0.56% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 45 0.44% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 93 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8509 77.68% 77.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1052 9.60% 87.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 645 5.89% 93.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 263 2.40% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 183 1.67% 97.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 104 0.95% 98.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 63 0.58% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.37% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10954 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,68 +295,68 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21079 # The number of ROB reads -system.cpu.rob.rob_writes 22698 # The number of ROB writes -system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21935 # The number of ROB reads +system.cpu.rob.rob_writes 22958 # The number of ROB writes +system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11864 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.855000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.855000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.259403 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.259403 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13891 # number of integer regfile reads -system.cpu.int_regfile_writes 7248 # number of integer regfile writes +system.cpu.cpi 4.073276 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.073276 # CPI: Total CPI of All Threads +system.cpu.ipc 0.245503 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.245503 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13900 # number of integer regfile reads +system.cpu.int_regfile_writes 7266 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.424294 # Cycle average of tags in use -system.cpu.icache.total_refs 1455 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.098592 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 172.776641 # Cycle average of tags in use +system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.095238 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.424294 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084192 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084192 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1455 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1455 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1455 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1455 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1455 # number of overall hits -system.cpu.icache.overall_hits::total 1455 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses -system.cpu.icache.overall_misses::total 432 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15599000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15599000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15599000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15599000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15599000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228935 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228935 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228935 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228935 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228935 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228935 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36108.796296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36108.796296 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.776641 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084364 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084364 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits +system.cpu.icache.overall_hits::total 1462 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16386000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16386000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16386000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16386000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16386000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16386000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1897 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1897 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1897 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1897 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1897 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229309 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229309 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229309 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229309 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13154500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13154500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13154500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188192 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188192 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188192 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188192 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36847.338936 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36847.338936 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.023619 # Cycle average of tags in use -system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.940594 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.298936 # Cycle average of tags in use +system.cpu.dcache.total_refs 2197 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 100 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.970000 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.023619 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015387 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015387 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 730 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2216 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits -system.cpu.dcache.overall_hits::total 2216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 86 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 86 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 402 # number of overall misses -system.cpu.dcache.overall_misses::total 402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3106000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3106000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10571500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10571500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13677500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13677500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13677500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13677500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 63.298936 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015454 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015454 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1480 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1480 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 717 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2197 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2197 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2197 # number of overall hits +system.cpu.dcache.overall_hits::total 2197 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 329 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 329 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 421 # number of overall misses +system.cpu.dcache.overall_misses::total 421 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3732500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3732500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12822500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12822500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16555000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16555000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16555000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16555000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -437,22 +437,22 @@ system.cpu.dcache.demand_accesses::cpu.data 2618 # system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.054707 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.054707 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.153552 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.153552 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.153552 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.153552 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34023.631841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34023.631841 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.058524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314532 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.314532 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.160810 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.160810 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.160810 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.160810 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39323.040380 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39323.040380 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,119 +461,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 39 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 39 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 282 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 282 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 321 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 321 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 321 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # 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number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987745 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989035 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989059 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989035 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989059 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37775 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index d62e06b17..dd53d4220 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -181,7 +181,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -213,7 +213,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 76c88733e..a234b881d 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:44:31 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:30:03 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 18196500 because target called exit() +Hello World!Exiting @ tick 18885500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index b45b5b881..fa8b51b5a 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 18196500 # Number of ticks simulated -final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18885500 # Number of ticks simulated +final_tick 18885500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58781 # Simulator instruction rate (inst/s) -host_op_rate 58769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 200221364 # Simulator tick rate (ticks/s) -host_mem_usage 221628 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 37135 # Simulator instruction rate (inst/s) +host_op_rate 37131 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 131302803 # Simulator tick rate (ticks/s) +host_mem_usage 220012 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -19,28 +19,28 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1016459209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 471299426 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1487758635 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1016459209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1016459209 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1016459209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 471299426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1487758635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 979375712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 454105001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1433480713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 979375712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 979375712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 979375712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 454105001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1433480713 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 36394 # number of cpu cycles simulated +system.cpu.numCycles 37772 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1617 # Number of BP lookups +system.cpu.branch_predictor.lookups 1615 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1170 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 37.179487 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False). +system.cpu.branch_predictor.predictedNotTaken 1113 # Number of Branches Predicted As Not Taken (False). system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File @@ -58,12 +58,12 @@ system.cpu.execution_unit.executions 3979 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 10178 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6227 # Number of cycles cpu stages are processed. -system.cpu.activity 17.109963 # Percentage of cycles cpu is active +system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31527 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 16.533411 # Percentage of cycles cpu is active system.cpu.comLoads 716 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1116 # Number of Branches instructions committed @@ -75,72 +75,72 @@ system.cpu.committedInsts 5340 # Nu system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total) -system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.073408 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads -system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.073408 # CPI: Total CPI of All Threads +system.cpu.ipc 0.141375 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.141375 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33203 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4569 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 12.096262 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34575 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 8.463942 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34722 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed. +system.cpu.stage2.utilization 8.074764 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36789 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.utilization 2.602457 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34600 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3172 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 8.397755 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use -system.cpu.icache.total_refs 827 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.494329 # Cycle average of tags in use +system.cpu.icache.total_refs 825 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.835052 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits -system.cpu.icache.overall_hits::total 827 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses -system.cpu.icache.overall_misses::total 347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.295571 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.295571 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.295571 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55063.400576 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55063.400576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55063.400576 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 136.494329 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.066648 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.066648 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 825 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 825 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 825 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 825 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 825 # number of overall hits +system.cpu.icache.overall_hits::total 825 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses +system.cpu.icache.overall_misses::total 350 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19647000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19647000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19647000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19647000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19647000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19647000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1175 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1175 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1175 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1175 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.297872 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.297872 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.297872 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.297872 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.297872 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.297872 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56134.285714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 56134.285714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 56134.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 56134.285714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 56134.285714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -149,70 +149,70 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247871 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247871 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247871 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53154.639175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53154.639175 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15992500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15992500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15992500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15992500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15992500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15992500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247660 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247660 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247660 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247660 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247660 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247660 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54957.044674 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54957.044674 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54957.044674 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 54957.044674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54957.044674 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 54957.044674 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use -system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.670041 # Cycle average of tags in use +system.cpu.dcache.total_refs 1046 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 7.748148 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 392 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1049 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1049 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1049 # number of overall hits -system.cpu.dcache.overall_hits::total 1049 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 281 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 281 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 340 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses -system.cpu.dcache.overall_misses::total 340 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 82.670041 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020183 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020183 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 655 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 655 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 391 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1046 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1046 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1046 # number of overall hits +system.cpu.dcache.overall_hits::total 1046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 282 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 282 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 343 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses +system.cpu.dcache.overall_misses::total 343 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3569500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3569500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 17306500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 17306500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20876000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20876000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20876000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20876000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -221,38 +221,38 @@ system.cpu.dcache.demand_accesses::cpu.data 1389 # system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082402 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.417533 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.244780 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.244780 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55788.135593 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55010.676157 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55145.588235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55145.588235 # average overall miss latency +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085196 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085196 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.419019 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.419019 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246940 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246940 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246940 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246940 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58516.393443 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58516.393443 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.567376 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.567376 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 60862.973761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 60862.973761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 60862.973761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 60862.973761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2306500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 51255.555556 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 200 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 200 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 205 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 205 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 205 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 205 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 201 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 201 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 208 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 208 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses @@ -261,14 +261,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3065000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3065000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4526000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7591000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7591000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7591000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075419 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -277,26 +277,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 system.cpu.dcache.demand_mshr_miss_rate::total 0.097192 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097192 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53074.074074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53425.925926 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53285.185185 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56759.259259 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55876.543210 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55876.543210 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56229.629630 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56229.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56229.629630 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56229.629630 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 162.084916 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 136.002391 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.082525 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004150 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000796 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004946 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15656000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2985500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18641500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4434500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4434500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15656000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7420000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23076000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15656000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7420000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23076000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52390.350877 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52228.395062 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52359.338061 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52359.338061 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54173.010381 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56330.188679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54507.309942 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54746.913580 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54746.913580 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54173.010381 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55373.134328 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54553.191489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54173.010381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55373.134328 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54553.191489 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12139500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2343500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14483000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3454500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3454500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12139500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5798000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17937500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12139500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5798000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17937500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40195.906433 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40191.358025 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40195.035461 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42005.190311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44216.981132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42347.953216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42005.190311 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43268.656716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42405.437352 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini index 232d3350e..53f402a63 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini @@ -148,7 +148,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side @@ -180,7 +180,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] slave=system.system_port system.cpu.l2cache.mem_side diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout index e4af58bc7..81bff15c4 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:44:42 +gem5 compiled Jul 2 2012 08:54:18 +gem5 started Jul 2 2012 11:30:26 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 28206000 because target called exit() +Hello World!Exiting @ tick 29541000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 3580b75db..d0e2c9d97 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28206000 # Number of ticks simulated -final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29541000 # Number of ticks simulated +final_tick 29541000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 427855 # Simulator instruction rate (inst/s) -host_op_rate 427237 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2253599179 # Simulator tick rate (ticks/s) -host_mem_usage 221156 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 73924 # Simulator instruction rate (inst/s) +host_op_rate 73907 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 408761366 # Simulator tick rate (ticks/s) +host_mem_usage 220016 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5340 # Number of instructions simulated sim_ops 5340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 578600298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 304048784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 882649082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 578600298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 578600298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 578600298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 304048784 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 882649082 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 552452524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 290308385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 842760909 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 552452524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 552452524 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 552452524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 290308385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 842760909 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56412 # number of cpu cycles simulated +system.cpu.numCycles 59082 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5340 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1402 # nu system.cpu.num_load_insts 724 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 56412 # Number of busy cycles +system.cpu.num_busy_cycles 59082 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use +system.cpu.icache.tagsinuse 117.079183 # Cycle average of tags in use system.cpu.icache.total_refs 5127 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 117.079183 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.057168 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.057168 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 82.107175 # Cycle average of tags in use system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.065697 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020036 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020036 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 82.107175 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020046 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020046 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 142.223187 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 116.450335 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 25.652557 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003554 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004337 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 116.548564 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 25.674623 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003557 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000784 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004340 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index f4e4acba8..73bd70079 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -500,7 +500,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -532,7 +532,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 19d634444..3bef840f7 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:03:58 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 12:38:36 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 12198000 because target called exit() +Exiting @ tick 12803000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b16a10afa..d0e4f2a16 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,272 +1,272 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12198000 # Number of ticks simulated -final_tick 12198000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12803000 # Number of ticks simulated +final_tick 12803000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39950 # Simulator instruction rate (inst/s) -host_op_rate 72345 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89952499 # Simulator tick rate (ticks/s) -host_mem_usage 224288 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 24032 # Simulator instruction rate (inst/s) +host_op_rate 43521 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56800152 # Simulator tick rate (ticks/s) +host_mem_usage 227452 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 5416 # Number of instructions simulated sim_ops 9809 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 19328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9536 # Number of bytes read from this memory -system.physmem.bytes_read::total 28864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19328 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 302 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 149 # Number of read requests responded to by this memory -system.physmem.num_reads::total 451 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1584522053 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 781767503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2366289556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1584522053 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1584522053 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 781767503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2366289556 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9280 # Number of bytes read from this memory +system.physmem.bytes_read::total 28544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory +system.physmem.num_reads::total 446 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1504647348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 724830118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2229477466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1504647348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1504647348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1504647348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 724830118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2229477466 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24397 # number of cpu cycles simulated +system.cpu.numCycles 25607 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3206 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3206 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 560 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2627 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 792 # Number of BTB hits +system.cpu.BPredUnit.lookups 3125 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3125 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 558 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2605 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 830 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15410 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3206 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 792 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4170 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2487 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3163 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 16 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 98 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1951 # Number of cache lines fetched +system.cpu.fetch.icacheStallCycles 8034 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14981 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3125 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 830 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4070 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2483 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3408 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 244 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1957 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 281 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 16727 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.635918 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.075272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 17679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.502687 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.975668 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 12659 75.68% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 177 1.06% 76.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 166 0.99% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 214 1.28% 79.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 171 1.02% 80.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 175 1.05% 81.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 250 1.49% 82.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 166 0.99% 83.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2749 16.43% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 13710 77.55% 77.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 177 1.00% 78.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 164 0.93% 79.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 211 1.19% 80.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 170 0.96% 81.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 182 1.03% 82.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 260 1.47% 84.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 162 0.92% 85.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2643 14.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 16727 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.131410 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.631635 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7836 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3109 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3749 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26025 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8180 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1960 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 442 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3522 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 718 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24463 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 17679 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122037 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.585035 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8588 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3390 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3692 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 127 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1882 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25327 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1882 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8910 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2031 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 505 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3461 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23802 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 50 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.IQFullEvents 47 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 747 # Number of times rename has blocked due to LSQ full system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 35223 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 70488 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 70472 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 34224 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 68607 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 68591 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 14707 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 20516 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 33 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1918 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2376 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1791 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 19517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 35 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 35 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 1875 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2306 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1775 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21692 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17854 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 82 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11255 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20549 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 16727 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.067376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.893384 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 21232 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17582 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10865 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 19620 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 27 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 17679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.994513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.826049 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11276 67.41% 67.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1383 8.27% 75.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1035 6.19% 81.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 667 3.99% 85.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 692 4.14% 89.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 723 4.32% 94.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 673 4.02% 98.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 245 1.46% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 33 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12114 68.52% 68.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1582 8.95% 77.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1012 5.72% 83.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 689 3.90% 87.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 696 3.94% 91.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 692 3.91% 94.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 627 3.55% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 233 1.32% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 34 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 16727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 17679 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 140 73.30% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 30 15.71% 89.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 21 10.99% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 133 73.08% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 73.08% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 29 15.93% 89.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 20 10.99% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14397 80.64% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1982 11.10% 91.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1471 8.24% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14185 80.68% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1924 10.94% 91.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1469 8.36% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17854 # Type of FU issued -system.cpu.iq.rate 0.731811 # Inst issue rate -system.cpu.iq.fu_busy_cnt 191 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010698 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 52700 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32991 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16402 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17582 # Type of FU issued +system.cpu.iq.rate 0.686609 # Inst issue rate +system.cpu.iq.fu_busy_cnt 182 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010351 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53109 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32144 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16183 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18037 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17756 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 151 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 148 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1250 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 857 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 841 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1329 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 39 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21730 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 24 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2376 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1791 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1882 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1425 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21272 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 46 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2306 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1775 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 36 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 631 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 690 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16824 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1844 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1030 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 640 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16602 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1794 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 980 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3203 # number of memory reference insts executed -system.cpu.iew.exec_branches 1645 # Number of branches executed -system.cpu.iew.exec_stores 1359 # Number of stores executed -system.cpu.iew.exec_rate 0.689593 # Inst execution rate -system.cpu.iew.wb_sent 16593 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16406 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10679 # num instructions producing a value -system.cpu.iew.wb_consumers 24448 # num instructions consuming a value +system.cpu.iew.exec_refs 3144 # number of memory reference insts executed +system.cpu.iew.exec_branches 1642 # Number of branches executed +system.cpu.iew.exec_stores 1350 # Number of stores executed +system.cpu.iew.exec_rate 0.648338 # Inst execution rate +system.cpu.iew.wb_sent 16384 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16187 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10480 # num instructions producing a value +system.cpu.iew.wb_consumers 24095 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.672460 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.436805 # average fanout of values written-back +system.cpu.iew.wb_rate 0.632132 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.434945 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 11920 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11462 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 571 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14822 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.661787 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.507902 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 589 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 15797 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.620941 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.463366 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11181 75.44% 75.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1365 9.21% 84.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 653 4.41% 89.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 730 4.93% 93.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 2.46% 96.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 129 0.87% 97.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 139 0.94% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71 0.48% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 189 1.28% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12065 76.38% 76.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1534 9.71% 86.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 576 3.65% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 731 4.63% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 367 2.32% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 129 0.82% 97.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 134 0.85% 98.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 75 0.47% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 186 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 15797 # Number of insts commited each cycle system.cpu.commit.committedInsts 5416 # Number of instructions committed system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -277,68 +277,68 @@ system.cpu.commit.branches 1214 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9714 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 189 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 186 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36362 # The number of ROB reads -system.cpu.rob.rob_writes 45397 # The number of ROB writes -system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7670 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 36882 # The number of ROB reads +system.cpu.rob.rob_writes 44457 # The number of ROB writes +system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7928 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5416 # Number of Instructions Simulated system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5416 # Number of Instructions Simulated -system.cpu.cpi 4.504616 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.504616 # CPI: Total CPI of All Threads -system.cpu.ipc 0.221995 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.221995 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 35460 # number of integer regfile reads -system.cpu.int_regfile_writes 22063 # number of integer regfile writes +system.cpu.cpi 4.728028 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.728028 # CPI: Total CPI of All Threads +system.cpu.ipc 0.211505 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.211505 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 35136 # number of integer regfile reads +system.cpu.int_regfile_writes 21832 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7402 # number of misc regfile reads +system.cpu.misc_regfile_reads 7303 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 145.636183 # Cycle average of tags in use -system.cpu.icache.total_refs 1561 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.134868 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 144.987593 # Cycle average of tags in use +system.cpu.icache.total_refs 1569 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 302 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.195364 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 145.636183 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071111 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071111 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1561 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1561 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1561 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1561 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1561 # number of overall hits -system.cpu.icache.overall_hits::total 1561 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 390 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 390 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 390 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 390 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 390 # number of overall misses -system.cpu.icache.overall_misses::total 390 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13866500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13866500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13866500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13866500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13866500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13866500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1951 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1951 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1951 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1951 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1951 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199897 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.199897 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.199897 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.199897 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.199897 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.199897 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35555.128205 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35555.128205 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35555.128205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35555.128205 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35555.128205 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 144.987593 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070795 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070795 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1569 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1569 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1569 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1569 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1569 # number of overall hits +system.cpu.icache.overall_hits::total 1569 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 388 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 388 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 388 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 388 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 388 # number of overall misses +system.cpu.icache.overall_misses::total 388 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14367500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14367500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14367500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14367500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14367500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14367500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1957 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1957 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1957 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1957 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1957 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198263 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.198263 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.198263 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.198263 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.198263 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.198263 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 37029.639175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 37029.639175 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -353,88 +353,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 86 system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10687000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10687000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10687000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10687000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155818 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155818 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.155818 # 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number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11138000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11138000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11138000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11138000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11138000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11138000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154318 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.154318 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154318 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.154318 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.751522 # Cycle average of tags in use -system.cpu.dcache.total_refs 2365 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.979730 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.196834 # Cycle average of tags in use +system.cpu.dcache.total_refs 2330 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.180556 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.751522 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020691 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020691 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1507 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1507 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 83.196834 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020312 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020312 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1472 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2365 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2365 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2365 # number of overall hits -system.cpu.dcache.overall_hits::total 2365 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2330 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2330 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2330 # number of overall hits +system.cpu.dcache.overall_hits::total 2330 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 112 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 112 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 191 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 191 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 191 # number of overall misses -system.cpu.dcache.overall_misses::total 191 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4030500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4030500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2917500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2917500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6948000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6948000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6948000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6948000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1622 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1622 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 188 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 188 # number of overall misses +system.cpu.dcache.overall_misses::total 188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4401500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4401500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3078500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3078500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7480000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7480000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7480000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7480000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1584 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1584 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2556 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2556 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2556 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2556 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070900 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2518 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2518 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2518 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2518 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070707 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.074726 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.074726 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.074726 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.074726 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35047.826087 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35047.826087 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38388.157895 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38388.157895 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36376.963351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36376.963351 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36376.963351 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.074662 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.074662 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.074662 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.074662 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39787.234043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39787.234043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -443,117 +443,117 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9394000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4633000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14027000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9394000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4633000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14027000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9877000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2416500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12293500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2541500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9877000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4958000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14835000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9877000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4958000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14835000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994695 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997305 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995585 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993421 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995585 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31105.960265 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31006.849315 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.666667 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31177.631579 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31105.960265 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31093.959732 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31101.995565 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini index 3ced8b832..75df56c4d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini @@ -169,7 +169,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.cpu.l2cache.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port @@ -201,7 +201,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout index 62a044b81..c1b9925b1 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 13:44:28 -gem5 started Jun 4 2012 15:04:19 +gem5 compiled Jul 2 2012 08:58:39 +gem5 started Jul 2 2012 12:38:59 gem5 executing on zizzer -command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing +command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 28768000 because target called exit() +Exiting @ tick 29726000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index 1e89d36d4..4b1ad61d2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28768000 # Number of ticks simulated -final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 29726000 # Number of ticks simulated +final_tick 29726000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 318234 # Simulator instruction rate (inst/s) -host_op_rate 575684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1686451163 # Simulator tick rate (ticks/s) -host_mem_usage 223048 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host +host_inst_rate 107097 # Simulator instruction rate (inst/s) +host_op_rate 193883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 587308683 # Simulator tick rate (ticks/s) +host_mem_usage 226300 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5417 # Number of instructions simulated sim_ops 9810 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory @@ -19,16 +19,16 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 505005562 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 298109010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 803114572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 505005562 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 505005562 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 298109010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 803114572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 488730404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 288501648 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 777232053 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 488730404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 488730404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 488730404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 288501648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 777232053 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 57536 # number of cpu cycles simulated +system.cpu.numCycles 59452 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5417 # Number of instructions committed @@ -47,18 +47,18 @@ system.cpu.num_mem_refs 1990 # nu system.cpu.num_load_insts 1056 # Number of load instructions system.cpu.num_store_insts 934 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 57536 # Number of busy cycles +system.cpu.num_busy_cycles 59452 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use +system.cpu.icache.tagsinuse 105.590396 # Cycle average of tags in use system.cpu.icache.total_refs 6683 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 105.590396 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.051558 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.051558 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits @@ -129,14 +129,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 80.767478 # Cycle average of tags in use system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 80.668870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.019695 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.019695 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 80.767478 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.019719 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.019719 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1001 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1001 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 855 # number of WriteReq hits @@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 134.079161 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.370729 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.438613 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003216 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000868 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004084 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.593760 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.485401 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003222 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004092 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits |