diff options
Diffstat (limited to 'tests/quick/se/00.hello')
18 files changed, 2920 insertions, 2922 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index bcee17b83..da5dd186c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:03:27 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:21 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12450500 because target called exit() +Exiting @ tick 12146500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index e9f17ec08..40a9fef11 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12450500 # Number of ticks simulated -final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12146500 # Number of ticks simulated +final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73568 # Simulator instruction rate (inst/s) -host_op_rate 73552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 143373020 # Simulator tick rate (ticks/s) -host_mem_usage 215332 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 109785 # Simulator instruction rate (inst/s) +host_op_rate 109750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 208686624 # Simulator tick rate (ticks/s) +host_mem_usage 218220 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory -system.physmem.bytes_read::total 31360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 490 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 488 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1943 # DTB read hits -system.cpu.dtb.read_misses 53 # DTB read misses +system.cpu.dtb.read_hits 1978 # DTB read hits +system.cpu.dtb.read_misses 49 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1996 # DTB read accesses -system.cpu.dtb.write_hits 1071 # DTB write hits -system.cpu.dtb.write_misses 32 # DTB write misses +system.cpu.dtb.read_accesses 2027 # DTB read accesses +system.cpu.dtb.write_hits 1059 # DTB write hits +system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1103 # DTB write accesses -system.cpu.dtb.data_hits 3014 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1090 # DTB write accesses +system.cpu.dtb.data_hits 3037 # DTB hits +system.cpu.dtb.data_misses 80 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3099 # DTB accesses -system.cpu.itb.fetch_hits 2367 # ITB hits -system.cpu.itb.fetch_misses 26 # ITB misses +system.cpu.dtb.data_accesses 3117 # DTB accesses +system.cpu.itb.fetch_hits 2279 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2393 # ITB accesses +system.cpu.itb.fetch_accesses 2309 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24902 # number of cpu cycles simulated +system.cpu.numCycles 24294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2873 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits +system.cpu.BPredUnit.lookups 2808 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2784 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2684 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2587 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups +system.cpu.rename.RunCycles 2519 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10522 # Type of FU issued -system.cpu.iq.rate 0.422536 # Inst issue rate -system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10419 # Type of FU issued +system.cpu.iq.rate 0.428871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 108 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79 # number of nop insts executed -system.cpu.iew.exec_refs 3117 # number of memory reference insts executed -system.cpu.iew.exec_branches 1605 # Number of branches executed -system.cpu.iew.exec_stores 1108 # Number of stores executed -system.cpu.iew.exec_rate 0.396675 # Inst execution rate -system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9487 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4957 # num instructions producing a value -system.cpu.iew.wb_consumers 6732 # num instructions consuming a value +system.cpu.iew.exec_nop 83 # number of nop insts executed +system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_stores 1093 # Number of stores executed +system.cpu.iew.exec_rate 0.405244 # Inst execution rate +system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9443 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4951 # num instructions producing a value +system.cpu.iew.wb_consumers 6720 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back +system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,70 +310,70 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24667 # The number of ROB reads -system.cpu.rob.rob_writes 26868 # The number of ROB writes -system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24228 # The number of ROB reads +system.cpu.rob.rob_writes 26471 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads -system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12526 # number of integer regfile reads -system.cpu.int_regfile_writes 7116 # number of integer regfile writes +system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12506 # number of integer regfile reads +system.cpu.int_regfile_writes 7104 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use -system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use +system.cpu.icache.total_refs 1829 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits -system.cpu.icache.overall_hits::total 1909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses -system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits +system.cpu.icache.overall_hits::total 1829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses +system.cpu.icache.overall_misses::total 450 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,94 +382,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use -system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use +system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits -system.cpu.dcache.overall_hits::total 2244 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits +system.cpu.dcache.overall_hits::total 2275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 146 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 146 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5337000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5337000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12518000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,14 +478,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -494,103 +494,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 176 system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054393 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.380125 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 161.620273 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 62.759852 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004932 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001915 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006848 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses -system.cpu.l2cache.overall_misses::total 490 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 488 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10703000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3603500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2489000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2489000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6092500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6092500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16795500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 157d28a7a..2586fc610 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:45:03 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:32 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7015000 because target called exit() +Exiting @ tick 6934000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 119328db2..729742f8d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7015000 # Number of ticks simulated -final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 6934000 # Number of ticks simulated +final_tick 6934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16156 # Simulator instruction rate (inst/s) -host_op_rate 16154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47467285 # Simulator tick rate (ticks/s) -host_mem_usage 214556 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 29510 # Simulator instruction rate (inst/s) +host_op_rate 29504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85688409 # Simulator tick rate (ticks/s) +host_mem_usage 217944 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory -system.physmem.bytes_read::total 17600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory -system.physmem.num_reads::total 275 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory +system.physmem.bytes_read::total 17472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory +system.physmem.num_reads::total 273 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1735217768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 784539948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2519757716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1735217768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1735217768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1735217768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 784539948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2519757716 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 711 # DTB read hits -system.cpu.dtb.read_misses 43 # DTB read misses +system.cpu.dtb.read_hits 704 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 380 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.read_accesses 740 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 22 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 403 # DTB write accesses -system.cpu.dtb.data_hits 1091 # DTB hits -system.cpu.dtb.data_misses 66 # DTB misses +system.cpu.dtb.write_accesses 389 # DTB write accesses +system.cpu.dtb.data_hits 1071 # DTB hits +system.cpu.dtb.data_misses 58 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1157 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 1129 # DTB accesses +system.cpu.itb.fetch_hits 999 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1100 # ITB accesses +system.cpu.itb.fetch_accesses 1029 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14031 # number of cpu cycles simulated +system.cpu.numCycles 13869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1201 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits +system.cpu.BPredUnit.lookups 1119 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 563 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 252 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 783 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 216 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6858 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1119 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 426 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1175 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 850 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 783 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 170 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.037362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5436 82.23% 82.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 51 0.77% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.95% 84.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 97 1.47% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 136 2.06% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62 0.94% 89.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 1.00% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.97% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 570 8.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1197 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080684 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.494484 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4718 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 256 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1133 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking +system.cpu.decode.DecodedInsts 6102 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 67 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups +system.cpu.rename.RunCycles 1046 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5849 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4252 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6619 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6607 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2484 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle +system.cpu.rename.skidInsts 137 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 945 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2372 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1428 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.321430 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4990 75.48% 75.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 583 8.82% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 382 5.78% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 267 4.04% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 192 2.90% 97.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 114 1.72% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 53 0.80% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18 0.27% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6611 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 9.09% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 38.64% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2853 70.86% 70.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 775 19.25% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 397 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4206 # Type of FU issued -system.cpu.iq.rate 0.299765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 43 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4026 # Type of FU issued +system.cpu.iq.rate 0.290288 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010929 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14762 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7351 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3682 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4063 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5319 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 96 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 945 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3873 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 741 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 368 # number of nop insts executed -system.cpu.iew.exec_refs 1160 # number of memory reference insts executed -system.cpu.iew.exec_branches 681 # Number of branches executed -system.cpu.iew.exec_stores 403 # Number of stores executed -system.cpu.iew.exec_rate 0.285439 # Inst execution rate -system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3813 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1793 # num instructions producing a value -system.cpu.iew.wb_consumers 2339 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1130 # number of memory reference insts executed +system.cpu.iew.exec_branches 650 # Number of branches executed +system.cpu.iew.exec_stores 389 # Number of stores executed +system.cpu.iew.exec_rate 0.279256 # Inst execution rate +system.cpu.iew.wb_sent 3778 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1732 # num instructions producing a value +system.cpu.iew.wb_consumers 2249 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back +system.cpu.iew.wb_rate 0.265917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.770120 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2738 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 172 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.421121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.275697 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5226 85.43% 85.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 218 3.56% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 319 5.21% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 117 1.91% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 69 1.13% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.92% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.52% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 19 0.31% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6117 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,69 +310,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11567 # The number of ROB reads -system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.rob.rob_reads 11123 # The number of ROB reads +system.cpu.rob.rob_writes 11131 # The number of ROB writes system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7258 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4832 # number of integer regfile reads -system.cpu.int_regfile_writes 2958 # number of integer regfile writes +system.cpu.cpi 5.810222 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.810222 # CPI: Total CPI of All Threads +system.cpu.ipc 0.172110 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.172110 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4695 # number of integer regfile reads +system.cpu.int_regfile_writes 2856 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use -system.cpu.icache.total_refs 817 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.248355 # Cycle average of tags in use +system.cpu.icache.total_refs 752 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits -system.cpu.icache.overall_hits::total 817 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.248355 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045531 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045531 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 752 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 752 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 752 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 752 # number of overall hits +system.cpu.icache.overall_hits::total 752 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 247 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 247 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 247 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 247 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 247 # number of overall misses +system.cpu.icache.overall_misses::total 247 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8946000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8946000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8946000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8946000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8946000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8946000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.247247 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.247247 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.247247 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.247247 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.247247 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.247247 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36218.623482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36218.623482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6660500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188188 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use -system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.780075 # Cycle average of tags in use +system.cpu.dcache.total_refs 785 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.235294 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 45.780075 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 563 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 563 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits -system.cpu.dcache.overall_hits::total 793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 785 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 785 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 785 # number of overall hits +system.cpu.dcache.overall_hits::total 785 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 110 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 110 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 179 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses -system.cpu.dcache.overall_misses::total 179 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses +system.cpu.dcache.overall_misses::total 182 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3679000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3679000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2813500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2813500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 673 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.163447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.163447 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.188211 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188211 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188211 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188211 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35673.076923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,91 +477,91 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2166000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2166000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3037000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3037000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3037000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3037000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090639 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087901 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087901 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.119430 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 62 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 251 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 93.334885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.784545 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002848 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000878 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003727 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses -system.cpu.l2cache.overall_misses::total 275 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses +system.cpu.l2cache.overall_misses::total 273 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6449000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2098500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8547500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 830000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 830000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6449000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2928500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9377500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6449000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2928500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9377500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,28 +592,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5849000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1904500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7753500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 755000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 755000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5849000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8508500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5849000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8508500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 9fb63a7a7..c374c028c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:34:53 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10303500 because target called exit() +Exiting @ tick 10305000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ea50665b2..9b64fc302 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10303500 # Number of ticks simulated -final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10305000 # Number of ticks simulated +final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43907 # Simulator instruction rate (inst/s) -host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98312554 # Simulator tick rate (ticks/s) -host_mem_usage 230064 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated +host_inst_rate 40668 # Simulator instruction rate (inst/s) +host_op_rate 50741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91257316 # Simulator tick rate (ticks/s) +host_mem_usage 232684 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5752 # number of cpu cycles simulated +system.cpu.checker.numCycles 5742 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -115,319 +115,318 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20608 # number of cpu cycles simulated +system.cpu.numCycles 20611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits +system.cpu.BPredUnit.lookups 2522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2624 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2368 # Number of cycles rename is running system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 45 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9165 # Type of FU issued -system.cpu.iq.rate 0.444730 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9186 # Type of FU issued +system.cpu.iq.rate 0.445684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1406 # Number of branches executed -system.cpu.iew.exec_stores 1199 # Number of stores executed -system.cpu.iew.exec_rate 0.420565 # Inst execution rate -system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3874 # num instructions producing a value -system.cpu.iew.wb_consumers 7832 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3377 # number of memory reference insts executed +system.cpu.iew.exec_branches 1400 # Number of branches executed +system.cpu.iew.exec_stores 1208 # Number of stores executed +system.cpu.iew.exec_rate 0.423027 # Inst execution rate +system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3901 # num instructions producing a value +system.cpu.iew.wb_consumers 7899 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4600 # Number of instructions committed -system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4591 # Number of instructions committed +system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.refs 2138 # Number of memory references committed +system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.branches 944 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22629 # The number of ROB reads -system.cpu.rob.rob_writes 24771 # The number of ROB writes -system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4600 # Number of Instructions Simulated -system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39716 # number of integer regfile reads -system.cpu.int_regfile_writes 8038 # number of integer regfile writes +system.cpu.rob.rob_reads 22509 # The number of ROB reads +system.cpu.rob.rob_writes 24591 # The number of ROB writes +system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4591 # Number of Instructions Simulated +system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4591 # Number of Instructions Simulated +system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads +system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40006 # number of integer regfile reads +system.cpu.int_regfile_writes 8113 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16043 # number of misc regfile reads +system.cpu.misc_regfile_reads 15846 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use -system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use +system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits -system.cpu.icache.overall_hits::total 1665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits +system.cpu.icache.overall_hits::total 1637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,110 +435,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use -system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits +system.cpu.dcache.overall_hits::total 2425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses +system.cpu.dcache.overall_misses::total 477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,16 +547,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -566,73 +565,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -645,27 +644,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,49 +680,49 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index fc15b65e3..8b9162b5e 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:30 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:34:42 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10303500 because target called exit() +Exiting @ tick 10305000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 85d0d7401..e182dd250 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10303500 # Number of ticks simulated -final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10305000 # Number of ticks simulated +final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49511 # Simulator instruction rate (inst/s) -host_op_rate 61757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110854808 # Simulator tick rate (ticks/s) -host_mem_usage 229756 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated +host_inst_rate 29768 # Simulator instruction rate (inst/s) +host_op_rate 37142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66801597 # Simulator tick rate (ticks/s) +host_mem_usage 232684 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,319 +70,318 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20608 # number of cpu cycles simulated +system.cpu.numCycles 20611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits +system.cpu.BPredUnit.lookups 2522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2624 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2368 # Number of cycles rename is running system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 45 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9165 # Type of FU issued -system.cpu.iq.rate 0.444730 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9186 # Type of FU issued +system.cpu.iq.rate 0.445684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1406 # Number of branches executed -system.cpu.iew.exec_stores 1199 # Number of stores executed -system.cpu.iew.exec_rate 0.420565 # Inst execution rate -system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3874 # num instructions producing a value -system.cpu.iew.wb_consumers 7832 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3377 # number of memory reference insts executed +system.cpu.iew.exec_branches 1400 # Number of branches executed +system.cpu.iew.exec_stores 1208 # Number of stores executed +system.cpu.iew.exec_rate 0.423027 # Inst execution rate +system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3901 # num instructions producing a value +system.cpu.iew.wb_consumers 7899 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4600 # Number of instructions committed -system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4591 # Number of instructions committed +system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.refs 2138 # Number of memory references committed +system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.branches 944 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22629 # The number of ROB reads -system.cpu.rob.rob_writes 24771 # The number of ROB writes -system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4600 # Number of Instructions Simulated -system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39716 # number of integer regfile reads -system.cpu.int_regfile_writes 8038 # number of integer regfile writes +system.cpu.rob.rob_reads 22509 # The number of ROB reads +system.cpu.rob.rob_writes 24591 # The number of ROB writes +system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4591 # Number of Instructions Simulated +system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4591 # Number of Instructions Simulated +system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads +system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40006 # number of integer regfile reads +system.cpu.int_regfile_writes 8113 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16043 # number of misc regfile reads +system.cpu.misc_regfile_reads 15846 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use -system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use +system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits -system.cpu.icache.overall_hits::total 1665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits +system.cpu.icache.overall_hits::total 1637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,110 +390,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use -system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits +system.cpu.dcache.overall_hits::total 2425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses +system.cpu.dcache.overall_misses::total 477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,16 +502,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -521,73 +520,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -600,27 +599,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,49 +635,49 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a8cf8ab9b..a902d2024 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:03 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:15 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2875500 because target called exit() +Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index a4d8f3fa5..2fe5ceaba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2875500 # Number of ticks simulated -final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2870500 # Number of ticks simulated +final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 760705 # Simulator instruction rate (inst/s) -host_op_rate 946184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 472746039 # Simulator tick rate (ticks/s) -host_mem_usage 219832 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory -system.physmem.bytes_read::total 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +host_inst_rate 136961 # Simulator instruction rate (inst/s) +host_op_rate 170823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85547635 # Simulator tick rate (ticks/s) +host_mem_usage 223208 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory +system.physmem.bytes_read::total 22907 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -121,26 +121,26 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numCycles 5742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4600 # Number of instructions committed -system.cpu.committedOps 5739 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4591 # Number of instructions committed +system.cpu.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25237 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_busy_cycles 5742 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index f818842dc..d40bbcb86 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:52 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:04 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2875500 because target called exit() +Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 44b5714ac..ef6865dff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2875500 # Number of ticks simulated -final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2870500 # Number of ticks simulated +final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 577592 # Simulator instruction rate (inst/s) -host_op_rate 718947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 359450620 # Simulator tick rate (ticks/s) -host_mem_usage 219740 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory -system.physmem.bytes_read::total 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +host_inst_rate 62314 # Simulator instruction rate (inst/s) +host_op_rate 77743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38944247 # Simulator tick rate (ticks/s) +host_mem_usage 223212 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory +system.physmem.bytes_read::total 22907 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numCycles 5742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4600 # Number of instructions committed -system.cpu.committedOps 5739 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4591 # Number of instructions committed +system.cpu.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25237 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_busy_cycles 5742 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index a6d6adcc2..d4a066c4f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:13 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 26361000 because target called exit() +Exiting @ tick 26351000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 0449db647..bac15b503 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26361000 # Number of ticks simulated -final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26351000 # Number of ticks simulated +final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366471 # Simulator instruction rate (inst/s) -host_op_rate 454532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2105652624 # Simulator tick rate (ticks/s) -host_mem_usage 228652 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4574 # Number of instructions simulated -sim_ops 5682 # Number of ops (including micro ops) simulated +host_inst_rate 50718 # Simulator instruction rate (inst/s) +host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292657577 # Simulator tick rate (ticks/s) +host_mem_usage 231660 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 4565 # Number of instructions simulated +sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546261523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 303478624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 849740146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546261523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 303478624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 849740146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 52722 # number of cpu cycles simulated +system.cpu.numCycles 52702 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4574 # Number of instructions committed -system.cpu.committedOps 5682 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4565 # Number of instructions committed +system.cpu.committedOps 5672 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 28701 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 28656 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52722 # Number of busy cycles +system.cpu.num_busy_cycles 52702 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use -system.cpu.icache.total_refs 4373 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use +system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits -system.cpu.icache.overall_hits::total 4373 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits +system.cpu.icache.overall_hits::total 4364 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses @@ -119,18 +119,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12824000 system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052232 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052232 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency @@ -157,12 +157,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency @@ -171,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use -system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use +system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits -system.cpu.dcache.overall_hits::total 1919 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits +system.cpu.dcache.overall_hits::total 1918 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -207,26 +207,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7224000 system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068447 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068447 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency @@ -259,14 +259,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index c92fa97a1..d99f33506 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:27 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:52:53 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12671500 because target called exit() +Exiting @ tick 12478500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 69e82fc15..7981b4fdb 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12671500 # Number of ticks simulated -final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12478500 # Number of ticks simulated +final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63611 # Simulator instruction rate (inst/s) -host_op_rate 63597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155871053 # Simulator tick rate (ticks/s) -host_mem_usage 216124 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 84509 # Simulator instruction rate (inst/s) +host_op_rate 84485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203899861 # Simulator tick rate (ticks/s) +host_mem_usage 220092 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25344 # number of cpu cycles simulated +system.cpu.numCycles 24958 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2242 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits +system.cpu.BPredUnit.lookups 2172 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2966 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3014 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2873 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -171,120 +171,120 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8177 # Type of FU issued -system.cpu.iq.rate 0.322640 # Inst issue rate +system.cpu.iq.FU_type_0::total 8121 # Type of FU issued +system.cpu.iq.rate 0.325387 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1464 # number of nop insts executed -system.cpu.iew.exec_refs 3166 # number of memory reference insts executed -system.cpu.iew.exec_branches 1317 # Number of branches executed -system.cpu.iew.exec_stores 1061 # Number of stores executed -system.cpu.iew.exec_rate 0.306305 # Inst execution rate -system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7307 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2841 # num instructions producing a value -system.cpu.iew.wb_consumers 4060 # num instructions consuming a value +system.cpu.iew.exec_nop 1469 # number of nop insts executed +system.cpu.iew.exec_refs 3191 # number of memory reference insts executed +system.cpu.iew.exec_branches 1304 # Number of branches executed +system.cpu.iew.exec_stores 1065 # Number of stores executed +system.cpu.iew.exec_rate 0.311163 # Inst execution rate +system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2836 # num instructions producing a value +system.cpu.iew.wb_consumers 4075 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back +system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,69 +295,69 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22904 # The number of ROB reads -system.cpu.rob.rob_writes 22029 # The number of ROB writes -system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22599 # The number of ROB reads +system.cpu.rob.rob_writes 21853 # The number of ROB writes +system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads -system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10565 # number of integer regfile reads -system.cpu.int_regfile_writes 5131 # number of integer regfile writes +system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10560 # number of integer regfile reads +system.cpu.int_regfile_writes 5130 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 151 # number of misc regfile reads -system.cpu.icache.replacements 19 # number of replacements -system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use -system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use +system.cpu.icache.total_refs 1503 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits -system.cpu.icache.overall_hits::total 1592 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses -system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits +system.cpu.icache.overall_hits::total 1503 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,54 +366,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use -system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use +system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2472 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2472 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2472 # number of overall hits -system.cpu.dcache.overall_hits::total 2472 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits +system.cpu.dcache.overall_hits::total 2489 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses @@ -422,38 +422,38 @@ system.cpu.dcache.demand_misses::cpu.data 472 # n system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses system.cpu.dcache.overall_misses::total 472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,119 +462,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.190745 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.134201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006908 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 341 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 341 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11691000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses +system.cpu.l2cache.overall_misses::total 481 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1768500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1768500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16540500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16540500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 341 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 341 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991202 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index b797dcfe3..584102e9c 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:59:33 -gem5 started Jun 4 2012 14:44:10 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:53:15 gem5 executing on zizzer -command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11243500 because target called exit() +Exiting @ tick 11179000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 975867801..f8f7991bd 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11243500 # Number of ticks simulated -final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11179000 # Number of ticks simulated +final_tick 11179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72271 # Simulator instruction rate (inst/s) -host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140039967 # Simulator tick rate (ticks/s) -host_mem_usage 211876 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 61972 # Simulator instruction rate (inst/s) +host_op_rate 61960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119400246 # Simulator tick rate (ticks/s) +host_mem_usage 216052 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory -system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28864 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2003757044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 578227033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2581984077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2003757044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2003757044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2003757044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 578227033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2581984077 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22488 # number of cpu cycles simulated +system.cpu.numCycles 22359 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2514 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits +system.cpu.BPredUnit.lookups 2487 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2038 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 457 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2063 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 631 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 157 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6834 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14542 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 788 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1412 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 813 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.320439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.737355 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8598 78.07% 78.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 170 1.54% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 167 1.52% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 144 1.31% 82.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 198 1.80% 84.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 151 1.37% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.33% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 107 0.97% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 11.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2252 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 11013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.111230 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650387 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7023 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 884 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2239 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename +system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 359 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 445 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7240 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 304 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2086 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12206 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 201 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10543 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19911 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19856 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5536 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 518 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2072 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1895 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 60 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9264 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 154 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4859 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.841188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.574613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7627 69.25% 69.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1067 9.69% 78.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 747 6.78% 85.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 527 4.79% 90.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 4.35% 94.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 323 2.93% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 151 1.37% 99.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 51 0.46% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 41 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11013 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.35% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 80 44.69% 48.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 93 51.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5707 61.60% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1853 20.00% 81.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1702 18.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9284 # Type of FU issued -system.cpu.iq.rate 0.412842 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9264 # Type of FU issued +system.cpu.iq.rate 0.414330 # Inst issue rate +system.cpu.iq.fu_busy_cnt 179 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019322 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29812 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15773 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8347 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9409 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1110 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10943 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 107 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2072 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1895 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 311 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 389 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8757 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1710 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3258 # number of memory reference insts executed -system.cpu.iew.exec_branches 1391 # Number of branches executed -system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.389274 # Inst execution rate -system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8387 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4351 # num instructions producing a value -system.cpu.iew.wb_consumers 7020 # num instructions consuming a value +system.cpu.iew.exec_refs 3276 # number of memory reference insts executed +system.cpu.iew.exec_branches 1382 # Number of branches executed +system.cpu.iew.exec_stores 1566 # Number of stores executed +system.cpu.iew.exec_rate 0.391654 # Inst execution rate +system.cpu.iew.wb_sent 8550 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8374 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4334 # num instructions producing a value +system.cpu.iew.wb_consumers 6981 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374525 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.620828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5152 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 300 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.567515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.347907 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7783 76.15% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1041 10.19% 86.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 649 6.35% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.50% 95.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.84% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 1.06% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 57 0.56% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.44% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 93 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10220 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,68 +295,68 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21145 # The number of ROB reads -system.cpu.rob.rob_writes 22688 # The number of ROB writes -system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21079 # The number of ROB reads +system.cpu.rob.rob_writes 22698 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11346 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads -system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13921 # number of integer regfile reads -system.cpu.int_regfile_writes 7265 # number of integer regfile writes +system.cpu.cpi 3.855000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.855000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.259403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.259403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13891 # number of integer regfile reads +system.cpu.int_regfile_writes 7248 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use -system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 172.424294 # Cycle average of tags in use +system.cpu.icache.total_refs 1455 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.098592 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits -system.cpu.icache.overall_hits::total 1462 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.424294 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084192 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084192 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1455 # number of overall hits +system.cpu.icache.overall_hits::total 1455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses +system.cpu.icache.overall_misses::total 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15599000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15599000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15599000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15599000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15599000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228935 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228935 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228935 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228935 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228935 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228935 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36108.796296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36108.796296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,12 +365,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses @@ -383,12 +383,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188129 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188129 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188129 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency @@ -397,14 +397,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 63.023619 # Cycle average of tags in use system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. +system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.940594 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015262 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 63.023619 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015387 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015387 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits @@ -413,46 +413,46 @@ system.cpu.dcache.demand_hits::cpu.data 2216 # nu system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits system.cpu.dcache.overall_hits::total 2216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 83 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 86 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 399 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 399 # number of overall misses -system.cpu.dcache.overall_misses::total 399 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2993000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2993000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13580500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13580500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 402 # number of overall misses +system.cpu.dcache.overall_misses::total 402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3106000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3106000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10571500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10571500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13677500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13677500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13677500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13677500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2618 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.054707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.054707 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.153552 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.153552 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.153552 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.153552 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34023.631841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34023.631841 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,58 +461,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1890500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1890500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1748500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033715 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35669.811321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35669.811321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36427.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36427.083333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.260551 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012407 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 30.269313 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000924 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.544564 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 30.715987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000937 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006173 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits @@ -520,60 +520,60 @@ system.cpu.l2cache.demand_hits::total 5 # nu system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 403 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses -system.cpu.l2cache.overall_misses::total 449 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1829000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13862000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1674500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1674500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3503500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15536500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3503500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15536500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987745 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989035 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989035 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34380 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34509.433962 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.022333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34885.416667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34885.416667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34380 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34449.002217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34380 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34449.002217 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,49 +583,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12570500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10908500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3183500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14092000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10908500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3183500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14092000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987745 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989035 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |