diff options
Diffstat (limited to 'tests/quick/se/00.hello')
15 files changed, 1146 insertions, 1125 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index f2874fc12..6e3934424 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,7 +129,7 @@ type=O3Checker children=dtb itb tracer checker=Null clock=1 -cpu_id=-1 +cpu_id=0 defer_registration=false do_checkpoint_insts=true do_quiesce=true @@ -145,7 +145,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -162,8 +161,8 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] @@ -175,8 +174,8 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[4] @@ -188,16 +187,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -216,8 +217,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -489,16 +490,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -520,8 +523,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -530,16 +533,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -571,7 +576,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -589,13 +594,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 3b3dd4083..425371c96 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:18:47 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:20:03 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10843000 because target called exit() +Exiting @ tick 10738000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ca9aa91ca..96198ee3a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10843000 # Number of ticks simulated -final_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10738000 # Number of ticks simulated +final_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27388 # Simulator instruction rate (inst/s) -host_op_rate 34173 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64670790 # Simulator tick rate (ticks/s) -host_mem_usage 232736 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 398 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 28410 # Simulator instruction rate (inst/s) +host_op_rate 35442 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66366492 # Simulator tick rate (ticks/s) +host_mem_usage 227572 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +sim_insts 4596 # Number of instructions simulated +sim_ops 5734 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory +system.physmem.bytes_read::total 25728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory +system.physmem.num_reads::total 402 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5742 # number of cpu cycles simulated +system.cpu.checker.numCycles 5747 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -115,316 +115,316 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 21687 # number of cpu cycles simulated +system.cpu.numCycles 21477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2517 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 676 # Number of BTB hits +system.cpu.BPredUnit.lookups 2491 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12862 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12142 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1997 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2551 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2347 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2220 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 753 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9087 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle +system.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 766 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8841 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9087 # Type of FU issued -system.cpu.iq.rate 0.419007 # Inst issue rate -system.cpu.iq.fu_busy_cnt 210 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8841 # Type of FU issued +system.cpu.iq.rate 0.411650 # Inst issue rate +system.cpu.iq.fu_busy_cnt 213 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3344 # number of memory reference insts executed -system.cpu.iew.exec_branches 1407 # Number of branches executed -system.cpu.iew.exec_stores 1204 # Number of stores executed -system.cpu.iew.exec_rate 0.399318 # Inst execution rate -system.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8190 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3858 # num instructions producing a value -system.cpu.iew.wb_consumers 7806 # num instructions consuming a value +system.cpu.iew.exec_refs 3250 # number of memory reference insts executed +system.cpu.iew.exec_branches 1412 # Number of branches executed +system.cpu.iew.exec_stores 1169 # Number of stores executed +system.cpu.iew.exec_rate 0.393211 # Inst execution rate +system.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8006 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3825 # num instructions producing a value +system.cpu.iew.wb_consumers 7724 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.377646 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back +system.cpu.iew.wb_rate 0.372771 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4596 # Number of instructions committed +system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2138 # Number of memory references committed -system.cpu.commit.loads 1200 # Number of loads committed +system.cpu.commit.refs 2140 # Number of memory references committed +system.cpu.commit.loads 1201 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 944 # Number of branches committed +system.cpu.commit.branches 1008 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4976 # Number of committed integer instructions. +system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23828 # The number of ROB reads -system.cpu.rob.rob_writes 24602 # The number of ROB writes -system.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 4.723807 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads -system.cpu.ipc 0.211694 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39657 # number of integer regfile reads -system.cpu.int_regfile_writes 8076 # number of integer regfile writes +system.cpu.rob.rob_reads 23095 # The number of ROB reads +system.cpu.rob.rob_writes 23459 # The number of ROB writes +system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4596 # Number of Instructions Simulated +system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4596 # Number of Instructions Simulated +system.cpu.cpi 4.672977 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads +system.cpu.ipc 0.213996 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 38788 # number of integer regfile reads +system.cpu.int_regfile_writes 7902 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15863 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use -system.cpu.icache.total_refs 1630 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 15082 # number of misc regfile reads +system.cpu.misc_regfile_writes 26 # number of misc regfile writes +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use +system.cpu.icache.total_refs 1558 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits -system.cpu.icache.overall_hits::total 1630 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses -system.cpu.icache.overall_misses::total 367 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits +system.cpu.icache.overall_hits::total 1558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses +system.cpu.icache.overall_misses::total 373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -433,110 +433,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10405500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10405500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148222 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35153.716216 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35153.716216 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35153.716216 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35153.716216 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 74 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 74 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 74 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10560500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10560500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10560500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10560500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.154842 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35319.397993 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35319.397993 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use -system.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.954141 # Cycle average of tags in use +system.cpu.dcache.total_refs 2354 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.905405 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.954141 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021229 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 602 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 602 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2382 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2382 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2382 # number of overall hits -system.cpu.dcache.overall_hits::total 2382 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits +system.cpu.dcache.overall_hits::total 2329 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses -system.cpu.dcache.overall_misses::total 501 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6900500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6900500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12710500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12710500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7113500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7113500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12639500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19611000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19611000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19611000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19611000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1970 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1970 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19753000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19753000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19753000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2831 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2831 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2831 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2831 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.099583 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.099583 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173777 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173777 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173777 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36318.421053 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36318.421053 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40869.774920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40869.774920 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.177323 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.177323 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -545,124 +545,124 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3667500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3667500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1713000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1713000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5380500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5380500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5380500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5380500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054315 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3692500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3692500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1708000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5400500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5400500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5400500 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40785.714286 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40785.714286 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36110.738255 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36110.738255 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.052278 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052278 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.052278 # 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number of replacements -system.cpu.l2cache.tagsinuse 186.552400 # Cycle average of tags in use -system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.115169 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 187.774695 # Cycle average of tags in use +system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 360 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.108333 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.494709 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.057690 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004288 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001406 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005693 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 141.174021 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.600674 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004308 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001422 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005730 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 22 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10109500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5081500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15191000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 299 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935811 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.898263 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 447 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 447 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.936455 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.903704 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935811 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.907865 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935811 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.907865 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36003.610108 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39552.941176 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36837.016575 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39654.761905 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39654.761905 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37129.950495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36003.610108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39586.614173 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37129.950495 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.936455 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.864865 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.912752 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.936455 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.864865 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.912752 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36105.357143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39779.069767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36968.579235 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39535.714286 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39535.714286 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37232.843137 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36105.357143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39699.218750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37232.843137 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -680,50 +680,50 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 360 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9090000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2983000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12073000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1532500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1532500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9090000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4515500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13605500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9090000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4515500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13605500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.883375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9218000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3041500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9218000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4569000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13787000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9218000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4569000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13787000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.773585 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888889 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899329 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899329 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33158.273381 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 9e38ceef5..f5b7d940d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -512,7 +518,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index b7b5be837..dc9a7546c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:18:36 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:19:07 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10843000 because target called exit() +Exiting @ tick 10738000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index ab4ace327..e082161f0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 10843000 # Number of ticks simulated -final_tick 10843000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10738000 # Number of ticks simulated +final_tick 10738000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 17631 # Simulator instruction rate (inst/s) -host_op_rate 22000 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41635778 # Simulator tick rate (ticks/s) -host_mem_usage 232604 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5729 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory -system.physmem.bytes_read::total 25472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory -system.physmem.num_reads::total 398 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1623167020 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 725998340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2349165360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1623167020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1623167020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1623167020 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 725998340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2349165360 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 30784 # Simulator instruction rate (inst/s) +host_op_rate 38403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71910456 # Simulator tick rate (ticks/s) +host_mem_usage 227312 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +sim_insts 4596 # Number of instructions simulated +sim_ops 5734 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7936 # Number of bytes read from this memory +system.physmem.bytes_read::total 25728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124 # Number of read requests responded to by this memory +system.physmem.num_reads::total 402 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1656919352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 739057553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2395976904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1656919352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1656919352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1656919352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 739057553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2395976904 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,316 +70,316 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 21687 # number of cpu cycles simulated +system.cpu.numCycles 21477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2517 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1836 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 456 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1920 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 676 # Number of BTB hits +system.cpu.BPredUnit.lookups 2491 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1789 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 495 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1964 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 253 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7080 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12862 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2517 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2805 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1740 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2260 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6988 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12142 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 958 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2639 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1622 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2325 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1997 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.230988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.652427 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1931 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.169334 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.586059 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10529 78.96% 78.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 255 1.91% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 171 1.28% 82.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 221 1.66% 83.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 220 1.65% 85.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 289 2.17% 87.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 122 0.91% 88.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 119 0.89% 89.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1408 10.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10418 79.79% 79.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223 1.71% 81.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 193 1.48% 82.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 217 1.66% 84.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 209 1.60% 86.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 285 2.18% 88.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 109 0.83% 89.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 131 1.00% 90.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 9.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13334 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.116060 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.593074 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7240 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2427 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2551 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1028 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 446 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 13057 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115985 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.565349 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7128 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2493 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2402 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 89 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 945 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14296 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13276 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 558 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1028 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7514 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 500 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1638 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2347 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 307 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13390 # Number of instructions processed by rename +system.cpu.rename.SquashCycles 945 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7383 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 539 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1669 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2220 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 301 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12436 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 246 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13047 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 61618 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 60098 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1520 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7374 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 753 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1819 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9087 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5777 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16432 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13334 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.681491 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.365437 # Number of insts issued each cycle +system.cpu.rename.LSQFullEvents 239 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12439 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56552 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56280 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6758 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 766 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2732 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 47 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11190 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8841 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5157 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14543 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13057 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.677108 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.355722 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9565 71.73% 71.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1503 11.27% 83.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 815 6.11% 89.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 548 4.11% 93.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 447 3.35% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 275 2.06% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 0.97% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.31% 99.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9364 71.72% 71.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1488 11.40% 83.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 792 6.07% 89.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 545 4.17% 93.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 428 3.28% 96.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 276 2.11% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 114 0.87% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 42 0.32% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 8 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13334 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13057 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.86% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 142 67.62% 70.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 62 29.52% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.88% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 136 63.85% 65.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 73 34.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5478 60.28% 60.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2349 25.85% 86.26% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1249 13.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5345 60.46% 60.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 8 0.09% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2263 25.60% 86.18% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1222 13.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9087 # Type of FU issued -system.cpu.iq.rate 0.419007 # Inst issue rate -system.cpu.iq.fu_busy_cnt 210 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023110 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31814 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17497 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8174 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8841 # Type of FU issued +system.cpu.iq.rate 0.411650 # Inst issue rate +system.cpu.iq.fu_busy_cnt 213 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024092 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31043 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16402 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7990 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 76 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9277 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9034 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 54 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1634 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1531 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 881 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 653 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1028 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 203 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11780 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 137 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1819 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 945 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 246 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11245 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 116 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2732 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 42 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 334 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 423 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8660 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 427 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 97 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 287 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8445 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2081 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3344 # number of memory reference insts executed -system.cpu.iew.exec_branches 1407 # Number of branches executed -system.cpu.iew.exec_stores 1204 # Number of stores executed -system.cpu.iew.exec_rate 0.399318 # Inst execution rate -system.cpu.iew.wb_sent 8336 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8190 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3858 # num instructions producing a value -system.cpu.iew.wb_consumers 7806 # num instructions consuming a value +system.cpu.iew.exec_refs 3250 # number of memory reference insts executed +system.cpu.iew.exec_branches 1412 # Number of branches executed +system.cpu.iew.exec_stores 1169 # Number of stores executed +system.cpu.iew.exec_rate 0.393211 # Inst execution rate +system.cpu.iew.wb_sent 8142 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8006 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3825 # num instructions producing a value +system.cpu.iew.wb_consumers 7724 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.377646 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494235 # average fanout of values written-back +system.cpu.iew.wb_rate 0.372771 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.495210 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6051 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12307 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.465507 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.263835 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 5517 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 336 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12113 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.473376 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.288273 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9888 80.34% 80.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1205 9.79% 90.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 432 3.51% 93.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 264 2.15% 95.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 159 1.29% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 164 1.33% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 55 0.45% 98.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 38 0.31% 99.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.83% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9737 80.38% 80.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1166 9.63% 90.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 419 3.46% 93.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 269 2.22% 95.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 155 1.28% 96.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 162 1.34% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 54 0.45% 98.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 39 0.32% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 112 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12307 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 12113 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4596 # Number of instructions committed +system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2138 # Number of memory references committed -system.cpu.commit.loads 1200 # Number of loads committed +system.cpu.commit.refs 2140 # Number of memory references committed +system.cpu.commit.loads 1201 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 944 # Number of branches committed +system.cpu.commit.branches 1008 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4976 # Number of committed integer instructions. +system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 112 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23828 # The number of ROB reads -system.cpu.rob.rob_writes 24602 # The number of ROB writes -system.cpu.timesIdled 202 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8353 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 4.723807 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.723807 # CPI: Total CPI of All Threads -system.cpu.ipc 0.211694 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.211694 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39657 # number of integer regfile reads -system.cpu.int_regfile_writes 8076 # number of integer regfile writes +system.cpu.rob.rob_reads 23095 # The number of ROB reads +system.cpu.rob.rob_writes 23459 # The number of ROB writes +system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8420 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4596 # Number of Instructions Simulated +system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4596 # Number of Instructions Simulated +system.cpu.cpi 4.672977 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.672977 # CPI: Total CPI of All Threads +system.cpu.ipc 0.213996 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.213996 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 38788 # number of integer regfile reads +system.cpu.int_regfile_writes 7902 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15863 # number of misc regfile reads -system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 5 # number of replacements -system.cpu.icache.tagsinuse 149.186170 # Cycle average of tags in use -system.cpu.icache.total_refs 1630 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.506757 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 15082 # number of misc regfile reads +system.cpu.misc_regfile_writes 26 # number of misc regfile writes +system.cpu.icache.replacements 4 # number of replacements +system.cpu.icache.tagsinuse 149.911543 # Cycle average of tags in use +system.cpu.icache.total_refs 1558 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.210702 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.186170 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072845 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072845 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1630 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1630 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1630 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1630 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1630 # number of overall hits -system.cpu.icache.overall_hits::total 1630 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 367 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 367 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 367 # number of overall misses -system.cpu.icache.overall_misses::total 367 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13154000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13154000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13154000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13154000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13154000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13154000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1997 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1997 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1997 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183776 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183776 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183776 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183776 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183776 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183776 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35841.961853 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35841.961853 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35841.961853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35841.961853 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35841.961853 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 149.911543 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073199 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073199 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1558 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1558 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1558 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1558 # number of overall hits +system.cpu.icache.overall_hits::total 1558 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses +system.cpu.icache.overall_misses::total 373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13334000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13334000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13334000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13334000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13334000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13334000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1931 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1931 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1931 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1931 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1931 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193164 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.193164 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.193164 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.193164 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.193164 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.193164 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35747.989276 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35747.989276 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35747.989276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35747.989276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35747.989276 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -388,110 +388,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 71 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10405500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10405500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10405500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10405500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148222 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148222 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148222 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148222 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10560500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10560500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154842 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.154842 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154842 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.154842 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35319.397993 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35319.397993 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35319.397993 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35319.397993 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.628845 # Cycle average of tags in use -system.cpu.dcache.total_refs 2404 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.134228 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.954141 # Cycle average of tags in use +system.cpu.dcache.total_refs 2354 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.905405 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.628845 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021150 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021150 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.954141 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021229 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021229 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1727 # 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number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 2329 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2329 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2329 # number of overall hits +system.cpu.dcache.overall_hits::total 2329 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 191 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 191 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 311 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 311 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 501 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 19753000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19753000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19753000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19753000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1918 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1918 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2883 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2883 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2883 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2883 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.096447 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.096447 # miss rate for ReadReq accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2831 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2831 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2831 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2831 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.099583 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.099583 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.340635 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.340635 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173777 # 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miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.177323 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.177323 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37243.455497 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37243.455497 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40641.479100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40641.479100 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39143.712575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39143.712575 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39143.712575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39348.605578 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39348.605578 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39348.605578 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,124 +500,124 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 83 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 85 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 269 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 352 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 352 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 352 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # 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number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9218000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3041500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12259500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1527500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1527500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9218000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4569000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 13787000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9218000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4569000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 13787000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.773585 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888889 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.894382 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929054 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.894382 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33054.545455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 36827.160494 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33912.921348 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36488.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36488.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33054.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36711.382114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34184.673367 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899329 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.929766 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.837838 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899329 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33158.273381 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37091.463415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 34054.166667 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36369.047619 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36369.047619 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33158.273381 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36846.774194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34296.019900 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini index f9ef190bc..1ce31c334 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -80,7 +80,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -95,8 +94,8 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system [system.cpu.checker.itb] @@ -107,8 +106,8 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system [system.cpu.checker.tracer] @@ -122,8 +121,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -138,8 +137,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -154,7 +153,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -171,14 +170,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a902d2024..21ae26652 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:15 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:19:07 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 2fe5ceaba..592f491b0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136961 # Simulator instruction rate (inst/s) -host_op_rate 170823 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 85547635 # Simulator tick rate (ticks/s) -host_mem_usage 223208 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 92985 # Simulator instruction rate (inst/s) +host_op_rate 115998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58104040 # Simulator tick rate (ticks/s) +host_mem_usage 217212 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -129,7 +129,7 @@ system.cpu.committedOps 5729 # Nu system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 25195 # number of times the integer registers were read diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini index 10416c8b5..1c831ee09 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -100,7 +100,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index d40bbcb86..3072fae00 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:04 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:19:53 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index ef6865dff..c3735e13f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2870500 # Number of ticks simulated final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62314 # Simulator instruction rate (inst/s) -host_op_rate 77743 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38944247 # Simulator tick rate (ticks/s) -host_mem_usage 223212 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 116328 # Simulator instruction rate (inst/s) +host_op_rate 145112 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 72682624 # Simulator tick rate (ticks/s) +host_mem_usage 217124 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 5729 # Nu system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 25195 # number of times the integer registers were read diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini index e19a07626..bf0c1dcee 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -181,7 +187,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello +executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index 16fea9a8f..92bf5cdb0 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:19:21 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:19:07 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 0ed449cb9..ae539a028 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000027 # Nu sim_ticks 27316000 # Number of ticks simulated final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 53670 # Simulator instruction rate (inst/s) -host_op_rate 66671 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 321019881 # Simulator tick rate (ticks/s) -host_mem_usage 231588 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 78983 # Simulator instruction rate (inst/s) +host_op_rate 98109 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 472376751 # Simulator tick rate (ticks/s) +host_mem_usage 225996 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -78,7 +78,7 @@ system.cpu.committedOps 5672 # Nu system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 28656 # number of times the integer registers were read |