diff options
Diffstat (limited to 'tests/quick/se/00.hello')
26 files changed, 2472 insertions, 1943 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index b10a33b72..353f5c8e3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 35015500 # Number of ticks simulated -final_tick 35015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 35024500 # Number of ticks simulated +final_tick 35024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57020 # Simulator instruction rate (inst/s) -host_op_rate 57008 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 311836228 # Simulator tick rate (ticks/s) -host_mem_usage 240292 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 173753 # Simulator instruction rate (inst/s) +host_op_rate 173686 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 950177695 # Simulator tick rate (ticks/s) +host_mem_usage 289108 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -19,12 +19,12 @@ system.physmem.bytes_inst_read::cpu.inst 23296 # Nu system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 533 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 974197141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974197141 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665305365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665305365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 974197141 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974197141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 973946809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 973946809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 665134406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665134406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 973946809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 973946809 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -71,7 +71,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34917000 # Total gap between requests +system.physmem.totGap 34926000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -196,15 +196,15 @@ system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # By system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3823500 # Total ticks spent queuing -system.physmem.totMemAccLat 13817250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3928000 # Total ticks spent queuing +system.physmem.totMemAccLat 13921750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7173.55 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7369.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25923.55 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.20 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26119.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 973.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.20 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 973.95 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.61 # Data bus utilization in percentage @@ -216,24 +216,32 @@ system.physmem.readRowHits 435 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65510.32 # Average gap between requests +system.physmem.avgGap 65527.20 # Average gap between requests system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 15500 # Time in different power states system.physmem.memoryStateTime::REF 1040000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 30385500 # Time in different power states +system.physmem.memoryStateTime::ACT 30394500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 974197141 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34112 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 533 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 533 # Request fanout histogram system.membus.reqLayer0.occupancy 618000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) system.membus.respLayer1.occupancy 4976250 # Layer occupancy (ticks) @@ -281,26 +289,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 70031 # number of cpu cycles simulated +system.cpu.numCycles 70049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.942344 # CPI: cycles per instruction -system.cpu.ipc 0.091388 # IPC: instructions per cycle -system.cpu.tickCycles 12510 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57521 # Total number of cycles that the object has spent stopped +system.cpu.cpi 10.945156 # CPI: cycles per instruction +system.cpu.ipc 0.091365 # IPC: instructions per cycle +system.cpu.tickCycles 12515 # Number of cycles that the object actually ticked +system.cpu.idleCycles 57534 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.143820 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 176.176418 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2265 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.205479 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.143820 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.086008 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.086008 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 176.176418 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.086024 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.086024 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 248 # Occupied blocks per task id @@ -319,12 +327,12 @@ system.cpu.icache.demand_misses::cpu.inst 365 # n system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25932750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25932750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25932750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25932750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25932750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25932750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25941750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25941750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25941750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25941750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25941750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25941750 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2630 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2630 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2630 # number of demand (read+write) accesses @@ -337,12 +345,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.138783 system.cpu.icache.demand_miss_rate::total 0.138783 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.138783 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.138783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71048.630137 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71048.630137 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71048.630137 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71048.630137 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71048.630137 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71073.287671 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71073.287671 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71073.287671 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71073.287671 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71073.287671 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -357,26 +365,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25045250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 25045250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25045250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 25045250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25045250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 25045250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25054250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25054250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25054250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25054250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25054250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25054250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138783 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.138783 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138783 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.138783 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68617.123288 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68617.123288 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68617.123288 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68617.123288 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68641.780822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68641.780822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68641.780822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 68641.780822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 976024903 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -384,11 +391,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 73 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 34176 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 626250 # Layer occupancy (ticks) @@ -396,14 +413,14 @@ system.cpu.toL2Bus.respLayer0.utilization 1.8 # L system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.878182 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.917543 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.878182 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007137 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 233.917543 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007139 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id @@ -426,12 +443,12 @@ system.cpu.l2cache.overall_misses::cpu.inst 533 # system.cpu.l2cache.overall_misses::total 533 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 31726750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 31726750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 36782750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36782750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 36782750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36782750 # number of overall miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 5065000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5065000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 36791750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 36791750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 36791750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 36791750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 73 # number of ReadExReq accesses(hits+misses) @@ -450,12 +467,12 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68971.195652 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 68971.195652 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69260.273973 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69260.273973 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69010.787992 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69010.787992 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69010.787992 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69383.561644 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69383.561644 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69027.673546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69027.673546 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69027.673546 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,14 +489,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 533 system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 533 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25965250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25965250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30103250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30103250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30103250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30103250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25964750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25964750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 4147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4147500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 30112250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30112250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 30112250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30112250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -488,24 +505,24 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998127 system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56446.195652 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56446.195652 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56478.893058 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56478.893058 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56445.108696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56445.108696 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 56815.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56815.068493 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56495.778612 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56495.778612 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.053835 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 104.075920 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1968 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.644970 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 104.053835 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.025404 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025404 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 104.075920 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.025409 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025409 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -528,10 +545,10 @@ system.cpu.dcache.demand_misses::cpu.inst 227 # n system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7727250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7727250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8696750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8696750 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 7718250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7718250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 8705750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8705750 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.inst 16424000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 16424000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.inst 16424000 # number of overall miss cycles @@ -552,10 +569,10 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.103417 system.cpu.dcache.demand_miss_rate::total 0.103417 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.103417 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.103417 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75757.352941 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75757.352941 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69574 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69574 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 75669.117647 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75669.117647 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 69646 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69646 # average WriteReq miss latency system.cpu.dcache.demand_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 72352.422907 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::cpu.inst 72352.422907 # average overall miss latency @@ -584,10 +601,10 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7154500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5130500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5130500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 7145500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7145500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 5139500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5139500 # number of WriteReq MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 12285000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 12285000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 12285000 # number of overall MSHR miss cycles @@ -600,10 +617,10 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.076993 system.cpu.dcache.demand_mshr_miss_rate::total 0.076993 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.076993 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.076993 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74526.041667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74526.041667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70280.821918 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70280.821918 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 74432.291667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74432.291667 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 70404.109589 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70404.109589 # average WriteReq mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 72692.307692 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 72692.307692 # average overall mshr miss latency diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index f7bb9a203..b6d7e6ec3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000021 # Nu sim_ticks 20537500 # Number of ticks simulated final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46749 # Simulator instruction rate (inst/s) -host_op_rate 46745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150649735 # Simulator tick rate (ticks/s) -host_mem_usage 236424 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 100086 # Simulator instruction rate (inst/s) +host_op_rate 100066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 322455292 # Simulator tick rate (ticks/s) +host_mem_usage 290128 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # By system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 4551750 # Total ticks spent queuing -system.physmem.totMemAccLat 13683000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4742750 # Total ticks spent queuing +system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9346.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28096.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15339250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1517614121 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 415 # Transaction distribution system.membus.trans_dist::ReadResp 415 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 31168 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 487 # Request fanout histogram system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) @@ -579,7 +587,6 @@ system.cpu.fp_regfile_reads 8 # nu system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1520730371 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution @@ -587,11 +594,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 72 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt index 60119bd53..a2eda1208 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 3208000 # Number of ticks simulated final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 172950 # Simulator instruction rate (inst/s) -host_op_rate 172880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 86758979 # Simulator tick rate (ticks/s) -host_mem_usage 253924 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 1057772 # Simulator instruction rate (inst/s) +host_op_rate 1055326 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 528762156 # Simulator tick rate (ticks/s) +host_mem_usage 277832 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 2087281796 # Wr system.physmem.bw_total::cpu.inst 7980049875 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 4826683292 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12806733167 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12806733167 # Throughput (bytes/s) -system.membus.data_through_bus 41084 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 7583 # Transaction distribution +system.membus.trans_dist::ReadResp 7583 # Transaction distribution +system.membus.trans_dist::WriteReq 865 # Transaction distribution +system.membus.trans_dist::WriteResp 865 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 12800 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4096 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 16896 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 25600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 15484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 41084 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8448 # Request fanout histogram +system.membus.snoop_fanout::mean 0.757576 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.428575 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2048 24.24% 24.24% # Request fanout histogram +system.membus.snoop_fanout::1 6400 75.76% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 8448 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index e6ec389d1..dcfebc3a2 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000033 # Nu sim_ticks 32544000 # Number of ticks simulated final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 550056 # Simulator instruction rate (inst/s) -host_op_rate 549394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2794675827 # Simulator tick rate (ticks/s) -host_mem_usage 262632 # Number of bytes of host memory used +host_inst_rate 485157 # Simulator instruction rate (inst/s) +host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2465828156 # Simulator tick rate (ticks/s) +host_mem_usage 286540 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 546705998 # In system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 877089479 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 373 # Transaction distribution system.membus.trans_dist::ReadResp 373 # Transaction distribution system.membus.trans_dist::ReadExReq 73 # Transaction distribution system.membus.trans_dist::ReadExResp 73 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28544 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) @@ -455,7 +463,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 879056047 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -463,11 +470,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 73 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 894 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28608 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 447 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 447 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 447 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 223500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 418500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 7e0b73788..6f17c0be9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18662000 # Number of ticks simulated final_tick 18662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32674 # Simulator instruction rate (inst/s) -host_op_rate 32664 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 235769003 # Simulator tick rate (ticks/s) -host_mem_usage 238980 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 154264 # Simulator instruction rate (inst/s) +host_op_rate 154144 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1111892278 # Simulator tick rate (ticks/s) +host_mem_usage 287792 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -196,12 +196,12 @@ system.physmem.bytesPerActivate::768-895 3 6.82% 88.64% # By system.physmem.bytesPerActivate::896-1023 1 2.27% 90.91% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 4 9.09% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 44 # Bytes accessed per row activation -system.physmem.totQLat 1654250 # Total ticks spent queuing -system.physmem.totMemAccLat 7429250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1719250 # Total ticks spent queuing +system.physmem.totMemAccLat 7494250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5370.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5581.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24120.94 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24331.98 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1056.26 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1056.26 # Average system read bandwidth in MiByte/s @@ -223,17 +223,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15310750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1056264066 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 616 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 19712 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 308 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 308 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 308 # Request fanout histogram system.membus.reqLayer0.occupancy 362000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) system.membus.respLayer1.occupancy 2870500 # Layer occupancy (ticks) @@ -376,7 +384,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 66880.044843 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66880.044843 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 66880.044843 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1056264066 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -384,11 +391,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 27 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 446 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 616 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 19712 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19712 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 308 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 308 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 381750 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index a87953c0f..286f63d05 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000012 # Nu sim_ticks 11765500 # Number of ticks simulated final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 45706 # Simulator instruction rate (inst/s) -host_op_rate 45696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 225189511 # Simulator tick rate (ticks/s) -host_mem_usage 236100 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 81487 # Simulator instruction rate (inst/s) +host_op_rate 81445 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 401265305 # Simulator tick rate (ticks/s) +host_mem_usage 288836 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # By system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation -system.physmem.totQLat 1710500 # Total ticks spent queuing -system.physmem.totMemAccLat 6810500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1802000 # Total ticks spent queuing +system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6288.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25038.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 260000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 7778000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1479580128 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution system.membus.trans_dist::ReadExReq 24 # Transaction distribution system.membus.trans_dist::ReadExResp 24 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 544 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 17408 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 272 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 272 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 272 # Request fanout histogram system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) @@ -577,7 +585,6 @@ system.cpu.int_regfile_writes 2774 # nu system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1479580128 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 24 # Transaction distribution @@ -585,11 +592,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 24 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 170 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 544 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 17408 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 17408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 272 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 272 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) @@ -717,14 +734,14 @@ system.cpu.l2cache.overall_misses::total 272 # nu system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1692250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1692250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6143750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18850000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6143750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18850000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -750,14 +767,14 @@ system.cpu.l2cache.overall_miss_rate::total 1 # system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70510.416667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70510.416667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69301.470588 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72279.411765 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69301.470588 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -780,14 +797,14 @@ system.cpu.l2cache.overall_mshr_misses::total 272 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1398750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1398750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5100750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15449500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5100750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15449500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -802,22 +819,22 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 1 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58281.250000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58281.250000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60008.823529 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56799.632353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118379 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118379 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id @@ -842,14 +859,14 @@ system.cpu.dcache.demand_misses::cpu.data 198 # n system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7443000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7443000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5304000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5304000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12747000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12747000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12747000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12747000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -866,14 +883,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63615.384615 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63615.384615 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65481.481481 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65481.481481 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64378.787879 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64378.787879 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64378.787879 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -900,12 +917,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 85 system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6230250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6230250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6230250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6230250 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses @@ -916,12 +933,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71572.916667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71572.916667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73297.058824 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73297.058824 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt index 6080ce665..8c96cc883 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000001 # Nu sim_ticks 1297500 # Number of ticks simulated final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 741583 # Simulator instruction rate (inst/s) -host_op_rate 738395 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 370291096 # Simulator tick rate (ticks/s) -host_mem_usage 253628 # Number of bytes of host memory used +host_inst_rate 828617 # Simulator instruction rate (inst/s) +host_op_rate 824640 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 413479924 # Simulator tick rate (ticks/s) +host_mem_usage 276508 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1586127168 # Wr system.physmem.bw_total::cpu.inst 7969171484 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3910597303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11879768786 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11879768786 # Throughput (bytes/s) -system.membus.data_through_bus 15414 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 3000 # Transaction distribution +system.membus.trans_dist::ReadResp 3000 # Transaction distribution +system.membus.trans_dist::WriteReq 294 # Transaction distribution +system.membus.trans_dist::WriteResp 294 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 5170 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1418 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6588 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 10340 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 5074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15414 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 3294 # Request fanout histogram +system.membus.snoop_fanout::mean 0.784760 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.411051 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 709 21.52% 21.52% # Request fanout histogram +system.membus.snoop_fanout::1 2585 78.48% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 3294 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 3ccccfd43..6695f502c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000017 # Nu sim_ticks 16524000 # Number of ticks simulated final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366311 # Simulator instruction rate (inst/s) -host_op_rate 365532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2339184598 # Simulator tick rate (ticks/s) -host_mem_usage 262348 # Number of bytes of host memory used +host_inst_rate 428144 # Simulator instruction rate (inst/s) +host_op_rate 427151 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2733498759 # Simulator tick rate (ticks/s) +host_mem_usage 286260 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 631324135 # In system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 948922779 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 218 # Transaction distribution system.membus.trans_dist::ReadResp 218 # Transaction distribution system.membus.trans_dist::ReadExReq 27 # Transaction distribution system.membus.trans_dist::ReadExResp 27 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15680 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 245 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 245 # Request fanout histogram system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) @@ -449,7 +457,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 948922779 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -457,11 +464,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 27 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 326 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 164 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 15680 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10432 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 245 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 245 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 245 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 122500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 244500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 65ff8dd3e..59eccf84d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000028 # Nu sim_ticks 27911000 # Number of ticks simulated final_tick 27911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 66829 # Simulator instruction rate (inst/s) -host_op_rate 78212 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 404876453 # Simulator tick rate (ticks/s) -host_mem_usage 278412 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 116522 # Simulator instruction rate (inst/s) +host_op_rate 136369 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 705946329 # Simulator tick rate (ticks/s) +host_mem_usage 304192 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -195,12 +195,12 @@ system.physmem.bytesPerActivate::640-767 2 3.12% 79.69% # By system.physmem.bytesPerActivate::768-895 3 4.69% 84.38% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.62% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 64 # Bytes accessed per row activation -system.physmem.totQLat 2525000 # Total ticks spent queuing -system.physmem.totMemAccLat 10400000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2575500 # Total ticks spent queuing +system.physmem.totMemAccLat 10450500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6011.90 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6132.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24761.90 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24882.14 # Average memory access latency per DRAM burst system.physmem.avgRdBW 963.06 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 963.06 # Average system read bandwidth in MiByte/s @@ -222,30 +222,38 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22840500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 963061159 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 377 # Transaction distribution system.membus.trans_dist::ReadResp 377 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 840 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 840 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26880 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26880 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 420 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 420 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 420 # Request fanout histogram system.membus.reqLayer0.occupancy 484000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) system.membus.respLayer1.occupancy 3924000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 14.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 1905 # Number of BP lookups -system.cpu.branchPred.condPredicted 1139 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1903 # Number of BP lookups +system.cpu.branchPred.condPredicted 1138 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1574 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1573 # Number of BTB lookups system.cpu.branchPred.BTBHits 325 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.648030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 223 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 20.661157 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -341,59 +349,59 @@ system.cpu.discardedOps 1208 # Nu system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 12.124674 # CPI: cycles per instruction system.cpu.ipc 0.082476 # IPC: instructions per cycle -system.cpu.tickCycles 10535 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45287 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 10521 # Number of cycles that the object actually ticked +system.cpu.idleCycles 45301 # Total number of cycles that the object has spent stopped system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.198888 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1923 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 162.201432 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 321 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.990654 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.978193 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.198888 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079199 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079199 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 162.201432 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.079200 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.079200 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 318 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155273 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4809 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4809 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1923 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1923 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1923 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1923 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1923 # number of overall hits -system.cpu.icache.overall_hits::total 1923 # number of overall hits +system.cpu.icache.tags.tag_accesses 4801 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4801 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits +system.cpu.icache.overall_hits::total 1919 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 321 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 321 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 321 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 321 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 321 # number of overall misses system.cpu.icache.overall_misses::total 321 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21494250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21494250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21494250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21494250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21494250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21494250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2244 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2244 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2244 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2244 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2244 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143048 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143048 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143048 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143048 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143048 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66960.280374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66960.280374 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66960.280374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66960.280374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66960.280374 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21503250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21503250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21503250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21503250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21503250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21503250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2240 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2240 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2240 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2240 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2240 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143304 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143304 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143304 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143304 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143304 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143304 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66988.317757 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 66988.317757 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 66988.317757 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 66988.317757 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 66988.317757 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,26 +416,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 321 system.cpu.icache.demand_mshr_misses::total 321 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 321 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 321 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20721750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20721750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20721750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20721750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20721750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20721750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143048 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143048 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143048 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143048 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64553.738318 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64553.738318 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64553.738318 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64553.738318 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20730750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20730750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20730750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20730750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20730750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20730750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143304 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143304 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143304 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143304 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64581.775701 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64581.775701 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64581.775701 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 64581.775701 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1070832288 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -435,11 +442,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 43 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 292 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 934 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29888 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 467 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 233500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 546750 # Layer occupancy (ticks) @@ -447,12 +468,12 @@ system.cpu.toL2Bus.respLayer0.utilization 2.0 # L system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.954343 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.957604 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 377 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103448 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.954343 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 195.957604 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id @@ -475,14 +496,14 @@ system.cpu.l2cache.demand_misses::cpu.inst 428 # system.cpu.l2cache.demand_misses::total 428 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 428 # number of overall misses system.cpu.l2cache.overall_misses::total 428 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26168000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26168000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26169000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 26169000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 2824000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2824000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 28992000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28992000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 28992000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28992000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 28993000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 28993000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 28993000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 28993000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 424 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.inst 43 # number of ReadExReq accesses(hits+misses) @@ -499,14 +520,14 @@ system.cpu.l2cache.demand_miss_rate::cpu.inst 0.916488 system.cpu.l2cache.demand_miss_rate::total 0.916488 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.916488 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916488 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67968.831169 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67968.831169 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67971.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67971.428571 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 65674.418605 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65674.418605 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67738.317757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67738.317757 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67738.317757 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67740.654206 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67740.654206 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67740.654206 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -529,14 +550,14 @@ system.cpu.l2cache.demand_mshr_misses::cpu.inst 420 system.cpu.l2cache.demand_mshr_misses::total 420 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 420 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 420 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20973000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20973000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20974000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20974000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 2284000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2284000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23257000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23257000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23257000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23257000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 23258000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23258000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 23258000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.889151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadExReq accesses @@ -545,24 +566,24 @@ system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.899358 system.cpu.l2cache.demand_mshr_miss_rate::total 0.899358 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.899358 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899358 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55631.299735 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55631.299735 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55633.952255 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55633.952255 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 53116.279070 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53116.279070 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55373.809524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55373.809524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55376.190476 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55376.190476 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.663656 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 86.665340 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1919 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 13.143836 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 86.663656 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.inst 0.021158 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021158 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.inst 86.665340 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id @@ -589,14 +610,14 @@ system.cpu.dcache.demand_misses::cpu.inst 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.inst 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6958741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6958741 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 6950741 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6950741 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.inst 4586500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 4586500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 11545241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11545241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 11545241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11545241 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 11537241 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 11537241 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 11537241 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 11537241 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.inst 1166 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1166 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.inst 913 # number of WriteReq accesses(hits+misses) @@ -617,14 +638,14 @@ system.cpu.dcache.demand_miss_rate::cpu.inst 0.087542 system.cpu.dcache.demand_miss_rate::total 0.087542 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.inst 0.087542 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.087542 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60510.791304 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60510.791304 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 60441.226087 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60441.226087 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 68455.223881 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 68455.223881 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63435.390110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63435.390110 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63435.390110 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 63391.434066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 63391.434066 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 63391.434066 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,14 +670,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.inst 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.inst 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6265258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6265258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6257258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6257258 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 2867000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2867000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9132258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9132258 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9132258 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9132258 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 9124258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9124258 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 9124258 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9124258 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.088336 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088336 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.047097 # mshr miss rate for WriteReq accesses @@ -665,14 +686,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.070226 system.cpu.dcache.demand_mshr_miss_rate::total 0.070226 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.070226 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.070226 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.747573 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60827.747573 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 60750.077670 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60750.077670 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 66674.418605 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66674.418605 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62549.712329 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62549.712329 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 62494.917808 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 62494.917808 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index a4baa9644..bbf908c21 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000016 # Nu sim_ticks 16223000 # Number of ticks simulated final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32617 # Simulator instruction rate (inst/s) -host_op_rate 38195 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115221437 # Simulator tick rate (ticks/s) -host_mem_usage 253076 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 55920 # Simulator instruction rate (inst/s) +host_op_rate 65484 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197542740 # Simulator tick rate (ticks/s) +host_mem_usage 304472 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # By system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2970000 # Total ticks spent queuing -system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3126000 # Total ticks spent queuing +system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s @@ -226,17 +226,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1566171485 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25408 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 397 # Request fanout histogram system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) @@ -718,7 +726,6 @@ system.cpu.cc_regfile_reads 28734 # nu system.cpu.cc_regfile_writes 3302 # number of cc regfile writes system.cpu.misc_regfile_reads 3189 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution @@ -726,11 +733,29 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 42 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) @@ -738,14 +763,14 @@ system.cpu.toL2Bus.respLayer0.utilization 3.0 # L system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id @@ -764,12 +789,12 @@ system.cpu.icache.demand_misses::cpu.inst 402 # n system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses @@ -782,12 +807,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -808,36 +833,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 294 system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id @@ -864,16 +889,16 @@ system.cpu.l2cache.demand_misses::total 402 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) @@ -897,16 +922,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.911565 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -933,16 +958,16 @@ system.cpu.l2cache.demand_mshr_misses::total 397 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses @@ -955,27 +980,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id @@ -1004,16 +1029,16 @@ system.cpu.dcache.demand_misses::cpu.data 521 # n system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -1036,16 +1061,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -1072,14 +1097,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses @@ -1088,14 +1113,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index adfd7b504..f52a81778 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,62 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16223000 # Number of ticks simulated -final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 11859500 # Number of ticks simulated +final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35590 # Simulator instruction rate (inst/s) -host_op_rate 41676 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 125719954 # Simulator tick rate (ticks/s) -host_mem_usage 252016 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 50616 # Simulator instruction rate (inst/s) +host_op_rate 59274 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 130716325 # Simulator tick rate (ticks/s) +host_mem_usage 300356 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory +system.physmem.bytes_read::total 46848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory +system.physmem.num_reads::total 732 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 733 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 90 # Per bank write bursts -system.physmem.perBankRdBursts::1 46 # Per bank write bursts -system.physmem.perBankRdBursts::2 20 # Per bank write bursts -system.physmem.perBankRdBursts::3 43 # Per bank write bursts -system.physmem.perBankRdBursts::4 18 # Per bank write bursts -system.physmem.perBankRdBursts::5 32 # Per bank write bursts -system.physmem.perBankRdBursts::6 35 # Per bank write bursts -system.physmem.perBankRdBursts::7 10 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 8 # Per bank write bursts -system.physmem.perBankRdBursts::10 28 # Per bank write bursts -system.physmem.perBankRdBursts::11 42 # Per bank write bursts -system.physmem.perBankRdBursts::12 9 # Per bank write bursts -system.physmem.perBankRdBursts::13 6 # Per bank write bursts +system.physmem.perBankRdBursts::0 143 # Per bank write bursts +system.physmem.perBankRdBursts::1 90 # Per bank write bursts +system.physmem.perBankRdBursts::2 40 # Per bank write bursts +system.physmem.perBankRdBursts::3 73 # Per bank write bursts +system.physmem.perBankRdBursts::4 58 # Per bank write bursts +system.physmem.perBankRdBursts::5 88 # Per bank write bursts +system.physmem.perBankRdBursts::6 52 # Per bank write bursts +system.physmem.perBankRdBursts::7 18 # Per bank write bursts +system.physmem.perBankRdBursts::8 12 # Per bank write bursts +system.physmem.perBankRdBursts::9 28 # Per bank write bursts +system.physmem.perBankRdBursts::10 34 # Per bank write bursts +system.physmem.perBankRdBursts::11 47 # Per bank write bursts +system.physmem.perBankRdBursts::12 17 # Per bank write bursts +system.physmem.perBankRdBursts::13 19 # Per bank write bursts system.physmem.perBankRdBursts::14 0 # Per bank write bursts -system.physmem.perBankRdBursts::15 6 # Per bank write bursts +system.physmem.perBankRdBursts::15 14 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16156000 # Total gap between requests +system.physmem.totGap 11846500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 733 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,22 +94,22 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -186,71 +190,80 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2970000 # Total ticks spent queuing -system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation +system.physmem.totQLat 17284989 # Total ticks spent queuing +system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.24 # Data bus utilization in percentage -system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 30.90 # Data bus utilization in percentage +system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 662 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40695.21 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 11000 # Time in different power states -system.physmem.memoryStateTime::REF 520000 # Time in different power states +system.physmem.avgGap 16161.66 # Average gap between requests +system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem.memoryStateTime::REF 260000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT 7800750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1566171485 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution -system.membus.trans_dist::ReadExReq 42 # Transaction distribution -system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 25408 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 704 # Transaction distribution +system.membus.trans_dist::ReadResp 702 # Transaction distribution +system.membus.trans_dist::ReadExReq 29 # Transaction distribution +system.membus.trans_dist::ReadExResp 29 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 733 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 733 # Request fanout histogram +system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 55.9 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 2638 # Number of BP lookups -system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 783 # Number of BTB hits +system.cpu.branchPred.lookups 2560 # Number of BP lookups +system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups +system.cpu.branchPred.BTBHits 497 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -336,237 +349,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32447 # number of cpu cycles simulated +system.cpu.numCycles 23720 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2145 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups +system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5106 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4105 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8358 # Type of FU issued -system.cpu.iq.rate 0.257589 # Inst issue rate -system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 7242 # Type of FU issued +system.cpu.iq.rate 0.305312 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3148 # number of memory reference insts executed -system.cpu.iew.exec_branches 1457 # Number of branches executed -system.cpu.iew.exec_stores 1240 # Number of stores executed -system.cpu.iew.exec_rate 0.248498 # Inst execution rate -system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7601 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3572 # num instructions producing a value -system.cpu.iew.wb_consumers 6998 # num instructions consuming a value +system.cpu.iew.exec_nop 14 # number of nop insts executed +system.cpu.iew.exec_refs 2449 # number of memory reference insts executed +system.cpu.iew.exec_branches 1283 # Number of branches executed +system.cpu.iew.exec_stores 1021 # Number of stores executed +system.cpu.iew.exec_rate 0.287858 # Inst execution rate +system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6654 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3045 # num instructions producing a value +system.cpu.iew.wb_consumers 5519 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -612,403 +622,449 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21719 # The number of ROB writes -system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24066 # The number of ROB reads +system.cpu.rob.rob_writes 16749 # The number of ROB writes +system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7944 # number of integer regfile reads -system.cpu.int_regfile_writes 4420 # number of integer regfile writes -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.cc_regfile_reads 28734 # number of cc regfile reads -system.cpu.cc_regfile_writes 3302 # number of cc regfile writes -system.cpu.misc_regfile_reads 3189 # number of misc regfile reads +system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads +system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6786 # number of integer regfile reads +system.cpu.int_regfile_writes 3839 # number of integer regfile writes +system.cpu.fp_regfile_reads 16 # number of floating regfile reads +system.cpu.cc_regfile_reads 24301 # number of cc regfile reads +system.cpu.cc_regfile_writes 2919 # number of cc regfile writes +system.cpu.misc_regfile_reads 2642 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. +system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1026 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) +system.cpu.icache.tags.replacements 47 # number of replacements +system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits -system.cpu.icache.overall_hits::total 1666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses -system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8536 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits +system.cpu.icache.overall_hits::total 3784 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses +system.cpu.icache.overall_misses::total 332 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated +system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 35 # 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average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 355 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # 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number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # 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Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 715 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses +system.cpu.dcache.overall_misses::total 392 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index f5795e533..9b7b2bcb6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109620 # Simulator instruction rate (inst/s) -host_op_rate 128318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64270947 # Simulator tick rate (ticks/s) -host_mem_usage 268656 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 582910 # Simulator instruction rate (inst/s) +host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 341032781 # Simulator tick rate (ticks/s) +host_mem_usage 293692 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,34 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9855260716 # Throughput (bytes/s) -system.membus.data_through_bus 26555 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index efe28c206..73cde8525 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133655 # Simulator instruction rate (inst/s) -host_op_rate 156442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78348823 # Simulator tick rate (ticks/s) -host_mem_usage 267596 # Number of bytes of host memory used -host_seconds 0.03 # Real time elapsed on the host +host_inst_rate 685428 # Simulator instruction rate (inst/s) +host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 400788339 # Simulator tick rate (ticks/s) +host_mem_usage 292412 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,34 @@ system.physmem.bw_write::total 1353868992 # Wr system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 9855260716 # Throughput (bytes/s) -system.membus.data_through_bus 26555 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 5596 # Transaction distribution +system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.membus.trans_dist::WriteReq 913 # Transaction distribution +system.membus.trans_dist::WriteResp 913 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6531 # Request fanout histogram +system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 4 # Request fanout histogram +system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::total 6531 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index f26a07dcf..8f2c9257f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000026 # Nu sim_ticks 25815000 # Number of ticks simulated final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 85918 # Simulator instruction rate (inst/s) -host_op_rate 100276 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 485659481 # Simulator tick rate (ticks/s) -host_mem_usage 277384 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 367819 # Simulator instruction rate (inst/s) +host_op_rate 428893 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2075494452 # Simulator tick rate (ticks/s) +host_mem_usage 302164 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 557815224 # In system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 867712570 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 307 # Transaction distribution system.membus.trans_dist::ReadResp 307 # Transaction distribution system.membus.trans_dist::ReadExReq 43 # Transaction distribution system.membus.trans_dist::ReadExResp 43 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 22400 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 350 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 350 # Request fanout histogram system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) @@ -520,7 +528,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 947046291 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution @@ -528,11 +535,25 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 43 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 12868f8fc..2de82825c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000025 # Nu sim_ticks 24907000 # Number of ticks simulated final_tick 24907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84163 # Simulator instruction rate (inst/s) -host_op_rate 84145 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360406899 # Simulator tick rate (ticks/s) -host_mem_usage 264444 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 110455 # Simulator instruction rate (inst/s) +host_op_rate 110427 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 472950648 # Simulator tick rate (ticks/s) +host_mem_usage 286112 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # By system.physmem.bytesPerActivate::768-895 3 2.83% 95.28% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.72% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation -system.physmem.totQLat 4873000 # Total ticks spent queuing -system.physmem.totMemAccLat 13404250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4936500 # Total ticks spent queuing +system.physmem.totMemAccLat 13467750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10709.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10849.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29459.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29599.45 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1169.15 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1169.15 # Average system read bandwidth in MiByte/s @@ -226,17 +226,25 @@ system.physmem.memoryStateTime::REF 780000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 22841500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1169149235 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 404 # Transaction distribution system.membus.trans_dist::ReadResp 404 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 910 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 910 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 29120 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 29120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 455 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 455 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 455 # Request fanout histogram system.membus.reqLayer0.occupancy 552000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) system.membus.respLayer1.occupancy 4259500 # Layer occupancy (ticks) @@ -292,12 +300,12 @@ system.cpu.execution_unit.executions 3133 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9486 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9484 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 44432 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5383 # Number of cycles cpu stages are processed. -system.cpu.activity 10.805982 # Percentage of cycles cpu is active +system.cpu.idleCycles 44434 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5381 # Number of cycles cpu stages are processed. +system.cpu.activity 10.801967 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -315,30 +323,30 @@ system.cpu.cpi_total 8.568111 # CP system.cpu.ipc 0.116712 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.116712 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 46167 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3648 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.323095 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 47002 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2813 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.646894 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 46168 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3647 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 7.321088 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 47003 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2812 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 5.644886 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 47048 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 2767 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 5.554552 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage3.idleCycles 48577 # Number of cycles 0 instructions are processed. system.cpu.stage3.runCycles 1238 # Number of cycles 1+ instructions are processed. system.cpu.stage3.utilization 2.485195 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46927 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2888 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.797451 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 46929 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2886 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 5.793436 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 150.585033 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 150.581339 # Cycle average of tags in use system.cpu.icache.tags.total_refs 428 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1.341693 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.585033 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073528 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 150.581339 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073526 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 306 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id @@ -357,12 +365,12 @@ system.cpu.icache.demand_misses::cpu.inst 350 # n system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25291750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25291750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25291750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25291750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25291750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25291750 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25285250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25285250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25285250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25285250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25285250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25285250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 778 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 778 # number of demand (read+write) accesses @@ -375,12 +383,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.449871 system.cpu.icache.demand_miss_rate::total 0.449871 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.449871 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.449871 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72262.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 72262.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 72262.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 72262.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 72262.142857 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72243.571429 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72243.571429 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72243.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72243.571429 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72243.571429 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -401,26 +409,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 319 system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22956750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22956750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22956750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22956750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22956750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22956750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22950250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22950250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22950250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22950250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22950250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22950250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.410026 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.410026 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.410026 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.410026 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71964.733542 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71964.733542 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71964.733542 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71964.733542 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71944.357367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71944.357367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71944.357367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 71944.357367 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1174288353 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 406 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -428,11 +435,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 51 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 638 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 914 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 29248 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 457 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 457 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 457 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 228500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 538750 # Layer occupancy (ticks) @@ -440,13 +457,13 @@ system.cpu.toL2Bus.respLayer0.utilization 2.2 # L system.cpu.toL2Bus.respLayer1.occupancy 226250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 208.347330 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 208.342392 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.267110 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.080220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 152.263135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.079256 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004647 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001711 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006358 # Average percentage of cache occupancy @@ -473,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22611250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6877000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29488250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3810250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3810250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22611250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10687250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33298500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22611250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10687250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33298500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22604750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6885000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29489750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3812750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3812750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22604750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10697750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33302500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22604750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10697750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33302500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -506,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71328.864353 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79045.977011 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72990.717822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74710.784314 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74710.784314 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73183.516484 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71328.864353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77443.840580 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73183.516484 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71308.359621 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79137.931034 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72994.430693 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74759.803922 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74759.803922 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71308.359621 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77519.927536 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73192.307692 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71308.359621 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77519.927536 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73192.307692 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18629250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5798500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24427750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18629250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8965250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27594500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18629250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8965250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27594500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18622750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5806500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24429250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18622750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8975750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 27598500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18622750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8975750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 27598500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -558,25 +575,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58767.350158 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66649.425287 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60464.727723 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62093.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62093.137255 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58767.350158 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64965.579710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60647.252747 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58746.845426 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66741.379310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60468.440594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62142.156863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62142.156863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58746.845426 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65041.666667 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60656.043956 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58746.845426 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65041.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60656.043956 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 90.296415 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 90.295130 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1638 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 11.869565 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 90.296415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 90.295130 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022045 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id @@ -601,14 +618,14 @@ system.cpu.dcache.demand_misses::cpu.data 450 # n system.cpu.dcache.demand_misses::total 450 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 450 # number of overall misses system.cpu.dcache.overall_misses::total 450 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7634750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7634750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21637250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21637250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29272000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29272000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29272000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29272000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7642750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7642750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21639750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21639750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 29282500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 29282500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 29282500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29282500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -625,14 +642,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.215517 system.cpu.dcache.demand_miss_rate::total 0.215517 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.215517 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.215517 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78708.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 78708.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61295.325779 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61295.325779 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65048.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65048.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65048.888889 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78791.237113 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78791.237113 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61302.407932 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 61302.407932 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65072.222222 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65072.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65072.222222 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65072.222222 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked @@ -657,14 +674,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6970500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6970500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3864250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3864250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10834750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10834750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10834750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10834750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6978500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10845250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10845250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10845250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10845250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -673,14 +690,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80120.689655 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80120.689655 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75769.607843 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75769.607843 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78512.681159 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78512.681159 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80212.643678 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80212.643678 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75818.627451 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75818.627451 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78588.768116 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78588.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78588.768116 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78588.768116 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 8c5d2b15c..cc5bb948f 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000022 # Nu sim_ticks 21611500 # Number of ticks simulated final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 39362 # Simulator instruction rate (inst/s) -host_op_rate 39354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 164927772 # Simulator tick rate (ticks/s) -host_mem_usage 235848 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 87050 # Simulator instruction rate (inst/s) +host_op_rate 87030 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 364707967 # Simulator tick rate (ticks/s) +host_mem_usage 288672 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -199,12 +199,12 @@ system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # By system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation -system.physmem.totQLat 5548500 # Total ticks spent queuing -system.physmem.totMemAccLat 14529750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 5601000 # Total ticks spent queuing +system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11583.51 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30333.51 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s @@ -226,20 +226,28 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1418504037 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 428 # Transaction distribution system.membus.trans_dist::ReadResp 428 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30656 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 479 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 479 # Request fanout histogram system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4492750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 20.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 2196 # Number of BP lookups @@ -562,7 +570,6 @@ system.cpu.int_regfile_writes 5412 # nu system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 164 # number of misc regfile reads -system.cpu.toL2Bus.throughput 1427388196 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -570,11 +577,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 51 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 30848 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) @@ -582,14 +599,14 @@ system.cpu.toL2Bus.respLayer0.utilization 2.7 # L system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 161.374264 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.374264 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078796 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078796 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id @@ -608,12 +625,12 @@ system.cpu.icache.demand_misses::cpu.inst 453 # n system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses system.cpu.icache.overall_misses::total 453 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31448500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31448500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31448500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31448500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31448500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31448500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses @@ -626,12 +643,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69422.737307 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69422.737307 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -652,33 +669,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 340 system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24624500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24624500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24624500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24624500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72425 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72425 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 222.300532 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 428 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007009 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.614658 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685875 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004993 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001791 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.006784 # Average percentage of cache occupancy @@ -705,17 +722,17 @@ system.cpu.l2cache.demand_misses::total 479 # nu system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 479 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24254500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7288250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31542750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4058000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4058000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24254500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11346250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35600750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24254500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11346250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35600750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 431 # number of ReadReq accesses(hits+misses) @@ -738,17 +755,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993776 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991176 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993776 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71971.810089 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80090.659341 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73698.014019 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79568.627451 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79568.627451 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74323.068894 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74323.068894 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -768,17 +785,17 @@ system.cpu.l2cache.demand_mshr_misses::total 479 system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 479 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19999000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6168250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26167250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3423500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3423500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19999000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9591750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29590750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19999000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9591750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29590750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses @@ -790,25 +807,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993776 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 92.430317 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id @@ -833,14 +850,14 @@ system.cpu.dcache.demand_misses::cpu.data 531 # n system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses system.cpu.dcache.overall_misses::total 531 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -857,14 +874,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -889,14 +906,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -905,14 +922,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt index c5418ef55..49c05c732 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2907000 # Number of ticks simulated final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1298058 # Simulator instruction rate (inst/s) -host_op_rate 1293725 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 644853594 # Simulator tick rate (ticks/s) -host_mem_usage 255756 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host +host_inst_rate 972729 # Simulator instruction rate (inst/s) +host_op_rate 970456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 484177215 # Simulator tick rate (ticks/s) +host_mem_usage 275596 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1258341933 # Wr system.physmem.bw_total::cpu.inst 8001375989 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2762985896 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10764361885 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10764361885 # Throughput (bytes/s) -system.membus.data_through_bus 31292 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 6978 # Transaction distribution +system.membus.trans_dist::ReadResp 6978 # Transaction distribution +system.membus.trans_dist::WriteReq 925 # Transaction distribution +system.membus.trans_dist::WriteResp 925 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11630 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15806 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23260 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31292 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7903 # Request fanout histogram +system.membus.snoop_fanout::mean 0.735797 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.440936 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2088 26.42% 26.42% # Request fanout histogram +system.membus.snoop_fanout::1 5815 73.58% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7903 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index ee2cc6627..a40ed7ca5 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000032 # Nu sim_ticks 31633000 # Number of ticks simulated final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 474922 # Simulator instruction rate (inst/s) -host_op_rate 474341 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2577866515 # Simulator tick rate (ticks/s) -host_mem_usage 263440 # Number of bytes of host memory used +host_inst_rate 442331 # Simulator instruction rate (inst/s) +host_op_rate 441894 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2401898254 # Simulator tick rate (ticks/s) +host_mem_usage 285092 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 608984289 # In system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 888186388 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 388 # Transaction distribution system.membus.trans_dist::ReadResp 388 # Transaction distribution system.membus.trans_dist::ReadExReq 51 # Transaction distribution system.membus.trans_dist::ReadExResp 51 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28096 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 439 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 439 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 439 # Request fanout histogram system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) @@ -441,7 +449,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 892232795 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution @@ -449,11 +456,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 51 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28224 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 895c59829..2b23aa030 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 18857500 # Number of ticks simulated final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41326 # Simulator instruction rate (inst/s) -host_op_rate 41320 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 134509153 # Simulator tick rate (ticks/s) -host_mem_usage 232584 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 98075 # Simulator instruction rate (inst/s) +host_op_rate 98051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 319158839 # Simulator tick rate (ticks/s) +host_mem_usage 285824 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -200,12 +200,12 @@ system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # By system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3609000 # Total ticks spent queuing -system.physmem.totMemAccLat 11934000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3635500 # Total ticks spent queuing +system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8128.38 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26878.38 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s @@ -227,17 +227,25 @@ system.physmem.memoryStateTime::REF 520000 # Ti system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15315250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1506880552 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution system.membus.trans_dist::ReadExResp 47 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 28416 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 444 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 444 # Request fanout histogram system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) @@ -563,7 +571,6 @@ system.cpu.int_regfile_reads 13743 # nu system.cpu.int_regfile_writes 7176 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes -system.cpu.toL2Bus.throughput 1530637677 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution @@ -571,11 +578,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 47 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 28864 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt index bcfd2d5d0..080dd7c2e 100644 --- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000003 # Nu sim_ticks 2896000 # Number of ticks simulated final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1148266 # Simulator instruction rate (inst/s) -host_op_rate 1144862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570752858 # Simulator tick rate (ticks/s) -host_mem_usage 250716 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 1326844 # Simulator instruction rate (inst/s) +host_op_rate 1322603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 659230594 # Simulator tick rate (ticks/s) +host_mem_usage 274036 # Number of bytes of host memory used +host_seconds 0.00 # Real time elapsed on the host sim_insts 5793 # Number of instructions simulated sim_ops 5793 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1453383978 # Wr system.physmem.bw_total::cpu.inst 8001381215 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2737914365 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 10739295580 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 10739295580 # Throughput (bytes/s) -system.membus.data_through_bus 31101 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 6754 # Transaction distribution +system.membus.trans_dist::ReadResp 6754 # Transaction distribution +system.membus.trans_dist::WriteReq 1046 # Transaction distribution +system.membus.trans_dist::WriteResp 1046 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 11586 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 4014 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15600 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 23172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 7929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31101 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7800 # Request fanout histogram +system.membus.snoop_fanout::mean 0.742692 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.437178 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2007 25.73% 25.73% # Request fanout histogram +system.membus.snoop_fanout::1 5793 74.27% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7800 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 90109d140..8a50d5754 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20918500 # Number of ticks simulated -final_tick 20918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 20927500 # Number of ticks simulated +final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69876 # Simulator instruction rate (inst/s) -host_op_rate 69862 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274294219 # Simulator tick rate (ticks/s) -host_mem_usage 270808 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 84066 # Simulator instruction rate (inst/s) +host_op_rate 84047 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 330123200 # Simulator tick rate (ticks/s) +host_mem_usage 286520 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 884193417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 409972034 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1294165452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 884193417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 884193417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 884193417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 409972034 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1294165452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 883813164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 409795723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1293608888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 883813164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 883813164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 883813164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 409795723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1293608888 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20849000 # Total gap between requests +system.physmem.totGap 20858000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -198,15 +198,15 @@ system.physmem.bytesPerActivate::512-639 8 10.81% 87.84% # By system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation -system.physmem.totQLat 3773250 # Total ticks spent queuing -system.physmem.totMemAccLat 11704500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3885750 # Total ticks spent queuing +system.physmem.totMemAccLat 11817000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8920.21 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9186.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27670.21 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1294.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27936.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1293.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1294.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1293.61 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 10.11 # Data bus utilization in percentage @@ -218,24 +218,32 @@ system.physmem.readRowHits 339 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49288.42 # Average gap between requests +system.physmem.avgGap 49309.69 # Average gap between requests system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 13500 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 15312750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1294165452 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 342 # Transaction distribution system.membus.trans_dist::ReadResp 342 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 27072 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 423 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 423 # Request fanout histogram system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) @@ -251,7 +259,7 @@ system.cpu.branchPred.BTBHitPct 43.484736 # BT system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41838 # number of cpu cycles simulated +system.cpu.numCycles 41856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). @@ -273,12 +281,12 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9651 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 422 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35590 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6248 # Number of cycles cpu stages are processed. -system.cpu.activity 14.933792 # Percentage of cycles cpu is active +system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 35611 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. +system.cpu.activity 14.920203 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -290,36 +298,36 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.853952 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 7.857331 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.853952 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127324 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 7.857331 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127270 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127324 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37198 # Number of cycles 0 instructions are processed. +system.cpu.ipc_total 0.127270 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 37216 # Number of cycles 0 instructions are processed. system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.090396 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38644 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3194 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.634208 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38804 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.251781 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40862 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 976 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.332807 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38681 # Number of cycles 0 instructions are processed. +system.cpu.stage0.utilization 11.085627 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 38661 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.633314 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 38823 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.246273 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 40881 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.329415 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.545772 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.676310 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.676310 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069666 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069666 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 142.708262 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.069682 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.069682 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id @@ -338,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 366 # n system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25425250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25425250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25425250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25425250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25425250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25425250 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25412000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25412000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25412000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25412000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25412000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25412000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses @@ -356,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69467.896175 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69467.896175 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69467.896175 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69467.896175 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69467.896175 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69431.693989 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69431.693989 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69431.693989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69431.693989 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,26 +390,25 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20653250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20653250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20653250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20653250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20653250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20653250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20639500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20639500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20639500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20639500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20639500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20639500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70973.367698 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70973.367698 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70973.367698 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70973.367698 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70926.116838 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70926.116838 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 1303343930 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -409,31 +416,41 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 81 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 27264 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 217000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.122448 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.106217 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.016231 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005161 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.138007 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.023105 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000825 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005162 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses @@ -457,17 +474,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20334750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24350750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5999500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20334750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10015500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30350250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20334750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10015500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30350250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20321000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4025000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24346000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6008250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 20321000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10033250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30354250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 20321000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10033250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30354250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -490,17 +507,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70362.456747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75773.584906 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71201.023392 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74067.901235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74067.901235 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70362.456747 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74742.537313 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71750 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70314.878893 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75943.396226 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.134503 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74175.925926 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74175.925926 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74875 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 71759.456265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74875 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 71759.456265 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -520,17 +537,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16720750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3361000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20081750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5004000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5004000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16720750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25085750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16720750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25085750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16706500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20076500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16706500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8383250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25089750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16706500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8383250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25089750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -542,27 +559,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57857.266436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63415.094340 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58718.567251 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61777.777778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61777.777778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57857.266436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62425.373134 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59304.373522 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57807.958478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63584.905660 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58703.216374 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61891.975309 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61891.975309 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.354091 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.354091 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020838 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020838 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id @@ -585,14 +602,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4579750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4579750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28882250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28882250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33462000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33462000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33462000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33462000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -609,14 +626,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75077.868852 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75077.868852 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69932.808717 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69932.808717 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70594.936709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70594.936709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70594.936709 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked @@ -641,14 +658,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4082500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6083000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6083000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10165500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10165500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10165500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -657,14 +674,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75601.851852 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75601.851852 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75098.765432 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75098.765432 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75300 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75300 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt index 0e41891dc..e454f5068 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1015247 # Simulator instruction rate (inst/s) -host_op_rate 1012545 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 510902541 # Simulator tick rate (ticks/s) -host_mem_usage 261064 # Number of bytes of host memory used +host_inst_rate 399685 # Simulator instruction rate (inst/s) +host_op_rate 399265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 201759641 # Simulator tick rate (ticks/s) +host_mem_usage 276260 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -35,9 +35,27 @@ system.physmem.bw_write::total 1879755057 # Wr system.physmem.bw_total::cpu.inst 7971794396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3587678605 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11559473001 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 11559473001 # Throughput (bytes/s) -system.membus.data_through_bus 31147 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 6085 # Transaction distribution +system.membus.trans_dist::ReadResp 6085 # Transaction distribution +system.membus.trans_dist::WriteReq 673 # Transaction distribution +system.membus.trans_dist::WriteResp 673 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 10740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 2776 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13516 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 21480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 9667 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31147 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6758 # Request fanout histogram +system.membus.snoop_fanout::mean 0.794614 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.404013 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1388 20.54% 20.54% # Request fanout histogram +system.membus.snoop_fanout::1 5370 79.46% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 6758 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 5390 # number of cpu cycles simulated diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index f251b736b..706af6d1d 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 27800000 # Number of ticks simulated final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 487107 # Simulator instruction rate (inst/s) -host_op_rate 486440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2535570960 # Simulator tick rate (ticks/s) -host_mem_usage 269788 # Number of bytes of host memory used +host_inst_rate 583909 # Simulator instruction rate (inst/s) +host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3038583452 # Simulator tick rate (ticks/s) +host_mem_usage 285748 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -29,17 +29,25 @@ system.physmem.bw_inst_read::total 587050360 # In system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 895539568 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 308 # Transaction distribution system.membus.trans_dist::ReadResp 308 # Transaction distribution system.membus.trans_dist::ReadExReq 81 # Transaction distribution system.membus.trans_dist::ReadExResp 81 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 24896 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 389 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 389 # Request fanout histogram system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) @@ -426,7 +434,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 902446043 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -434,11 +441,21 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 81 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 514 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 784 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 25088 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 25088 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 392 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 392 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 392 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 196000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 385500 # Layer occupancy (ticks) diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index f7173c445..0db4f4424 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19744000 # Number of ticks simulated -final_tick 19744000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19678000 # Number of ticks simulated +final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27433 # Simulator instruction rate (inst/s) -host_op_rate 49695 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100653274 # Simulator tick rate (ticks/s) -host_mem_usage 249652 # Number of bytes of host memory used -host_seconds 0.20 # Real time elapsed on the host +host_inst_rate 48979 # Simulator instruction rate (inst/s) +host_op_rate 88725 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 179100946 # Simulator tick rate (ticks/s) +host_mem_usage 305852 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 891410049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 457050243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1348460292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 891410049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 891410049 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 891410049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 457050243 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1348460292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19695500 # Total gap between requests +system.physmem.totGap 19629500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -188,44 +188,43 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 159.132678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.193096 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 35 35.71% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32 32.65% 68.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 12 12.24% 80.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 4076000 # Total ticks spent queuing -system.physmem.totMemAccLat 11894750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 4347000 # Total ticks spent queuing +system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9774.58 # Average queueing delay per DRAM burst +system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28524.58 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1351.70 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1351.70 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.56 # Data bus utilization in percentage -system.physmem.busUtilRead 10.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.60 # Data bus utilization in percentage +system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 309 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47231.41 # Average gap between requests +system.physmem.avgGap 47073.14 # Average gap between requests system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined system.physmem.memoryStateTime::IDLE 11000 # Time in different power states system.physmem.memoryStateTime::REF 520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem.memoryStateTime::ACT 15318250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 1348460292 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution @@ -233,15 +232,24 @@ system.membus.trans_dist::ReadExResp 78 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 833 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 833 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 26624 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 417 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 417 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 417 # Request fanout histogram system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.7 # Layer utilization (%) +system.membus.respLayer1.utilization 19.8 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 3423 # Number of BP lookups system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted @@ -254,7 +262,7 @@ system.cpu.branchPred.usedRAS 247 # Nu system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39489 # number of cpu cycles simulated +system.cpu.numCycles 39357 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss @@ -285,8 +293,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.086682 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393223 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked system.cpu.decode.RunCycles 3336 # Number of cycles decode is running @@ -409,7 +417,7 @@ system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 17897 # Type of FU issued -system.cpu.iq.rate 0.453215 # Inst issue rate +system.cpu.iq.rate 0.454735 # Inst issue rate system.cpu.iq.fu_busy_cnt 224 # FU busy when requested system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads @@ -453,13 +461,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3251 # number of memory reference insts executed system.cpu.iew.exec_branches 1662 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.428626 # Inst execution rate +system.cpu.iew.exec_rate 0.430063 # Inst execution rate system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit system.cpu.iew.wb_count 16374 # cumulative count of insts written-back system.cpu.iew.wb_producers 11006 # num instructions producing a value system.cpu.iew.wb_consumers 17135 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.414647 # insts written-back per cycle +system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit @@ -532,13 +540,13 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 41132 # The number of ROB reads system.cpu.rob.rob_writes 44928 # The number of ROB writes system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17596 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.339963 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.339963 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136240 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136240 # IPC: Total IPC of All Threads +system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads +system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 21340 # number of integer regfile reads system.cpu.int_regfile_writes 13120 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads @@ -546,7 +554,6 @@ system.cpu.cc_regfile_reads 8069 # nu system.cpu.cc_regfile_writes 5036 # number of cc regfile writes system.cpu.misc_regfile_reads 7491 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 1351701783 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 78 # Transaction distribution @@ -554,26 +561,38 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 78 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 552 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 283 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 835 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 26688 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.753616 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.753616 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064333 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064333 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id @@ -592,12 +611,12 @@ system.cpu.icache.demand_misses::cpu.inst 368 # n system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25386000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25386000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25386000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25386000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25386000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25386000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses @@ -610,12 +629,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68983.695652 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68983.695652 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68983.695652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68983.695652 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68983.695652 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,36 +655,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 276 system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19887250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19887250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19887250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19887250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19887250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19887250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72055.253623 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72055.253623 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72055.253623 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72055.253623 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.478116 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.827183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.650934 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004023 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000966 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004989 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id @@ -689,17 +708,17 @@ system.cpu.l2cache.demand_misses::total 417 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19600750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24547250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5508750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5508750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19600750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10455250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30056000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19600750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10455250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30056000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -722,17 +741,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997608 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71275.454545 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72410.766962 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70625 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70625 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72076.738609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71275.454545 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73628.521127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72076.738609 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -752,17 +771,17 @@ system.cpu.l2cache.demand_mshr_misses::total 417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16144250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20300250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16144250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24839500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16144250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24839500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses @@ -774,27 +793,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58706.363636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59882.743363 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58195.512821 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58195.512821 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58706.363636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61234.154930 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59567.146283 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.450988 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.450988 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020130 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020130 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id @@ -819,12 +838,12 @@ system.cpu.dcache.overall_misses::cpu.data 214 # system.cpu.dcache.overall_misses::total 214 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5769250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5769250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15584750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15584750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15584750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15584750 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) @@ -843,12 +862,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73964.743590 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73964.743590 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72825.934579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72825.934579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72825.934579 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -873,12 +892,12 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 142 system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5586750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5586750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10596250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10596250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10596250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10596250 # number of overall MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses @@ -889,12 +908,12 @@ system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71625 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71625 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74621.478873 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74621.478873 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt index 0a6735ef0..baff57318 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000006 # Nu sim_ticks 5615000 # Number of ticks simulated final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 478524 # Simulator instruction rate (inst/s) -host_op_rate 865796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 498092788 # Simulator tick rate (ticks/s) -host_mem_usage 271572 # Number of bytes of host memory used +host_inst_rate 365210 # Simulator instruction rate (inst/s) +host_op_rate 661016 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 380445830 # Simulator tick rate (ticks/s) +host_mem_usage 292780 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -35,9 +35,33 @@ system.physmem.bw_write::total 1266607302 # Wr system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 12304541407 # Throughput (bytes/s) -system.membus.data_through_bus 69090 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.trans_dist::ReadReq 7917 # Transaction distribution +system.membus.trans_dist::ReadResp 7917 # Transaction distribution +system.membus.trans_dist::WriteReq 935 # Transaction distribution +system.membus.trans_dist::WriteResp 935 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8852 # Request fanout histogram +system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram +system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram +system.membus.snoop_fanout::total 8852 # Request fanout histogram system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index bc4d8d180..8118efe8c 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000028 # Nu sim_ticks 28358000 # Number of ticks simulated final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 260669 # Simulator instruction rate (inst/s) -host_op_rate 471875 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1371807276 # Simulator tick rate (ticks/s) -host_mem_usage 281320 # Number of bytes of host memory used +host_inst_rate 307468 # Simulator instruction rate (inst/s) +host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1618053178 # Simulator tick rate (ticks/s) +host_mem_usage 302528 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -29,7 +29,6 @@ system.physmem.bw_inst_read::total 512306933 # In system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 814726003 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 282 # Transaction distribution system.membus.trans_dist::ReadResp 282 # Transaction distribution system.membus.trans_dist::ReadExReq 79 # Transaction distribution @@ -37,11 +36,20 @@ system.membus.trans_dist::ReadExResp 79 # Tr system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 23104 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 361 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 361 # Request fanout histogram system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) @@ -428,7 +436,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 816982862 # Throughput (bytes/s) system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -436,11 +443,23 @@ system.cpu.toL2Bus.trans_dist::ReadExResp 79 # T system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 456 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 268 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count::total 724 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 23168 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 14592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8576 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 342000 # Layer occupancy (ticks) |