diff options
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt')
| -rw-r--r-- | tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 1416 |
1 files changed, 708 insertions, 708 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 752a25834..3794759d9 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23754500 # Number of ticks simulated -final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25499500 # Number of ticks simulated +final_tick 25499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70868 # Simulator instruction rate (inst/s) -host_op_rate 70863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132078042 # Simulator tick rate (ticks/s) -host_mem_usage 294344 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 83845 # Simulator instruction rate (inst/s) +host_op_rate 83838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167736694 # Simulator tick rate (ticks/s) +host_mem_usage 294000 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory +system.physmem.bytes_read::total 62848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40704 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory +system.physmem.num_reads::total 982 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1596266593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 868409184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2464675778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1596266593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 868409184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2464675778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 982 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 982 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83 # Per bank write bursts -system.physmem.perBankRdBursts::1 151 # Per bank write bursts -system.physmem.perBankRdBursts::2 78 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 152 # Per bank write bursts +system.physmem.perBankRdBursts::2 79 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts system.physmem.perBankRdBursts::4 88 # Per bank write bursts system.physmem.perBankRdBursts::5 49 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 49 # Per bank write bursts -system.physmem.perBankRdBursts::8 41 # Per bank write bursts -system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::6 33 # Per bank write bursts +system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts system.physmem.perBankRdBursts::10 30 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 122 # Per bank write bursts -system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 120 # Per bank write bursts +system.physmem.perBankRdBursts::14 69 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23342000 # Total gap between requests +system.physmem.totGap 25359500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.readPktSize::6 982 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation -system.physmem.totQLat 12504500 # Total ticks spent queuing -system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.836364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.810990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.156672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 36.82% 36.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62 28.18% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 22 10.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.36% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 4.55% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.18% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.73% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.73% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 5.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 220 # Bytes accessed per row activation +system.physmem.totQLat 12877000 # Total ticks spent queuing +system.physmem.totMemAccLat 31289500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13113.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31863.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2464.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2464.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 20.52 # Data bus utilization in percentage -system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 19.26 # Data bus utilization in percentage +system.physmem.busUtilRead 19.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 763 # Number of row buffer hits during reads +system.physmem.readRowHits 752 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23940.51 # Average gap between requests -system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 25824.34 # Average gap between requests +system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 929880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 507375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4547400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ) -system.physmem_0.averagePower 1000.821593 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states +system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23657895 # Total energy per rank (pJ) +system.physmem_0.averagePower 1001.657370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 688500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 920.632125 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states +system.physmem_1.actBackEnergy 15503715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 591000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21359100 # Total energy per rank (pJ) +system.physmem_1.averagePower 903.085461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 888000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21996000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 7608 # Number of BP lookups -system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.lookups 7477 # Number of BP lookups +system.cpu.branchPred.condPredicted 4177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1616 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 15.740741 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 5192 # DTB read hits -system.cpu.dtb.read_misses 102 # DTB read misses +system.cpu.dtb.read_hits 4911 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 5294 # DTB read accesses -system.cpu.dtb.write_hits 2108 # DTB write hits -system.cpu.dtb.write_misses 66 # DTB write misses +system.cpu.dtb.read_accesses 5011 # DTB read accesses +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 69 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2174 # DTB write accesses -system.cpu.dtb.data_hits 7300 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2175 # DTB write accesses +system.cpu.dtb.data_hits 7017 # DTB hits +system.cpu.dtb.data_misses 169 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7468 # DTB accesses -system.cpu.itb.fetch_hits 5663 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 7186 # DTB accesses +system.cpu.itb.fetch_hits 5467 # ITB hits +system.cpu.itb.fetch_misses 60 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5720 # ITB accesses +system.cpu.itb.fetch_accesses 5527 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 47510 # number of cpu cycles simulated +system.cpu.numCycles 51000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 1416 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 41297 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7477 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1862 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10878 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 471 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5467 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 803 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.490920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.868697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20832 75.21% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 522 1.88% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 376 1.36% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 569 2.05% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 524 1.89% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 456 1.65% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 499 1.80% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 422 1.52% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3499 12.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.146608 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.809745 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36892 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11130 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5276 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1210 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 704 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 509 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1210 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37566 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5376 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5257 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4377 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30969 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 361 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 477 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3380 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23374 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 38597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 38579 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14234 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2267 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1410 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22900 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8231 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.826745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.538980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19213 69.36% 69.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2603 9.40% 78.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1960 7.08% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1418 5.12% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1237 4.47% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 696 2.51% 97.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 372 1.34% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 137 0.49% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 63 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27 8.23% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 211 64.33% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 90 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7493 65.81% 65.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2715 23.85% 89.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1173 10.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11915 # Type of FU issued +system.cpu.iq.FU_type_0::total 11386 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7630 66.27% 66.28% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2714 23.57% 89.88% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1165 10.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11442 # Type of FU issued -system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.491623 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11514 # Type of FU issued +system.cpu.iq.FU_type::total 22900 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.449020 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 168 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 328 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.006987 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007336 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.014323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73887 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 41585 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20089 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 23202 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1811 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 601 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 281 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 75 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1765 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 545 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1210 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27815 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2876 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 747 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21491 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2518 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2502 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 5020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 71 # number of nop insts executed -system.cpu.iew.exec_nop::1 73 # number of nop insts executed -system.cpu.iew.exec_nop::total 144 # number of nop insts executed -system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1763 # Number of branches executed -system.cpu.iew.exec_branches::1 1733 # Number of branches executed -system.cpu.iew.exec_branches::total 3496 # Number of branches executed -system.cpu.iew.exec_stores::0 1117 # Number of stores executed -system.cpu.iew.exec_stores::1 1079 # Number of stores executed -system.cpu.iew.exec_stores::total 2196 # Number of stores executed -system.cpu.iew.exec_rate 0.461419 # Inst execution rate -system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5390 # num instructions producing a value -system.cpu.iew.wb_producers::1 5243 # num instructions producing a value -system.cpu.iew.wb_producers::total 10633 # num instructions producing a value -system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 67 # number of nop insts executed +system.cpu.iew.exec_nop::total 136 # number of nop insts executed +system.cpu.iew.exec_refs::0 3616 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3607 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7223 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1734 # Number of branches executed +system.cpu.iew.exec_branches::1 1745 # Number of branches executed +system.cpu.iew.exec_branches::total 3479 # Number of branches executed +system.cpu.iew.exec_stores::0 1098 # Number of stores executed +system.cpu.iew.exec_stores::1 1105 # Number of stores executed +system.cpu.iew.exec_stores::total 2203 # Number of stores executed +system.cpu.iew.exec_rate 0.421392 # Inst execution rate +system.cpu.iew.wb_sent::0 10180 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10330 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9974 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 10135 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 20109 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5251 # num instructions producing a value +system.cpu.iew.wb_producers::1 5302 # num instructions producing a value +system.cpu.iew.wb_producers::total 10553 # num instructions producing a value +system.cpu.iew.wb_consumers::0 7044 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 7008 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 14052 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.195569 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.198725 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.394294 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.745457 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.756564 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.750996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1130 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.343029 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22639 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2318 8.39% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1067 3.86% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 382 1.38% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 325 1.18% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 202 0.73% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 0.75% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 146 0.53% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 325 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27612 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -707,28 +707,28 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133653 # The number of ROB reads -system.cpu.rob.rob_writes 59305 # The number of ROB writes -system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 130940 # The number of ROB reads +system.cpu.rob.rob_writes 58397 # The number of ROB writes +system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23301 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 27427 # number of integer regfile reads -system.cpu.int_regfile_writes 15512 # number of integer regfile writes +system.cpu.cpi::0 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi::1 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.001883 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26966 # number of integer regfile reads +system.cpu.int_regfile_writes 15368 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -736,289 +736,289 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.719872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 5036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.554913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits -system.cpu.dcache.overall_hits::total 5082 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses -system.cpu.dcache.overall_misses::total 1031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 213.719872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084473 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12454 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12454 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 4006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 4006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 5036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 5036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 5036 # number of overall hits +system.cpu.dcache.overall_hits::total 5036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses +system.cpu.dcache.overall_misses::total 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26557000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26557000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48843926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48843926 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75400926 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75400926 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4324 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4324 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 6054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 6054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 6054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 6054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5713 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.946154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 556 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 556 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # 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number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements::0 7 # number of replacements +system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # 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Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11936 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits -system.cpu.icache.overall_hits::total 4726 # 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number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5654 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5654 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5654 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5654 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.164132 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.164132 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.164132 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.164132 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69572.462284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69572.462284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69572.462284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69572.462284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4138 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 322.759154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.157597 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.157597 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 630 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 243 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.307617 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11558 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11558 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4537 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4537 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4537 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4537 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4537 # number of overall hits +system.cpu.icache.overall_hits::total 4537 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 923 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 923 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 923 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 923 # number of overall misses +system.cpu.icache.overall_misses::total 923 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70921745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70921745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70921745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70921745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70921745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70921745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5460 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169048 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.169048 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.169048 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.169048 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.169048 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.169048 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76838.293608 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76838.293608 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76838.293608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76838.293608 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.855422 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.724138 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46837996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46837996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46837996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46837996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46837996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46837996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111072 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.111072 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.111072 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74582.796178 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74582.796178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 285 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 285 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51664496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51664496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51664496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116850 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116850 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116850 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80978.833856 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80978.833856 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80978.833856 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80978.833856 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80978.833856 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80978.833856 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 443.003584 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 444.038251 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 838 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002387 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 321.314753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 121.688831 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009806 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013519 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 495 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 323.497640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 120.540612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 838 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 537 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025574 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8854 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8854 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 626 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 830 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # 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Layer utilization (%) -system.membus.trans_dist::ReadReq 830 # Transaction distribution -system.membus.trans_dist::ReadResp 830 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 838 # Transaction distribution +system.membus.trans_dist::ReadResp 838 # Transaction distribution +system.membus.trans_dist::ReadExReq 144 # Transaction distribution +system.membus.trans_dist::ReadExResp 144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 975 # Request fanout histogram +system.membus.snoop_fanout::samples 982 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 982 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 975 # Request fanout histogram -system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 38.1 # Layer utilization (%) +system.membus.snoop_fanout::total 982 # Request fanout histogram +system.membus.reqLayer0.occupancy 1219500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5224000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- |