diff options
Diffstat (limited to 'tests/quick/se/01.hello-2T-smt/ref/alpha')
3 files changed, 159 insertions, 158 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini index 431cc37fd..4cb5e1d1b 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,22 +31,18 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1 -BTBEntries=4096 -BTBTagSize=16 +children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 LFSTSize=1024 LQEntries=32 LSQCheckLoads=true LSQDepCheckShift=4 -RASSize=16 SQEntries=32 SSITSize=1024 activity=0 backComSize=5 +branchPred=system.cpu.branchPred cachePorts=200 checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 clock=500 commitToDecodeDelay=1 commitToFetchDelay=1 @@ -56,7 +53,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -69,22 +65,15 @@ forwardComSize=5 fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 iewToCommitDelay=1 iewToDecodeDelay=1 iewToFetchDelay=1 iewToRenameDelay=1 -instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa0 system.cpu.isa1 issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 @@ -96,7 +85,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=2 -predType=tournament profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -115,6 +103,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -124,6 +113,24 @@ workload=system.cpu.workload0 system.cpu.workload1 dcache_port=system.cpu.dcache.cpu_side icache_port=system.cpu.icache.cpu_side +[system.cpu.branchPred] +type=BranchPredictor +BTBEntries=4096 +BTBTagSize=16 +RASSize=16 +choiceCtrBits=2 +choicePredictorSize=8192 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +instShiftAmt=2 +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +numThreads=2 +predType=tournament + [system.cpu.dcache] type=BaseCache addr_ranges=0:18446744073709551615 @@ -131,21 +138,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -425,21 +427,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -448,6 +445,12 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=AlphaInterrupts +[system.cpu.isa0] +type=AlphaISA + +[system.cpu.isa1] +type=AlphaISA + [system.cpu.itb] type=AlphaTLB size=48 @@ -459,21 +462,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -500,7 +498,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -519,7 +517,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index d895f3126..d90ba5e01 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 1 2012 14:46:44 -gem5 started Nov 1 2012 15:18:34 -gem5 executing on u200540-lin +gem5 compiled Jan 23 2013 13:29:14 +gem5 started Jan 23 2013 13:39:20 +gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index b523abef7..18c747e94 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000020 # Nu sim_ticks 19857000 # Number of ticks simulated final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50642 # Simulator instruction rate (inst/s) -host_op_rate 50640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78893380 # Simulator tick rate (ticks/s) -host_mem_usage 214784 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 38427 # Simulator instruction rate (inst/s) +host_op_rate 38425 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59863252 # Simulator tick rate (ticks/s) +host_mem_usage 271256 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory @@ -185,6 +185,15 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 20387.35 # Average gap between requests +system.cpu.branchPred.lookups 6348 # Number of BP lookups +system.cpu.branchPred.condPredicted 3569 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1446 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4530 # Number of BTB lookups +system.cpu.branchPred.BTBHits 874 # Number of BTB hits +system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu.branchPred.BTBHitPct 19.293598 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 898 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -222,14 +231,6 @@ system.cpu.workload1.num_syscalls 17 # Nu system.cpu.numCycles 39715 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6348 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1446 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4530 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 874 # Number of BTB hits -system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 898 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 184 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered @@ -712,114 +713,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 60835.195200 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements::0 0 # number of replacements -system.cpu.dcache.replacements::1 0 # number of replacements -system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use -system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits -system.cpu.dcache.overall_hits::total 4387 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses -system.cpu.dcache.overall_misses::total 1035 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements @@ -947,5 +840,113 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47651.405145 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements::0 0 # number of replacements +system.cpu.dcache.replacements::1 0 # number of replacements +system.cpu.dcache.replacements::total 0 # number of replacements +system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use +system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits +system.cpu.dcache.overall_hits::total 4387 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses +system.cpu.dcache.overall_misses::total 1035 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |